1 /* 2 * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #ifndef __ASSEMBLER__ 11 #include <stdlib.h> 12 #endif 13 14 #include <arch.h> 15 16 #include "rcar_def.h" 17 18 /******************************************************************************* 19 * Platform binary types for linking 20 ******************************************************************************/ 21 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 22 #define PLATFORM_LINKER_ARCH aarch64 23 24 /******************************************************************************* 25 * Generic platform constants 26 ******************************************************************************/ 27 #define FIRMWARE_WELCOME_STR "Booting Rcar-gen3 Trusted Firmware\n" 28 29 /* Size of cacheable stacks */ 30 #if IMAGE_BL1 31 #if TRUSTED_BOARD_BOOT 32 #define PLATFORM_STACK_SIZE U(0x1000) 33 #else 34 #define PLATFORM_STACK_SIZE U(0x440) 35 #endif 36 #elif IMAGE_BL2 37 #if TRUSTED_BOARD_BOOT 38 #define PLATFORM_STACK_SIZE U(0x1000) 39 #else 40 #define PLATFORM_STACK_SIZE U(0x400) 41 #endif 42 #elif IMAGE_BL31 43 #define PLATFORM_STACK_SIZE U(0x400) 44 #elif IMAGE_BL32 45 #define PLATFORM_STACK_SIZE U(0x440) 46 #endif 47 48 #define BL332_IMAGE_ID (NS_BL2U_IMAGE_ID + 1) 49 #define BL333_IMAGE_ID (NS_BL2U_IMAGE_ID + 2) 50 #define BL334_IMAGE_ID (NS_BL2U_IMAGE_ID + 3) 51 #define BL335_IMAGE_ID (NS_BL2U_IMAGE_ID + 4) 52 #define BL336_IMAGE_ID (NS_BL2U_IMAGE_ID + 5) 53 #define BL337_IMAGE_ID (NS_BL2U_IMAGE_ID + 6) 54 #define BL338_IMAGE_ID (NS_BL2U_IMAGE_ID + 7) 55 56 #define BL332_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 8) 57 #define BL333_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 9) 58 #define BL334_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 10) 59 #define BL335_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 11) 60 #define BL336_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 12) 61 #define BL337_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 13) 62 #define BL338_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 14) 63 64 #define BL332_CERT_ID (NS_BL2U_IMAGE_ID + 15) 65 #define BL333_CERT_ID (NS_BL2U_IMAGE_ID + 16) 66 #define BL334_CERT_ID (NS_BL2U_IMAGE_ID + 17) 67 #define BL335_CERT_ID (NS_BL2U_IMAGE_ID + 18) 68 #define BL336_CERT_ID (NS_BL2U_IMAGE_ID + 19) 69 #define BL337_CERT_ID (NS_BL2U_IMAGE_ID + 20) 70 #define BL338_CERT_ID (NS_BL2U_IMAGE_ID + 21) 71 72 /* io drivers id */ 73 #define FLASH_DEV_ID U(0) 74 #define EMMC_DEV_ID U(1) 75 76 /* 77 * R-Car H3 Cortex-A57 78 * L1:I/48KB(16KBx3way) D/32KB(16KBx2way) L2:2MB(128KBx16way) 79 * Cortex-A53 80 * L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way) 81 */ 82 #define PLATFORM_CACHE_LINE_SIZE 64 83 #define PLATFORM_CLUSTER_COUNT U(2) 84 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 85 #define PLATFORM_CLUSTER1_CORE_COUNT U(4) 86 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 87 PLATFORM_CLUSTER0_CORE_COUNT) 88 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 89 90 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 91 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 92 PLATFORM_CLUSTER_COUNT + 1) 93 94 #define PLAT_MAX_RET_STATE U(1) 95 #define PLAT_MAX_OFF_STATE U(2) 96 97 #define MAX_IO_DEVICES U(3) 98 #define MAX_IO_HANDLES U(4) 99 100 /* 101 ****************************************************************************** 102 * BL2 specific defines. 103 ****************************************************************************** 104 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 105 * size plus a little space for growth. 106 */ 107 #define RCAR_SYSRAM_BASE U(0xE6300000) 108 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 109 #define BL2_LIMIT U(0xE6320000) 110 #else 111 #define BL2_LIMIT U(0xE6360000) 112 #endif 113 114 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 115 #define BL2_BASE U(0xE6304000) 116 #define BL2_IMAGE_LIMIT U(0xE6318000) 117 #elif (RCAR_LSI == RCAR_V3M) 118 #define BL2_BASE U(0xE6344000) 119 #define BL2_IMAGE_LIMIT U(0xE636E800) 120 #else 121 #define BL2_BASE U(0xE6304000) 122 #define BL2_IMAGE_LIMIT U(0xE632E800) 123 #endif 124 #define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE) 125 126 /* 127 ****************************************************************************** 128 * BL31 specific defines. 129 ****************************************************************************** 130 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 131 * current BL3-1 debug size plus a little space for growth. 132 */ 133 #define BL31_BASE (RCAR_TRUSTED_SRAM_BASE) 134 #define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE + \ 135 RCAR_TRUSTED_SRAM_SIZE) 136 #define RCAR_BL31_LOG_BASE (0x44040000) 137 #define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000) 138 #define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE) 139 #define BL31_SRAM_BASE (DEVICE_SRAM_BASE) 140 #define BL31_SRAM_LIMIT (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE) 141 142 /******************************************************************************* 143 * BL32 specific defines. 144 ******************************************************************************/ 145 #ifndef SPD_NONE 146 #define BL32_BASE U(0x44100000) 147 #define BL32_LIMIT (BL32_BASE + U(0x200000)) 148 #endif 149 150 /******************************************************************************* 151 * BL33 152 ******************************************************************************/ 153 #define BL33_BASE DRAM1_NS_BASE 154 #define BL33_COMP_SIZE U(0x200000) 155 #define BL33_COMP_BASE (BL33_BASE - BL33_COMP_SIZE) 156 157 /******************************************************************************* 158 * Platform specific page table and MMU setup constants 159 ******************************************************************************/ 160 #if IMAGE_BL1 161 #define MAX_XLAT_TABLES U(2) 162 #elif IMAGE_BL2 163 #define MAX_XLAT_TABLES U(5) 164 #elif IMAGE_BL31 165 #define MAX_XLAT_TABLES U(4) 166 #elif IMAGE_BL32 167 #define MAX_XLAT_TABLES U(3) 168 #endif 169 170 #if IMAGE_BL2 171 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40) 172 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) 173 #else 174 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 175 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 176 #endif 177 178 #define MAX_MMAP_REGIONS (RCAR_MMAP_ENTRIES + RCAR_BL_REGIONS) 179 180 /******************************************************************************* 181 * Declarations and constants to access the mailboxes safely. Each mailbox is 182 * aligned on the biggest cache line size in the platform. This is known only 183 * to the platform as it might have a combination of integrated and external 184 * caches. Such alignment ensures that two mailboxes do not sit on the same cache 185 * line at any cache level. They could belong to different cpus/clusters & 186 * get written while being protected by different locks causing corruption of 187 * a valid mailbox address. 188 ******************************************************************************/ 189 #define CACHE_WRITEBACK_SHIFT (6) 190 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 191 192 /******************************************************************************* 193 * Size of the per-cpu data in bytes that should be reserved in the generic 194 * per-cpu data structure for the RCAR port. 195 ******************************************************************************/ 196 #if !USE_COHERENT_MEM 197 #define PLAT_PCPU_DATA_SIZE (2) 198 #endif 199 200 #endif /* PLATFORM_DEF_H */ 201