1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef MCUCFG_H 7 #define MCUCFG_H 8 9 #include <stdint.h> 10 11 #include <mt8173_def.h> 12 13 struct mt8173_mcucfg_regs { 14 uint32_t mp0_ca7l_cache_config; 15 struct { 16 uint32_t mem_delsel0; 17 uint32_t mem_delsel1; 18 } mp0_cpu[4]; 19 uint32_t mp0_cache_mem_delsel0; 20 uint32_t mp0_cache_mem_delsel1; 21 uint32_t mp0_axi_config; 22 uint32_t mp0_misc_config[2]; 23 struct { 24 uint32_t rv_addr_lw; 25 uint32_t rv_addr_hw; 26 } mp0_rv_addr[4]; 27 uint32_t mp0_ca7l_cfg_dis; 28 uint32_t mp0_ca7l_clken_ctrl; 29 uint32_t mp0_ca7l_rst_ctrl; 30 uint32_t mp0_ca7l_misc_config; 31 uint32_t mp0_ca7l_dbg_pwr_ctrl; 32 uint32_t mp0_rw_rsvd0; 33 uint32_t mp0_rw_rsvd1; 34 uint32_t mp0_ro_rsvd; 35 uint32_t reserved0_0[100]; 36 uint32_t mp1_cpucfg; 37 uint32_t mp1_miscdbg; 38 uint32_t reserved0_1[13]; 39 uint32_t mp1_rst_ctl; 40 uint32_t mp1_clkenm_div; 41 uint32_t reserved0_2[7]; 42 uint32_t mp1_config_res; 43 uint32_t reserved0_3[13]; 44 struct { 45 uint32_t rv_addr_lw; 46 uint32_t rv_addr_hw; 47 } mp1_rv_addr[2]; 48 uint32_t reserved0_4[84]; 49 uint32_t mp0_rst_status; /* 0x400 */ 50 uint32_t mp0_dbg_ctrl; 51 uint32_t mp0_dbg_flag; 52 uint32_t mp0_ca7l_ir_mon; 53 struct { 54 uint32_t pc_lw; 55 uint32_t pc_hw; 56 uint32_t fp_arch32; 57 uint32_t sp_arch32; 58 uint32_t fp_arch64_lw; 59 uint32_t fp_arch64_hw; 60 uint32_t sp_arch64_lw; 61 uint32_t sp_arch64_hw; 62 } mp0_dbg_core[4]; 63 uint32_t dfd_ctrl; 64 uint32_t dfd_cnt_l; 65 uint32_t dfd_cnt_h; 66 uint32_t misccfg_mp0_rw_rsvd; 67 uint32_t misccfg_sec_vio_status0; 68 uint32_t misccfg_sec_vio_status1; 69 uint32_t reserved1[22]; 70 uint32_t misccfg_rw_rsvd; /* 0x500 */ 71 uint32_t mcusys_dbg_mon_sel_a; 72 uint32_t mcusys_dbg_mon; 73 uint32_t reserved2[61]; 74 uint32_t mcusys_config_a; /* 0x600 */ 75 uint32_t mcusys_config1_a; 76 uint32_t mcusys_gic_peribase_a; 77 uint32_t reserved3; 78 uint32_t sec_range0_start; /* 0x610 */ 79 uint32_t sec_range0_end; 80 uint32_t sec_range_enable; 81 uint32_t reserved4; 82 uint32_t int_pol_ctl[8]; /* 0x620 */ 83 uint32_t aclken_div; /* 0x640 */ 84 uint32_t pclken_div; 85 uint32_t l2c_sram_ctrl; 86 uint32_t armpll_jit_ctrl; 87 uint32_t cci_addrmap; /* 0x650 */ 88 uint32_t cci_config; 89 uint32_t cci_periphbase; 90 uint32_t cci_nevntcntovfl; 91 uint32_t cci_clk_ctrl; /* 0x660 */ 92 uint32_t cci_acel_s1_ctrl; 93 uint32_t bus_fabric_dcm_ctrl; 94 uint32_t reserved5; 95 uint32_t xgpt_ctl; /* 0x670 */ 96 uint32_t xgpt_idx; 97 uint32_t ptpod2_ctl0; 98 uint32_t ptpod2_ctl1; 99 uint32_t mcusys_revid; 100 uint32_t mcusys_rw_rsvd0; 101 uint32_t mcusys_rw_rsvd1; 102 }; 103 104 static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE; 105 106 /* cpu boot mode */ 107 #define MP0_CPUCFG_64BIT_SHIFT 12 108 #define MP1_CPUCFG_64BIT_SHIFT 28 109 #define MP0_CPUCFG_64BIT (U(0xf) << MP0_CPUCFG_64BIT_SHIFT) 110 #define MP1_CPUCFG_64BIT (U(0xf) << MP1_CPUCFG_64BIT_SHIFT) 111 112 /* scu related */ 113 enum { 114 MP0_ACINACTM_SHIFT = 4, 115 MP1_ACINACTM_SHIFT = 0, 116 MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT, 117 MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT 118 }; 119 120 enum { 121 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0, 122 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4, 123 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8, 124 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12, 125 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16, 126 127 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = 128 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, 129 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = 130 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, 131 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = 132 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, 133 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = 134 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, 135 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = 136 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT 137 }; 138 139 enum { 140 MP1_AINACTS_SHIFT = 4, 141 MP1_AINACTS = 1 << MP1_AINACTS_SHIFT 142 }; 143 144 enum { 145 MP1_SW_CG_GEN_SHIFT = 12, 146 MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT 147 }; 148 149 enum { 150 MP1_L2RSTDISABLE_SHIFT = 14, 151 MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT 152 }; 153 154 /* cci clock control related */ 155 enum { 156 MCU_BUS_DCM_EN = 1 << 8 157 }; 158 159 /* l2c sram control related */ 160 enum { 161 L2C_SRAM_DCM_EN = 1 << 0 162 }; 163 164 /* bus fabric dcm control related */ 165 enum { 166 PSYS_ADB400_DCM_EN = 1 << 29, 167 GPU_ADB400_DCM_EN = 1 << 28, 168 169 EMI1_ADB400_DCM_EN = 1 << 27, 170 EMI_ADB400_DCM_EN = 1 << 26, 171 INFRA_ADB400_DCM_EN = 1 << 25, 172 L2C_ADB400_DCM_EN = 1 << 24, 173 174 MP0_ADB400_DCM_EN = 1 << 23, 175 CCI400_CK_ONLY_DCM_EN = 1 << 22, 176 L2C_IDLE_DCM_EN = 1 << 21, 177 178 CA15U_ADB_DYNAMIC_CG_EN = 1 << 19, 179 CA7L_ADB_DYNAMIC_CG_EN = 1 << 18, 180 L2C_ADB_DYNAMIC_CG_EN = 1 << 17, 181 182 EMICLK_EMI1_DYNAMIC_CG_EN = 1 << 12, 183 184 INFRACLK_PSYS_DYNAMIC_CG_EN = 1 << 11, 185 EMICLK_GPU_DYNAMIC_CG_EN = 1 << 10, 186 EMICLK_EMI_DYNAMIC_CG_EN = 1 << 8, 187 188 CCI400_SLV_RW_DCM_EN = 1 << 7, 189 CCI400_SLV_DCM_EN = 1 << 5, 190 191 ACLK_PSYS_DYNAMIC_CG_EN = 1 << 3, 192 ACLK_GPU_DYNAMIC_CG_EN = 1 << 2, 193 ACLK_EMI_DYNAMIC_CG_EN = 1 << 1, 194 ACLK_INFRA_DYNAMIC_CG_EN = 1 << 0, 195 196 /* adb400 related */ 197 ADB400_GRP_DCM_EN = PSYS_ADB400_DCM_EN | GPU_ADB400_DCM_EN | 198 EMI1_ADB400_DCM_EN | EMI_ADB400_DCM_EN | 199 INFRA_ADB400_DCM_EN | L2C_ADB400_DCM_EN | 200 MP0_ADB400_DCM_EN, 201 202 /* cci400 related */ 203 CCI400_GRP_DCM_EN = CCI400_CK_ONLY_DCM_EN | CCI400_SLV_RW_DCM_EN | 204 CCI400_SLV_DCM_EN, 205 206 /* adb clock related */ 207 ADBCLK_GRP_DCM_EN = CA15U_ADB_DYNAMIC_CG_EN | CA7L_ADB_DYNAMIC_CG_EN | 208 L2C_ADB_DYNAMIC_CG_EN, 209 210 /* emi clock related */ 211 EMICLK_GRP_DCM_EN = EMICLK_EMI1_DYNAMIC_CG_EN | 212 EMICLK_GPU_DYNAMIC_CG_EN | 213 EMICLK_EMI_DYNAMIC_CG_EN, 214 215 /* bus clock related */ 216 ACLK_GRP_DCM_EN = ACLK_PSYS_DYNAMIC_CG_EN | ACLK_GPU_DYNAMIC_CG_EN | 217 ACLK_EMI_DYNAMIC_CG_EN | ACLK_INFRA_DYNAMIC_CG_EN, 218 }; 219 220 #endif /* MCUCFG_H */ 221