1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * sun9i clock register definitions 4 * 5 * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> 6 */ 7 8 #ifndef _SUNXI_CLOCK_SUN9I_H 9 #define _SUNXI_CLOCK_SUN9I_H 10 11 #ifndef __ASSEMBLY__ 12 #include <linux/bitops.h> 13 #endif 14 15 struct sunxi_ccm_reg { 16 u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */ 17 u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */ 18 u32 pll3_audio_cfg; /* 0x08 audio pll configuration */ 19 u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */ 20 u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */ 21 u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */ 22 u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */ 23 u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */ 24 u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */ 25 u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */ 26 u32 pll11_isp_cfg; /* 0x28 isp pll6 ontrol */ 27 u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */ 28 u8 reserved1[0x20]; /* 0x30 */ 29 u32 cpu_clk_source; /* 0x50 cpu clk source configuration */ 30 u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */ 31 u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */ 32 u32 gtbus_cfg; /* 0x5c gtbus clock configuration */ 33 u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */ 34 u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */ 35 u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */ 36 u8 reserved2[0x04]; /* 0x6c */ 37 u32 apb0_cfg; /* 0x70 apb0 clock configuration */ 38 u32 apb1_cfg; /* 0x74 apb1 clock configuration */ 39 u32 cci400_cfg; /* 0x78 cci400 clock configuration */ 40 u8 reserved3[0x04]; /* 0x7c */ 41 u32 ats_cfg; /* 0x80 ats clock configuration */ 42 u32 trace_cfg; /* 0x84 trace clock configuration */ 43 u8 reserved4[0x14]; /* 0x88 */ 44 u32 pll_stable_status; /* 0x9c */ 45 u8 reserved5[0xe0]; /* 0xa0 */ 46 u32 clk_output_a; /* 0x180 clk_output_a */ 47 u32 clk_output_b; /* 0x184 clk_output_a */ 48 u8 reserved6[0x278]; /* 0x188 */ 49 50 u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */ 51 u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */ 52 u8 reserved7[0x08]; /* 0x408 */ 53 u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */ 54 u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */ 55 u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */ 56 u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */ 57 u8 reserved8[0x08]; /* 0x420 */ 58 u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */ 59 u32 ss_clk_cfg; /* 0x42c security system clock cfg */ 60 u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */ 61 u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */ 62 u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */ 63 u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */ 64 u8 reserved9[0x44]; /* 0x440 */ 65 u32 dram_clk_cfg; /* 0x484 DRAM (controller) clock config */ 66 u8 reserved10[0x8]; /* 0x488 */ 67 u32 de_clk_cfg; /* 0x490 display engine clock configuration */ 68 u8 reserved11[0x04]; /* 0x494 */ 69 u32 mp_clk_cfg; /* 0x498 mp clock configuration */ 70 u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */ 71 u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */ 72 u8 reserved12[0x1c]; /* 0x4a4 */ 73 u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */ 74 u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */ 75 u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */ 76 u32 fd_clk_cfg; /* 0x4cc FD module clock */ 77 u32 ve_clk_cfg; /* 0x4d0 VE module clock */ 78 u32 avs_clk_cfg; /* 0x4d4 AVS module clock */ 79 u8 reserved13[0x18]; /* 0x4d8 */ 80 u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */ 81 u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */ 82 u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */ 83 u8 reserved14[0x10]; /* 0x4fc */ 84 u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */ 85 u8 reserved15[0x70]; /* 0x510 */ 86 87 u32 ahb_gate0; /* 0x580 AHB0 Gating Register */ 88 u32 ahb_gate1; /* 0x584 AHB1 Gating Register */ 89 u32 ahb_gate2; /* 0x588 AHB2 Gating Register */ 90 u8 reserved16[0x04]; /* 0x58c */ 91 u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */ 92 u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */ 93 u8 reserved17[0x08]; /* 0x598 */ 94 u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */ 95 u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */ 96 u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */ 97 u8 reserved18[0x04]; /* 0x5ac */ 98 u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */ 99 u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */ 100 }; 101 102 #define CCM_PLL4_CTRL_N_SHIFT 8 103 #define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT) 104 #define CCM_PLL4_CTRL_P_SHIFT 16 105 #define CCM_PLL4_CTRL_P_MASK (0x1 << CCM_PLL4_CTRL_P_SHIFT) 106 #define CCM_PLL4_CTRL_M_SHIFT 18 107 #define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT) 108 109 /* pllx_cfg bits */ 110 #define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8) 111 #define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16) 112 #define CCM_PLL1_CTRL_EN (1 << 31) 113 #define CCM_PLL1_CLOCK_TIME_2 (2 << 24) 114 115 #define CCM_PLL2_CTRL_N(n) (((n) & 0xff) << 8) 116 #define CCM_PLL2_CTRL_P(n) (((n) & 0x1) << 16) 117 #define CCM_PLL2_CTRL_EN (1 << 31) 118 #define CCM_PLL2_CLOCK_TIME_2 (2 << 24) 119 120 #define CCM_PLL4_CTRL_N(n) (((n) & 0xff) << 8) 121 #define CCM_PLL4_CTRL_EN (1 << 31) 122 123 #define CCM_PLL6_CTRL_N(n) (((n) & 0xff) << 8) 124 #define CCM_PLL6_CTRL_P(p) (((p) & 0x1) << 16) 125 #define CCM_PLL6_CTRL_EN (1 << 31) 126 #define CCM_PLL6_CFG_UPDATE (1 << 30) 127 128 #define CCM_PLL12_CTRL_N(n) (((n) & 0xff) << 8) 129 #define CCM_PLL12_CTRL_EN (1 << 31) 130 131 #define PLL_C0CPUX_STATUS (1 << 0) 132 #define PLL_C1CPUX_STATUS (1 << 1) 133 #define PLL_DDR_STATUS (1 << 5) 134 #define PLL_PERIPH1_STATUS (1 << 11) 135 136 /* cpu_clk_source bits */ 137 #define C0_CPUX_CLK_SRC_SHIFT 0 138 #define C1_CPUX_CLK_SRC_SHIFT 8 139 #define C0_CPUX_CLK_SRC_MASK (1 << C0_CPUX_CLK_SRC_SHIFT) 140 #define C1_CPUX_CLK_SRC_MASK (1 << C1_CPUX_CLK_SRC_SHIFT) 141 #define C0_CPUX_CLK_SRC_OSC24M (0 << C0_CPUX_CLK_SRC_SHIFT) 142 #define C0_CPUX_CLK_SRC_PLL1 (1 << C0_CPUX_CLK_SRC_SHIFT) 143 #define C1_CPUX_CLK_SRC_OSC24M (0 << C1_CPUX_CLK_SRC_SHIFT) 144 #define C1_CPUX_CLK_SRC_PLL2 (1 << C1_CPUX_CLK_SRC_SHIFT) 145 146 /* c0_cfg */ 147 #define C0_CFG_AXI0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) 148 #define C0_CFG_APB0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 8) 149 150 /* ahbx_cfg */ 151 #define AHBx_SRC_CLK_SELECT_SHIFT 24 152 #define AHBx_SRC_MASK (0x3 << AHBx_SRC_CLK_SELECT_SHIFT) 153 #define AHB0_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) 154 #define AHB1_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) 155 #define AHB2_SRC_OSC24M (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) 156 #define AHBx_SRC_PLL_PERIPH0 (0x1 << AHBx_SRC_CLK_SELECT_SHIFT) 157 #define AHBx_SRC_PLL_PERIPH1 (0x2 << AHBx_SRC_CLK_SELECT_SHIFT) 158 #define AHBx_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0) 159 160 /* apb0_cfg */ 161 #define APB0_SRC_CLK_SELECT_SHIFT 24 162 #define APB0_SRC_MASK (0x1 << APB0_SRC_CLK_SELECT_SHIFT) 163 #define APB0_SRC_OSC24M (0x0 << APB0_SRC_CLK_SELECT_SHIFT) 164 #define APB0_SRC_PLL_PERIPH0 (0x1 << APB0_SRC_CLK_SELECT_SHIFT) 165 #define APB0_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0) 166 167 /* gtbus_clk_cfg */ 168 #define GTBUS_SRC_CLK_SELECT_SHIFT 24 169 #define GTBUS_SRC_MASK (0x3 << GTBUS_SRC_CLK_SELECT_SHIFT) 170 #define GTBUS_SRC_OSC24M (0x0 << GTBUS_SRC_CLK_SELECT_SHIFT) 171 #define GTBUS_SRC_PLL_PERIPH0 (0x1 << GTBUS_SRC_CLK_SELECT_SHIFT) 172 #define GTBUS_SRC_PLL_PERIPH1 (0x2 << GTBUS_SRC_CLK_SELECT_SHIFT) 173 #define GTBUS_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) 174 175 /* cci400_clk_cfg */ 176 #define CCI400_SRC_CLK_SELECT_SHIFT 24 177 #define CCI400_SRC_MASK (0x3 << CCI400_SRC_CLK_SELECT_SHIFT) 178 #define CCI400_SRC_OSC24M (0x0 << CCI400_SRC_CLK_SELECT_SHIFT) 179 #define CCI400_SRC_PLL_PERIPH0 (0x1 << CCI400_SRC_CLK_SELECT_SHIFT) 180 #define CCI400_SRC_PLL_PERIPH1 (0x2 << CCI400_SRC_CLK_SELECT_SHIFT) 181 #define CCI400_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) 182 183 /* sd#_clk_cfg fields */ 184 #define CCM_MMC_CTRL_M(x) ((x) - 1) 185 #define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) 186 #define CCM_MMC_CTRL_N(x) ((x) << 16) 187 #define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) 188 #define CCM_MMC_CTRL_OSCM24 (0 << 24) 189 #define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24) 190 #define CCM_MMC_CTRL_ENABLE (1 << 31) 191 192 /* ahb_gate0 fields */ 193 #define AHB_GATE_OFFSET_MCTL 14 194 195 /* On sun9i all sdc-s share their ahb gate, so ignore (x) */ 196 #define AHB_GATE_OFFSET_NAND0 13 197 #define AHB_GATE_OFFSET_MMC(x) 8 198 199 /* ahb gate1 field */ 200 #define AHB_GATE_OFFSET_DMA 24 201 202 /* apb1_gate fields */ 203 #define APB1_GATE_UART_SHIFT 16 204 #define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) 205 #define APB1_GATE_TWI_SHIFT 0 206 #define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) 207 208 /* ahb_reset0_cfg fields */ 209 #define AHB_RESET_OFFSET_MCTL 14 210 211 /* On sun9i all sdc-s share their ahb reset, so ignore (x) */ 212 #define AHB_RESET_OFFSET_MMC(x) 8 213 214 /* apb1_reset_cfg fields */ 215 #define APB1_RESET_UART_SHIFT 16 216 #define APB1_RESET_UART_MASK (0xff << APB1_RESET_UART_SHIFT) 217 #define APB1_RESET_TWI_SHIFT 0 218 #define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) 219 220 221 #ifndef __ASSEMBLY__ 222 void clock_set_pll1(unsigned int clk); 223 void clock_set_pll2(unsigned int clk); 224 void clock_set_pll4(unsigned int clk); 225 void clock_set_pll6(unsigned int clk); 226 void clock_set_pll12(unsigned int clk); 227 unsigned int clock_get_pll4_periph0(void); 228 #endif 229 230 #endif /* _SUNXI_CLOCK_SUN9I_H */ 231