1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright 2016 Chen-Yu Tsai
4  *
5  * Chen-Yu Tsai <wens@csie.org>
6  */
7 
8 #ifndef _CCU_SUN9I_A80_H_
9 #define _CCU_SUN9I_A80_H_
10 
11 #include <dt-bindings/clock/sun9i-a80-ccu.h>
12 #include <dt-bindings/reset/sun9i-a80-ccu.h>
13 
14 #define CLK_PLL_C0CPUX		0
15 #define CLK_PLL_C1CPUX		1
16 
17 /* pll-audio and pll-periph0 are exported to the PRCM block */
18 
19 #define CLK_PLL_VE		4
20 #define CLK_PLL_DDR		5
21 #define CLK_PLL_VIDEO0		6
22 #define CLK_PLL_VIDEO1		7
23 #define CLK_PLL_GPU		8
24 #define CLK_PLL_DE		9
25 #define CLK_PLL_ISP		10
26 #define CLK_PLL_PERIPH1		11
27 
28 /* The CPUX clocks are exported */
29 
30 #define CLK_ATB0		14
31 #define CLK_AXI0		15
32 #define CLK_ATB1		16
33 #define CLK_AXI1		17
34 #define CLK_GTBUS		18
35 #define CLK_AHB0		19
36 #define CLK_AHB1		20
37 #define CLK_AHB2		21
38 #define CLK_APB0		22
39 #define CLK_APB1		23
40 #define CLK_CCI400		24
41 #define CLK_ATS			25
42 #define CLK_TRACE		26
43 
44 /* module clocks and bus gates exported */
45 
46 #define CLK_NUMBER		(CLK_BUS_UART5 + 1)
47 
48 #endif /* _CCU_SUN9I_A80_H_ */
49