1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Actions Semi SoCs Clock Definitions
4  *
5  * Copyright (C) 2015 Actions Semi Co., Ltd.
6  * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7  *
8  */
9 
10 #ifndef _OWL_CLK_H_
11 #define _OWL_CLK_H_
12 
13 #include <clk-uclass.h>
14 #ifndef __ASSEMBLY__
15 #include <linux/bitops.h>
16 #endif
17 
18 enum owl_soc {
19 	S700,
20 	S900,
21 };
22 
23 struct owl_clk_priv {
24 	phys_addr_t base;
25 };
26 
27 /* BUSCLK register definitions */
28 #define CMU_PDBGDIV_8		7
29 #define CMU_PDBGDIV_SHIFT	26
30 #define CMU_PDBGDIV_DIV		(CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
31 #define CMU_PERDIV_8		7
32 #define CMU_PERDIV_SHIFT	20
33 #define CMU_PERDIV_DIV		(CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
34 #define CMU_NOCDIV_2		1
35 #define CMU_NOCDIV_SHIFT	19
36 #define CMU_NOCDIV_DIV		(CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
37 #define CMU_DMMCLK_SRC_APLL	2
38 #define CMU_DMMCLK_SRC_SHIFT	10
39 #define CMU_DMMCLK_SRC		(CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT)
40 #define CMU_APBCLK_DIV		BIT(8)
41 #define CMU_NOCCLK_SRC		BIT(7)
42 #define CMU_AHBCLK_DIV		BIT(4)
43 #define CMU_CORECLK_MASK	3
44 #define CMU_CORECLK_CPLL	BIT(1)
45 #define CMU_CORECLK_HOSC	BIT(0)
46 
47 /* COREPLL register definitions */
48 #define CMU_COREPLL_EN		BIT(9)
49 #define CMU_COREPLL_HOSC_EN	BIT(8)
50 #define CMU_COREPLL_OUT		(1104 / 24)
51 
52 /* DEVPLL register definitions */
53 #define CMU_DEVPLL_CLK		BIT(12)
54 #define CMU_DEVPLL_EN		BIT(8)
55 #define CMU_DEVPLL_OUT		(660 / 6)
56 
57 /* UARTCLK register definitions */
58 #define CMU_UARTCLK_SRC_DEVPLL	BIT(16)
59 
60 #define PLL_STABILITY_WAIT_US	50
61 
62 #define CMU_DEVCLKEN1_UART5	BIT(21)
63 #define CMU_DEVCLKEN1_UART3	BIT(11)
64 
65 #endif
66