1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef __SOC_MEDIATEK_MTK_MMSYS_H
4 #define __SOC_MEDIATEK_MTK_MMSYS_H
5 
6 #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
7 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
8 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
9 #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
10 #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
11 #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
12 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
13 #define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
14 #define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
15 #define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
16 #define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
17 #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
18 #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
19 #define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
20 
21 #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
22 #define DISP_REG_CONFIG_OUT_SEL			0x04c
23 #define DISP_REG_CONFIG_DSI_SEL			0x050
24 #define DISP_REG_CONFIG_DPI_SEL			0x064
25 
26 #define OVL0_MOUT_EN_COLOR0			0x1
27 #define OD_MOUT_EN_RDMA0			0x1
28 #define OD1_MOUT_EN_RDMA1			BIT(16)
29 #define UFOE_MOUT_EN_DSI0			0x1
30 #define COLOR0_SEL_IN_OVL0			0x1
31 #define OVL1_MOUT_EN_COLOR1			0x1
32 #define GAMMA_MOUT_EN_RDMA1			0x1
33 #define RDMA0_SOUT_DPI0				0x2
34 #define RDMA0_SOUT_DPI1				0x3
35 #define RDMA0_SOUT_DSI1				0x1
36 #define RDMA0_SOUT_DSI2				0x4
37 #define RDMA0_SOUT_DSI3				0x5
38 #define RDMA0_SOUT_MASK				0x7
39 #define RDMA1_SOUT_DPI0				0x2
40 #define RDMA1_SOUT_DPI1				0x3
41 #define RDMA1_SOUT_DSI1				0x1
42 #define RDMA1_SOUT_DSI2				0x4
43 #define RDMA1_SOUT_DSI3				0x5
44 #define RDMA1_SOUT_MASK				0x7
45 #define RDMA2_SOUT_DPI0				0x2
46 #define RDMA2_SOUT_DPI1				0x3
47 #define RDMA2_SOUT_DSI1				0x1
48 #define RDMA2_SOUT_DSI2				0x4
49 #define RDMA2_SOUT_DSI3				0x5
50 #define RDMA2_SOUT_MASK				0x7
51 #define DPI0_SEL_IN_RDMA1			0x1
52 #define DPI0_SEL_IN_RDMA2			0x3
53 #define DPI0_SEL_IN_MASK			0x3
54 #define DPI1_SEL_IN_RDMA1			(0x1 << 8)
55 #define DPI1_SEL_IN_RDMA2			(0x3 << 8)
56 #define DPI1_SEL_IN_MASK			(0x3 << 8)
57 #define DSI0_SEL_IN_RDMA1			0x1
58 #define DSI0_SEL_IN_RDMA2			0x4
59 #define DSI0_SEL_IN_MASK			0x7
60 #define DSI1_SEL_IN_RDMA1			0x1
61 #define DSI1_SEL_IN_RDMA2			0x4
62 #define DSI1_SEL_IN_MASK			0x7
63 #define DSI2_SEL_IN_RDMA1			(0x1 << 16)
64 #define DSI2_SEL_IN_RDMA2			(0x4 << 16)
65 #define DSI2_SEL_IN_MASK			(0x7 << 16)
66 #define DSI3_SEL_IN_RDMA1			(0x1 << 16)
67 #define DSI3_SEL_IN_RDMA2			(0x4 << 16)
68 #define DSI3_SEL_IN_MASK			(0x7 << 16)
69 #define COLOR1_SEL_IN_OVL1			0x1
70 
71 #define OVL_MOUT_EN_RDMA			0x1
72 #define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
73 #define BLS_TO_DPI_RDMA1_TO_DSI			0x2
74 #define BLS_RDMA1_DSI_DPI_MASK			0xf
75 #define DSI_SEL_IN_BLS				0x0
76 #define DPI_SEL_IN_BLS				0x0
77 #define DPI_SEL_IN_MASK				0x1
78 #define DSI_SEL_IN_RDMA				0x1
79 #define DSI_SEL_IN_MASK				0x1
80 
81 #define MMSYS_SW0_RST_B				0x140
82 
83 struct mtk_mmsys_routes {
84 	u32 from_comp;
85 	u32 to_comp;
86 	u32 addr;
87 	u32 mask;
88 	u32 val;
89 };
90 
91 struct mtk_mmsys_driver_data {
92 	const char *clk_driver;
93 	const struct mtk_mmsys_routes *routes;
94 	const unsigned int num_routes;
95 };
96 
97 /*
98  * Routes in mt8173, mt2701, mt2712 are different. That means
99  * in the same register address, it controls different input/output
100  * selection for each SoC. But, right now, they use the same table as
101  * default routes meet their requirements. But we don't have the complete
102  * route information for these three SoC, so just keep them in the same
103  * table. After we've more information, we could separate mt2701, mt2712
104  * to an independent table.
105  */
106 static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
107 	{
108 		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
109 		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
110 		BLS_TO_DSI_RDMA1_TO_DPI1
111 	}, {
112 		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
113 		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
114 		DSI_SEL_IN_BLS
115 	}, {
116 		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
117 		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
118 		BLS_TO_DPI_RDMA1_TO_DSI
119 	}, {
120 		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
121 		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
122 		DSI_SEL_IN_RDMA
123 	}, {
124 		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
125 		DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
126 		DPI_SEL_IN_BLS
127 	}, {
128 		DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
129 		DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
130 		GAMMA_MOUT_EN_RDMA1
131 	}, {
132 		DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
133 		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
134 		OD_MOUT_EN_RDMA0
135 	}, {
136 		DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
137 		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
138 		OD1_MOUT_EN_RDMA1
139 	}, {
140 		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
141 		DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
142 		OVL0_MOUT_EN_COLOR0
143 	}, {
144 		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
145 		DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
146 		COLOR0_SEL_IN_OVL0
147 	}, {
148 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
149 		DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
150 		OVL_MOUT_EN_RDMA
151 	}, {
152 		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
153 		DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
154 		OVL1_MOUT_EN_COLOR1
155 	}, {
156 		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
157 		DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
158 		COLOR1_SEL_IN_OVL1
159 	}, {
160 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
161 		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
162 		RDMA0_SOUT_DPI0
163 	}, {
164 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
165 		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
166 		RDMA0_SOUT_DPI1
167 	}, {
168 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
169 		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
170 		RDMA0_SOUT_DSI1
171 	}, {
172 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
173 		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
174 		RDMA0_SOUT_DSI2
175 	}, {
176 		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
177 		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
178 		RDMA0_SOUT_DSI3
179 	}, {
180 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
181 		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
182 		RDMA1_SOUT_DPI0
183 	}, {
184 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
185 		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
186 		DPI0_SEL_IN_RDMA1
187 	}, {
188 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
189 		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
190 		RDMA1_SOUT_DPI1
191 	}, {
192 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
193 		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
194 		DPI1_SEL_IN_RDMA1
195 	}, {
196 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
197 		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
198 		DSI0_SEL_IN_RDMA1
199 	}, {
200 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
201 		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
202 		RDMA1_SOUT_DSI1
203 	}, {
204 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
205 		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
206 		DSI1_SEL_IN_RDMA1
207 	}, {
208 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
209 		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
210 		RDMA1_SOUT_DSI2
211 	}, {
212 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
213 		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
214 		DSI2_SEL_IN_RDMA1
215 	}, {
216 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
217 		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
218 		RDMA1_SOUT_DSI3
219 	}, {
220 		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
221 		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
222 		DSI3_SEL_IN_RDMA1
223 	}, {
224 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
225 		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
226 		RDMA2_SOUT_DPI0
227 	}, {
228 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
229 		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
230 		DPI0_SEL_IN_RDMA2
231 	}, {
232 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
233 		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
234 		RDMA2_SOUT_DPI1
235 	}, {
236 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
237 		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
238 		DPI1_SEL_IN_RDMA2
239 	}, {
240 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
241 		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
242 		DSI0_SEL_IN_RDMA2
243 	}, {
244 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
245 		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
246 		RDMA2_SOUT_DSI1
247 	}, {
248 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
249 		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
250 		DSI1_SEL_IN_RDMA2
251 	}, {
252 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
253 		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
254 		RDMA2_SOUT_DSI2
255 	}, {
256 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
257 		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
258 		DSI2_SEL_IN_RDMA2
259 	}, {
260 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
261 		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
262 		RDMA2_SOUT_DSI3
263 	}, {
264 		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
265 		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
266 		DSI3_SEL_IN_RDMA2
267 	}, {
268 		DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
269 		DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,
270 		UFOE_MOUT_EN_DSI0
271 	}
272 };
273 
274 #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
275