1config ARCH_LS1021A 2 bool 3 select SYS_FSL_DDR_BE if SYS_FSL_DDR 4 select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR 5 select SYS_FSL_ERRATUM_A008378 6 select SYS_FSL_ERRATUM_A008407 7 select SYS_FSL_ERRATUM_A008850 8 select SYS_FSL_ERRATUM_A008997 if USB 9 select SYS_FSL_ERRATUM_A009007 if USB 10 select SYS_FSL_ERRATUM_A009008 if USB 11 select SYS_FSL_ERRATUM_A009663 12 select SYS_FSL_ERRATUM_A009798 if USB 13 select SYS_FSL_ERRATUM_A009942 14 select SYS_FSL_ERRATUM_A010315 15 select SYS_FSL_HAS_CCI400 16 select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR 17 select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR 18 select SYS_FSL_HAS_SEC 19 select SYS_FSL_SEC_COMPAT_5 20 select SYS_FSL_SEC_LE 21 select SYS_FSL_SRDS_1 22 select SYS_HAS_SERDES 23 imply CMD_PCI 24 imply SCSI 25 imply SCSI_AHCI 26 27menu "LS102xA architecture" 28 depends on ARCH_LS1021A 29 30config LS1_DEEP_SLEEP 31 bool "Deep sleep" 32 33config MAX_CPUS 34 int "Maximum number of CPUs permitted for LS102xA" 35 default 2 36 help 37 Set this number to the maximum number of possible CPUs in the SoC. 38 SoCs may have multiple clusters with each cluster may have multiple 39 ports. If some ports are reserved but higher ports are used for 40 cores, count the reserved ports. This will allocate enough memory 41 in spin table to properly handle all cores. 42 43config NXP_ESBC 44 bool "NXP_ESBC" 45 help 46 Enable Freescale Secure Boot feature. Normally selected 47 by defconfig. If unsure, do not change. 48 49config SYS_CCI400_OFFSET 50 hex "Offset for CCI400 base" 51 depends on SYS_FSL_HAS_CCI400 52 default 0x180000 53 help 54 Offset for CCI400 base. 55 CCI400 base addr = CCSRBAR + CCI400_OFFSET 56 57config SYS_FSL_ERRATUM_A008850 58 bool 59 help 60 Workaround for DDR erratum A008850 61 62config SYS_FSL_ERRATUM_A008997 63 bool 64 help 65 Workaround for USB PHY erratum A008997 66 67config SYS_FSL_ERRATUM_A009007 68 bool 69 help 70 Workaround for USB PHY erratum A009007 71 72config SYS_FSL_ERRATUM_A009008 73 bool 74 help 75 Workaround for USB PHY erratum A009008 76 77config SYS_FSL_ERRATUM_A009798 78 bool 79 help 80 Workaround for USB PHY erratum A009798 81 82config SYS_FSL_ERRATUM_A010315 83 bool "Workaround for PCIe erratum A010315" 84 85config SYS_FSL_HAS_CCI400 86 bool 87 88config SYS_FSL_SRDS_1 89 bool 90 91config SYS_FSL_SRDS_2 92 bool 93 94config SYS_HAS_SERDES 95 bool 96 97config SYS_FSL_IFC_BANK_COUNT 98 int "Maximum banks of Integrated flash controller" 99 default 8 100 101config SYS_FSL_ERRATUM_A008407 102 bool 103 104endmenu 105