1# SPDX-License-Identifier: GPL-2.0-only
2config ARM64
3	def_bool y
4	select ACPI_CCA_REQUIRED if ACPI
5	select ACPI_GENERIC_GSI if ACPI
6	select ACPI_GTDT if ACPI
7	select ACPI_IORT if ACPI
8	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9	select ACPI_MCFG if (ACPI && PCI)
10	select ACPI_SPCR_TABLE if ACPI
11	select ACPI_PPTT if ACPI
12	select ARCH_HAS_DEBUG_WX
13	select ARCH_BINFMT_ELF_STATE
14	select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
15	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
16	select ARCH_ENABLE_MEMORY_HOTPLUG
17	select ARCH_ENABLE_MEMORY_HOTREMOVE
18	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
19	select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
20	select ARCH_HAS_CACHE_LINE_SIZE
21	select ARCH_HAS_DEBUG_VIRTUAL
22	select ARCH_HAS_DEBUG_VM_PGTABLE
23	select ARCH_HAS_DMA_PREP_COHERENT
24	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
25	select ARCH_HAS_FAST_MULTIPLIER
26	select ARCH_HAS_FORTIFY_SOURCE
27	select ARCH_HAS_GCOV_PROFILE_ALL
28	select ARCH_HAS_GIGANTIC_PAGE
29	select ARCH_HAS_KCOV
30	select ARCH_HAS_KEEPINITRD
31	select ARCH_HAS_MEMBARRIER_SYNC_CORE
32	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
33	select ARCH_HAS_PTE_DEVMAP
34	select ARCH_HAS_PTE_SPECIAL
35	select ARCH_HAS_SETUP_DMA_OPS
36	select ARCH_HAS_SET_DIRECT_MAP
37	select ARCH_HAS_SET_MEMORY
38	select ARCH_STACKWALK
39	select ARCH_HAS_STRICT_KERNEL_RWX
40	select ARCH_HAS_STRICT_MODULE_RWX
41	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
42	select ARCH_HAS_SYNC_DMA_FOR_CPU
43	select ARCH_HAS_SYSCALL_WRAPPER
44	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
45	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
46	select ARCH_HAS_ZONE_DMA_SET if EXPERT
47	select ARCH_HAVE_ELF_PROT
48	select ARCH_HAVE_NMI_SAFE_CMPXCHG
49	select ARCH_INLINE_READ_LOCK if !PREEMPTION
50	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
51	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
52	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
53	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
54	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
55	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
56	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
57	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
58	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
59	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
60	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
61	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
62	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
63	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
64	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
65	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
66	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
67	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
68	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
69	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
70	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
71	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
72	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
73	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
74	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
75	select ARCH_KEEP_MEMBLOCK
76	select ARCH_USE_CMPXCHG_LOCKREF
77	select ARCH_USE_GNU_PROPERTY
78	select ARCH_USE_MEMTEST
79	select ARCH_USE_QUEUED_RWLOCKS
80	select ARCH_USE_QUEUED_SPINLOCKS
81	select ARCH_USE_SYM_ANNOTATIONS
82	select ARCH_SUPPORTS_DEBUG_PAGEALLOC
83	select ARCH_SUPPORTS_HUGETLBFS
84	select ARCH_SUPPORTS_MEMORY_FAILURE
85	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
86	select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
87	select ARCH_SUPPORTS_LTO_CLANG_THIN
88	select ARCH_SUPPORTS_CFI_CLANG
89	select ARCH_SUPPORTS_ATOMIC_RMW
90	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
91	select ARCH_SUPPORTS_NUMA_BALANCING
92	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
93	select ARCH_WANT_DEFAULT_BPF_JIT
94	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
95	select ARCH_WANT_FRAME_POINTERS
96	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
97	select ARCH_WANT_LD_ORPHAN_WARN
98	select ARCH_WANTS_NO_INSTR
99	select ARCH_HAS_UBSAN_SANITIZE_ALL
100	select ARM_AMBA
101	select ARM_ARCH_TIMER
102	select ARM_GIC
103	select AUDIT_ARCH_COMPAT_GENERIC
104	select ARM_GIC_V2M if PCI
105	select ARM_GIC_V3
106	select ARM_GIC_V3_ITS if PCI
107	select ARM_PSCI_FW
108	select BUILDTIME_TABLE_SORT
109	select CLONE_BACKWARDS
110	select COMMON_CLK
111	select CPU_PM if (SUSPEND || CPU_IDLE)
112	select CRC32
113	select DCACHE_WORD_ACCESS
114	select DMA_DIRECT_REMAP
115	select EDAC_SUPPORT
116	select FRAME_POINTER
117	select GENERIC_ALLOCATOR
118	select GENERIC_ARCH_TOPOLOGY
119	select GENERIC_CLOCKEVENTS_BROADCAST
120	select GENERIC_CPU_AUTOPROBE
121	select GENERIC_CPU_VULNERABILITIES
122	select GENERIC_EARLY_IOREMAP
123	select GENERIC_FIND_FIRST_BIT
124	select GENERIC_IDLE_POLL_SETUP
125	select GENERIC_IRQ_IPI
126	select GENERIC_IRQ_PROBE
127	select GENERIC_IRQ_SHOW
128	select GENERIC_IRQ_SHOW_LEVEL
129	select GENERIC_LIB_DEVMEM_IS_ALLOWED
130	select GENERIC_PCI_IOMAP
131	select GENERIC_PTDUMP
132	select GENERIC_SCHED_CLOCK
133	select GENERIC_SMP_IDLE_THREAD
134	select GENERIC_TIME_VSYSCALL
135	select GENERIC_GETTIMEOFDAY
136	select GENERIC_VDSO_TIME_NS
137	select HARDIRQS_SW_RESEND
138	select HAVE_MOVE_PMD
139	select HAVE_MOVE_PUD
140	select HAVE_PCI
141	select HAVE_ACPI_APEI if (ACPI && EFI)
142	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
143	select HAVE_ARCH_AUDITSYSCALL
144	select HAVE_ARCH_BITREVERSE
145	select HAVE_ARCH_COMPILER_H
146	select HAVE_ARCH_HUGE_VMAP
147	select HAVE_ARCH_JUMP_LABEL
148	select HAVE_ARCH_JUMP_LABEL_RELATIVE
149	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
150	select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
151	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
152	select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
153	select HAVE_ARCH_KFENCE
154	select HAVE_ARCH_KGDB
155	select HAVE_ARCH_MMAP_RND_BITS
156	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
157	select HAVE_ARCH_PREL32_RELOCATIONS
158	select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
159	select HAVE_ARCH_SECCOMP_FILTER
160	select HAVE_ARCH_STACKLEAK
161	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
162	select HAVE_ARCH_TRACEHOOK
163	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
164	select HAVE_ARCH_VMAP_STACK
165	select HAVE_ARM_SMCCC
166	select HAVE_ASM_MODVERSIONS
167	select HAVE_EBPF_JIT
168	select HAVE_C_RECORDMCOUNT
169	select HAVE_CMPXCHG_DOUBLE
170	select HAVE_CMPXCHG_LOCAL
171	select HAVE_CONTEXT_TRACKING
172	select HAVE_DEBUG_KMEMLEAK
173	select HAVE_DMA_CONTIGUOUS
174	select HAVE_DYNAMIC_FTRACE
175	select HAVE_DYNAMIC_FTRACE_WITH_REGS \
176		if $(cc-option,-fpatchable-function-entry=2)
177	select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
178		if DYNAMIC_FTRACE_WITH_REGS
179	select HAVE_EFFICIENT_UNALIGNED_ACCESS
180	select HAVE_FAST_GUP
181	select HAVE_FTRACE_MCOUNT_RECORD
182	select HAVE_FUNCTION_TRACER
183	select HAVE_FUNCTION_ERROR_INJECTION
184	select HAVE_FUNCTION_GRAPH_TRACER
185	select HAVE_GCC_PLUGINS
186	select HAVE_HW_BREAKPOINT if PERF_EVENTS
187	select HAVE_IRQ_TIME_ACCOUNTING
188	select HAVE_KVM
189	select HAVE_NMI
190	select HAVE_PATA_PLATFORM
191	select HAVE_PERF_EVENTS
192	select HAVE_PERF_REGS
193	select HAVE_PERF_USER_STACK_DUMP
194	select HAVE_REGS_AND_STACK_ACCESS_API
195	select HAVE_POSIX_CPU_TIMERS_TASK_WORK
196	select HAVE_FUNCTION_ARG_ACCESS_API
197	select HAVE_FUTEX_CMPXCHG if FUTEX
198	select MMU_GATHER_RCU_TABLE_FREE
199	select HAVE_RSEQ
200	select HAVE_STACKPROTECTOR
201	select HAVE_SYSCALL_TRACEPOINTS
202	select HAVE_KPROBES
203	select HAVE_KRETPROBES
204	select HAVE_GENERIC_VDSO
205	select IOMMU_DMA if IOMMU_SUPPORT
206	select IRQ_DOMAIN
207	select IRQ_FORCED_THREADING
208	select KASAN_VMALLOC if KASAN_GENERIC
209	select MODULES_USE_ELF_RELA
210	select NEED_DMA_MAP_STATE
211	select NEED_SG_DMA_LENGTH
212	select OF
213	select OF_EARLY_FLATTREE
214	select PCI_DOMAINS_GENERIC if PCI
215	select PCI_ECAM if (ACPI && PCI)
216	select PCI_SYSCALL if PCI
217	select POWER_RESET
218	select POWER_SUPPLY
219	select SPARSE_IRQ
220	select SWIOTLB
221	select SYSCTL_EXCEPTION_TRACE
222	select THREAD_INFO_IN_TASK
223	select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
224	select TRACE_IRQFLAGS_SUPPORT
225	help
226	  ARM 64-bit (AArch64) Linux support.
227
228config 64BIT
229	def_bool y
230
231config MMU
232	def_bool y
233
234config ARM64_PAGE_SHIFT
235	int
236	default 16 if ARM64_64K_PAGES
237	default 14 if ARM64_16K_PAGES
238	default 12
239
240config ARM64_CONT_PTE_SHIFT
241	int
242	default 5 if ARM64_64K_PAGES
243	default 7 if ARM64_16K_PAGES
244	default 4
245
246config ARM64_CONT_PMD_SHIFT
247	int
248	default 5 if ARM64_64K_PAGES
249	default 5 if ARM64_16K_PAGES
250	default 4
251
252config ARCH_MMAP_RND_BITS_MIN
253       default 14 if ARM64_64K_PAGES
254       default 16 if ARM64_16K_PAGES
255       default 18
256
257# max bits determined by the following formula:
258#  VA_BITS - PAGE_SHIFT - 3
259config ARCH_MMAP_RND_BITS_MAX
260       default 19 if ARM64_VA_BITS=36
261       default 24 if ARM64_VA_BITS=39
262       default 27 if ARM64_VA_BITS=42
263       default 30 if ARM64_VA_BITS=47
264       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
265       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
266       default 33 if ARM64_VA_BITS=48
267       default 14 if ARM64_64K_PAGES
268       default 16 if ARM64_16K_PAGES
269       default 18
270
271config ARCH_MMAP_RND_COMPAT_BITS_MIN
272       default 7 if ARM64_64K_PAGES
273       default 9 if ARM64_16K_PAGES
274       default 11
275
276config ARCH_MMAP_RND_COMPAT_BITS_MAX
277       default 16
278
279config NO_IOPORT_MAP
280	def_bool y if !PCI
281
282config STACKTRACE_SUPPORT
283	def_bool y
284
285config ILLEGAL_POINTER_VALUE
286	hex
287	default 0xdead000000000000
288
289config LOCKDEP_SUPPORT
290	def_bool y
291
292config GENERIC_BUG
293	def_bool y
294	depends on BUG
295
296config GENERIC_BUG_RELATIVE_POINTERS
297	def_bool y
298	depends on GENERIC_BUG
299
300config GENERIC_HWEIGHT
301	def_bool y
302
303config GENERIC_CSUM
304        def_bool y
305
306config GENERIC_CALIBRATE_DELAY
307	def_bool y
308
309config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
310	def_bool y
311
312config SMP
313	def_bool y
314
315config KERNEL_MODE_NEON
316	def_bool y
317
318config FIX_EARLYCON_MEM
319	def_bool y
320
321config PGTABLE_LEVELS
322	int
323	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
324	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
325	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
326	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
327	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
328	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
329
330config ARCH_SUPPORTS_UPROBES
331	def_bool y
332
333config ARCH_PROC_KCORE_TEXT
334	def_bool y
335
336config BROKEN_GAS_INST
337	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
338
339config KASAN_SHADOW_OFFSET
340	hex
341	depends on KASAN_GENERIC || KASAN_SW_TAGS
342	default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
343	default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
344	default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
345	default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
346	default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
347	default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
348	default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
349	default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
350	default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
351	default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
352	default 0xffffffffffffffff
353
354source "arch/arm64/Kconfig.platforms"
355
356menu "Kernel Features"
357
358menu "ARM errata workarounds via the alternatives framework"
359
360config ARM64_WORKAROUND_CLEAN_CACHE
361	bool
362
363config ARM64_ERRATUM_826319
364	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
365	default y
366	select ARM64_WORKAROUND_CLEAN_CACHE
367	help
368	  This option adds an alternative code sequence to work around ARM
369	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
370	  AXI master interface and an L2 cache.
371
372	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
373	  and is unable to accept a certain write via this interface, it will
374	  not progress on read data presented on the read data channel and the
375	  system can deadlock.
376
377	  The workaround promotes data cache clean instructions to
378	  data cache clean-and-invalidate.
379	  Please note that this does not necessarily enable the workaround,
380	  as it depends on the alternative framework, which will only patch
381	  the kernel if an affected CPU is detected.
382
383	  If unsure, say Y.
384
385config ARM64_ERRATUM_827319
386	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
387	default y
388	select ARM64_WORKAROUND_CLEAN_CACHE
389	help
390	  This option adds an alternative code sequence to work around ARM
391	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
392	  master interface and an L2 cache.
393
394	  Under certain conditions this erratum can cause a clean line eviction
395	  to occur at the same time as another transaction to the same address
396	  on the AMBA 5 CHI interface, which can cause data corruption if the
397	  interconnect reorders the two transactions.
398
399	  The workaround promotes data cache clean instructions to
400	  data cache clean-and-invalidate.
401	  Please note that this does not necessarily enable the workaround,
402	  as it depends on the alternative framework, which will only patch
403	  the kernel if an affected CPU is detected.
404
405	  If unsure, say Y.
406
407config ARM64_ERRATUM_824069
408	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
409	default y
410	select ARM64_WORKAROUND_CLEAN_CACHE
411	help
412	  This option adds an alternative code sequence to work around ARM
413	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
414	  to a coherent interconnect.
415
416	  If a Cortex-A53 processor is executing a store or prefetch for
417	  write instruction at the same time as a processor in another
418	  cluster is executing a cache maintenance operation to the same
419	  address, then this erratum might cause a clean cache line to be
420	  incorrectly marked as dirty.
421
422	  The workaround promotes data cache clean instructions to
423	  data cache clean-and-invalidate.
424	  Please note that this option does not necessarily enable the
425	  workaround, as it depends on the alternative framework, which will
426	  only patch the kernel if an affected CPU is detected.
427
428	  If unsure, say Y.
429
430config ARM64_ERRATUM_819472
431	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
432	default y
433	select ARM64_WORKAROUND_CLEAN_CACHE
434	help
435	  This option adds an alternative code sequence to work around ARM
436	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
437	  present when it is connected to a coherent interconnect.
438
439	  If the processor is executing a load and store exclusive sequence at
440	  the same time as a processor in another cluster is executing a cache
441	  maintenance operation to the same address, then this erratum might
442	  cause data corruption.
443
444	  The workaround promotes data cache clean instructions to
445	  data cache clean-and-invalidate.
446	  Please note that this does not necessarily enable the workaround,
447	  as it depends on the alternative framework, which will only patch
448	  the kernel if an affected CPU is detected.
449
450	  If unsure, say Y.
451
452config ARM64_ERRATUM_832075
453	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
454	default y
455	help
456	  This option adds an alternative code sequence to work around ARM
457	  erratum 832075 on Cortex-A57 parts up to r1p2.
458
459	  Affected Cortex-A57 parts might deadlock when exclusive load/store
460	  instructions to Write-Back memory are mixed with Device loads.
461
462	  The workaround is to promote device loads to use Load-Acquire
463	  semantics.
464	  Please note that this does not necessarily enable the workaround,
465	  as it depends on the alternative framework, which will only patch
466	  the kernel if an affected CPU is detected.
467
468	  If unsure, say Y.
469
470config ARM64_ERRATUM_834220
471	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
472	depends on KVM
473	default y
474	help
475	  This option adds an alternative code sequence to work around ARM
476	  erratum 834220 on Cortex-A57 parts up to r1p2.
477
478	  Affected Cortex-A57 parts might report a Stage 2 translation
479	  fault as the result of a Stage 1 fault for load crossing a
480	  page boundary when there is a permission or device memory
481	  alignment fault at Stage 1 and a translation fault at Stage 2.
482
483	  The workaround is to verify that the Stage 1 translation
484	  doesn't generate a fault before handling the Stage 2 fault.
485	  Please note that this does not necessarily enable the workaround,
486	  as it depends on the alternative framework, which will only patch
487	  the kernel if an affected CPU is detected.
488
489	  If unsure, say Y.
490
491config ARM64_ERRATUM_845719
492	bool "Cortex-A53: 845719: a load might read incorrect data"
493	depends on COMPAT
494	default y
495	help
496	  This option adds an alternative code sequence to work around ARM
497	  erratum 845719 on Cortex-A53 parts up to r0p4.
498
499	  When running a compat (AArch32) userspace on an affected Cortex-A53
500	  part, a load at EL0 from a virtual address that matches the bottom 32
501	  bits of the virtual address used by a recent load at (AArch64) EL1
502	  might return incorrect data.
503
504	  The workaround is to write the contextidr_el1 register on exception
505	  return to a 32-bit task.
506	  Please note that this does not necessarily enable the workaround,
507	  as it depends on the alternative framework, which will only patch
508	  the kernel if an affected CPU is detected.
509
510	  If unsure, say Y.
511
512config ARM64_ERRATUM_843419
513	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
514	default y
515	select ARM64_MODULE_PLTS if MODULES
516	help
517	  This option links the kernel with '--fix-cortex-a53-843419' and
518	  enables PLT support to replace certain ADRP instructions, which can
519	  cause subsequent memory accesses to use an incorrect address on
520	  Cortex-A53 parts up to r0p4.
521
522	  If unsure, say Y.
523
524config ARM64_LD_HAS_FIX_ERRATUM_843419
525	def_bool $(ld-option,--fix-cortex-a53-843419)
526
527config ARM64_ERRATUM_1024718
528	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
529	default y
530	help
531	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
532
533	  Affected Cortex-A55 cores (all revisions) could cause incorrect
534	  update of the hardware dirty bit when the DBM/AP bits are updated
535	  without a break-before-make. The workaround is to disable the usage
536	  of hardware DBM locally on the affected cores. CPUs not affected by
537	  this erratum will continue to use the feature.
538
539	  If unsure, say Y.
540
541config ARM64_ERRATUM_1418040
542	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
543	default y
544	depends on COMPAT
545	help
546	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
547	  errata 1188873 and 1418040.
548
549	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
550	  cause register corruption when accessing the timer registers
551	  from AArch32 userspace.
552
553	  If unsure, say Y.
554
555config ARM64_WORKAROUND_SPECULATIVE_AT
556	bool
557
558config ARM64_ERRATUM_1165522
559	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
560	default y
561	select ARM64_WORKAROUND_SPECULATIVE_AT
562	help
563	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
564
565	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
566	  corrupted TLBs by speculating an AT instruction during a guest
567	  context switch.
568
569	  If unsure, say Y.
570
571config ARM64_ERRATUM_1319367
572	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
573	default y
574	select ARM64_WORKAROUND_SPECULATIVE_AT
575	help
576	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
577	  and A72 erratum 1319367
578
579	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
580	  speculating an AT instruction during a guest context switch.
581
582	  If unsure, say Y.
583
584config ARM64_ERRATUM_1530923
585	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
586	default y
587	select ARM64_WORKAROUND_SPECULATIVE_AT
588	help
589	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
590
591	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
592	  corrupted TLBs by speculating an AT instruction during a guest
593	  context switch.
594
595	  If unsure, say Y.
596
597config ARM64_WORKAROUND_REPEAT_TLBI
598	bool
599
600config ARM64_ERRATUM_1286807
601	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
602	default y
603	select ARM64_WORKAROUND_REPEAT_TLBI
604	help
605	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
606
607	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
608	  address for a cacheable mapping of a location is being
609	  accessed by a core while another core is remapping the virtual
610	  address to a new physical page using the recommended
611	  break-before-make sequence, then under very rare circumstances
612	  TLBI+DSB completes before a read using the translation being
613	  invalidated has been observed by other observers. The
614	  workaround repeats the TLBI+DSB operation.
615
616config ARM64_ERRATUM_1463225
617	bool "Cortex-A76: Software Step might prevent interrupt recognition"
618	default y
619	help
620	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
621
622	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
623	  of a system call instruction (SVC) can prevent recognition of
624	  subsequent interrupts when software stepping is disabled in the
625	  exception handler of the system call and either kernel debugging
626	  is enabled or VHE is in use.
627
628	  Work around the erratum by triggering a dummy step exception
629	  when handling a system call from a task that is being stepped
630	  in a VHE configuration of the kernel.
631
632	  If unsure, say Y.
633
634config ARM64_ERRATUM_1542419
635	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
636	default y
637	help
638	  This option adds a workaround for ARM Neoverse-N1 erratum
639	  1542419.
640
641	  Affected Neoverse-N1 cores could execute a stale instruction when
642	  modified by another CPU. The workaround depends on a firmware
643	  counterpart.
644
645	  Workaround the issue by hiding the DIC feature from EL0. This
646	  forces user-space to perform cache maintenance.
647
648	  If unsure, say Y.
649
650config ARM64_ERRATUM_1508412
651	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
652	default y
653	help
654	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
655
656	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
657	  of a store-exclusive or read of PAR_EL1 and a load with device or
658	  non-cacheable memory attributes. The workaround depends on a firmware
659	  counterpart.
660
661	  KVM guests must also have the workaround implemented or they can
662	  deadlock the system.
663
664	  Work around the issue by inserting DMB SY barriers around PAR_EL1
665	  register reads and warning KVM users. The DMB barrier is sufficient
666	  to prevent a speculative PAR_EL1 read.
667
668	  If unsure, say Y.
669
670config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
671	bool
672
673config ARM64_ERRATUM_2119858
674	bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
675	default y
676	depends on CORESIGHT_TRBE
677	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
678	help
679	  This option adds the workaround for ARM Cortex-A710 erratum 2119858.
680
681	  Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
682	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
683	  the event of a WRAP event.
684
685	  Work around the issue by always making sure we move the TRBPTR_EL1 by
686	  256 bytes before enabling the buffer and filling the first 256 bytes of
687	  the buffer with ETM ignore packets upon disabling.
688
689	  If unsure, say Y.
690
691config ARM64_ERRATUM_2139208
692	bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
693	default y
694	depends on CORESIGHT_TRBE
695	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
696	help
697	  This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
698
699	  Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
700	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
701	  the event of a WRAP event.
702
703	  Work around the issue by always making sure we move the TRBPTR_EL1 by
704	  256 bytes before enabling the buffer and filling the first 256 bytes of
705	  the buffer with ETM ignore packets upon disabling.
706
707	  If unsure, say Y.
708
709config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
710	bool
711
712config ARM64_ERRATUM_2054223
713	bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
714	default y
715	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
716	help
717	  Enable workaround for ARM Cortex-A710 erratum 2054223
718
719	  Affected cores may fail to flush the trace data on a TSB instruction, when
720	  the PE is in trace prohibited state. This will cause losing a few bytes
721	  of the trace cached.
722
723	  Workaround is to issue two TSB consecutively on affected cores.
724
725	  If unsure, say Y.
726
727config ARM64_ERRATUM_2067961
728	bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
729	default y
730	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
731	help
732	  Enable workaround for ARM Neoverse-N2 erratum 2067961
733
734	  Affected cores may fail to flush the trace data on a TSB instruction, when
735	  the PE is in trace prohibited state. This will cause losing a few bytes
736	  of the trace cached.
737
738	  Workaround is to issue two TSB consecutively on affected cores.
739
740	  If unsure, say Y.
741
742config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
743	bool
744
745config ARM64_ERRATUM_2253138
746	bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
747	depends on CORESIGHT_TRBE
748	default y
749	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
750	help
751	  This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
752
753	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
754	  for TRBE. Under some conditions, the TRBE might generate a write to the next
755	  virtually addressed page following the last page of the TRBE address space
756	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
757
758	  Work around this in the driver by always making sure that there is a
759	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
760
761	  If unsure, say Y.
762
763config ARM64_ERRATUM_2224489
764	bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
765	depends on CORESIGHT_TRBE
766	default y
767	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
768	help
769	  This option adds the workaround for ARM Cortex-A710 erratum 2224489.
770
771	  Affected Cortex-A710 cores might write to an out-of-range address, not reserved
772	  for TRBE. Under some conditions, the TRBE might generate a write to the next
773	  virtually addressed page following the last page of the TRBE address space
774	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
775
776	  Work around this in the driver by always making sure that there is a
777	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
778
779	  If unsure, say Y.
780
781config CAVIUM_ERRATUM_22375
782	bool "Cavium erratum 22375, 24313"
783	default y
784	help
785	  Enable workaround for errata 22375 and 24313.
786
787	  This implements two gicv3-its errata workarounds for ThunderX. Both
788	  with a small impact affecting only ITS table allocation.
789
790	    erratum 22375: only alloc 8MB table size
791	    erratum 24313: ignore memory access type
792
793	  The fixes are in ITS initialization and basically ignore memory access
794	  type and table size provided by the TYPER and BASER registers.
795
796	  If unsure, say Y.
797
798config CAVIUM_ERRATUM_23144
799	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
800	depends on NUMA
801	default y
802	help
803	  ITS SYNC command hang for cross node io and collections/cpu mapping.
804
805	  If unsure, say Y.
806
807config CAVIUM_ERRATUM_23154
808	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
809	default y
810	help
811	  The gicv3 of ThunderX requires a modified version for
812	  reading the IAR status to ensure data synchronization
813	  (access to icc_iar1_el1 is not sync'ed before and after).
814
815	  If unsure, say Y.
816
817config CAVIUM_ERRATUM_27456
818	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
819	default y
820	help
821	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
822	  instructions may cause the icache to become corrupted if it
823	  contains data for a non-current ASID.  The fix is to
824	  invalidate the icache when changing the mm context.
825
826	  If unsure, say Y.
827
828config CAVIUM_ERRATUM_30115
829	bool "Cavium erratum 30115: Guest may disable interrupts in host"
830	default y
831	help
832	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
833	  1.2, and T83 Pass 1.0, KVM guest execution may disable
834	  interrupts in host. Trapping both GICv3 group-0 and group-1
835	  accesses sidesteps the issue.
836
837	  If unsure, say Y.
838
839config CAVIUM_TX2_ERRATUM_219
840	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
841	default y
842	help
843	  On Cavium ThunderX2, a load, store or prefetch instruction between a
844	  TTBR update and the corresponding context synchronizing operation can
845	  cause a spurious Data Abort to be delivered to any hardware thread in
846	  the CPU core.
847
848	  Work around the issue by avoiding the problematic code sequence and
849	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
850	  trap handler performs the corresponding register access, skips the
851	  instruction and ensures context synchronization by virtue of the
852	  exception return.
853
854	  If unsure, say Y.
855
856config FUJITSU_ERRATUM_010001
857	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
858	default y
859	help
860	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
861	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
862	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
863	  This fault occurs under a specific hardware condition when a
864	  load/store instruction performs an address translation using:
865	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
866	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
867	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
868	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
869
870	  The workaround is to ensure these bits are clear in TCR_ELx.
871	  The workaround only affects the Fujitsu-A64FX.
872
873	  If unsure, say Y.
874
875config HISILICON_ERRATUM_161600802
876	bool "Hip07 161600802: Erroneous redistributor VLPI base"
877	default y
878	help
879	  The HiSilicon Hip07 SoC uses the wrong redistributor base
880	  when issued ITS commands such as VMOVP and VMAPP, and requires
881	  a 128kB offset to be applied to the target address in this commands.
882
883	  If unsure, say Y.
884
885config QCOM_FALKOR_ERRATUM_1003
886	bool "Falkor E1003: Incorrect translation due to ASID change"
887	default y
888	help
889	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
890	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
891	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
892	  then only for entries in the walk cache, since the leaf translation
893	  is unchanged. Work around the erratum by invalidating the walk cache
894	  entries for the trampoline before entering the kernel proper.
895
896config QCOM_FALKOR_ERRATUM_1009
897	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
898	default y
899	select ARM64_WORKAROUND_REPEAT_TLBI
900	help
901	  On Falkor v1, the CPU may prematurely complete a DSB following a
902	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
903	  one more time to fix the issue.
904
905	  If unsure, say Y.
906
907config QCOM_QDF2400_ERRATUM_0065
908	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
909	default y
910	help
911	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
912	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
913	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
914
915	  If unsure, say Y.
916
917config QCOM_FALKOR_ERRATUM_E1041
918	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
919	default y
920	help
921	  Falkor CPU may speculatively fetch instructions from an improper
922	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
923	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
924
925	  If unsure, say Y.
926
927config NVIDIA_CARMEL_CNP_ERRATUM
928	bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
929	default y
930	help
931	  If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
932	  invalidate shared TLB entries installed by a different core, as it would
933	  on standard ARM cores.
934
935	  If unsure, say Y.
936
937config SOCIONEXT_SYNQUACER_PREITS
938	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
939	default y
940	help
941	  Socionext Synquacer SoCs implement a separate h/w block to generate
942	  MSI doorbell writes with non-zero values for the device ID.
943
944	  If unsure, say Y.
945
946endmenu
947
948
949choice
950	prompt "Page size"
951	default ARM64_4K_PAGES
952	help
953	  Page size (translation granule) configuration.
954
955config ARM64_4K_PAGES
956	bool "4KB"
957	help
958	  This feature enables 4KB pages support.
959
960config ARM64_16K_PAGES
961	bool "16KB"
962	help
963	  The system will use 16KB pages support. AArch32 emulation
964	  requires applications compiled with 16K (or a multiple of 16K)
965	  aligned segments.
966
967config ARM64_64K_PAGES
968	bool "64KB"
969	help
970	  This feature enables 64KB pages support (4KB by default)
971	  allowing only two levels of page tables and faster TLB
972	  look-up. AArch32 emulation requires applications compiled
973	  with 64K aligned segments.
974
975endchoice
976
977choice
978	prompt "Virtual address space size"
979	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
980	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
981	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
982	help
983	  Allows choosing one of multiple possible virtual address
984	  space sizes. The level of translation table is determined by
985	  a combination of page size and virtual address space size.
986
987config ARM64_VA_BITS_36
988	bool "36-bit" if EXPERT
989	depends on ARM64_16K_PAGES
990
991config ARM64_VA_BITS_39
992	bool "39-bit"
993	depends on ARM64_4K_PAGES
994
995config ARM64_VA_BITS_42
996	bool "42-bit"
997	depends on ARM64_64K_PAGES
998
999config ARM64_VA_BITS_47
1000	bool "47-bit"
1001	depends on ARM64_16K_PAGES
1002
1003config ARM64_VA_BITS_48
1004	bool "48-bit"
1005
1006config ARM64_VA_BITS_52
1007	bool "52-bit"
1008	depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1009	help
1010	  Enable 52-bit virtual addressing for userspace when explicitly
1011	  requested via a hint to mmap(). The kernel will also use 52-bit
1012	  virtual addresses for its own mappings (provided HW support for
1013	  this feature is available, otherwise it reverts to 48-bit).
1014
1015	  NOTE: Enabling 52-bit virtual addressing in conjunction with
1016	  ARMv8.3 Pointer Authentication will result in the PAC being
1017	  reduced from 7 bits to 3 bits, which may have a significant
1018	  impact on its susceptibility to brute-force attacks.
1019
1020	  If unsure, select 48-bit virtual addressing instead.
1021
1022endchoice
1023
1024config ARM64_FORCE_52BIT
1025	bool "Force 52-bit virtual addresses for userspace"
1026	depends on ARM64_VA_BITS_52 && EXPERT
1027	help
1028	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
1029	  to maintain compatibility with older software by providing 48-bit VAs
1030	  unless a hint is supplied to mmap.
1031
1032	  This configuration option disables the 48-bit compatibility logic, and
1033	  forces all userspace addresses to be 52-bit on HW that supports it. One
1034	  should only enable this configuration option for stress testing userspace
1035	  memory management code. If unsure say N here.
1036
1037config ARM64_VA_BITS
1038	int
1039	default 36 if ARM64_VA_BITS_36
1040	default 39 if ARM64_VA_BITS_39
1041	default 42 if ARM64_VA_BITS_42
1042	default 47 if ARM64_VA_BITS_47
1043	default 48 if ARM64_VA_BITS_48
1044	default 52 if ARM64_VA_BITS_52
1045
1046choice
1047	prompt "Physical address space size"
1048	default ARM64_PA_BITS_48
1049	help
1050	  Choose the maximum physical address range that the kernel will
1051	  support.
1052
1053config ARM64_PA_BITS_48
1054	bool "48-bit"
1055
1056config ARM64_PA_BITS_52
1057	bool "52-bit (ARMv8.2)"
1058	depends on ARM64_64K_PAGES
1059	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1060	help
1061	  Enable support for a 52-bit physical address space, introduced as
1062	  part of the ARMv8.2-LPA extension.
1063
1064	  With this enabled, the kernel will also continue to work on CPUs that
1065	  do not support ARMv8.2-LPA, but with some added memory overhead (and
1066	  minor performance overhead).
1067
1068endchoice
1069
1070config ARM64_PA_BITS
1071	int
1072	default 48 if ARM64_PA_BITS_48
1073	default 52 if ARM64_PA_BITS_52
1074
1075choice
1076	prompt "Endianness"
1077	default CPU_LITTLE_ENDIAN
1078	help
1079	  Select the endianness of data accesses performed by the CPU. Userspace
1080	  applications will need to be compiled and linked for the endianness
1081	  that is selected here.
1082
1083config CPU_BIG_ENDIAN
1084	bool "Build big-endian kernel"
1085	depends on !LD_IS_LLD || LLD_VERSION >= 130000
1086	help
1087	  Say Y if you plan on running a kernel with a big-endian userspace.
1088
1089config CPU_LITTLE_ENDIAN
1090	bool "Build little-endian kernel"
1091	help
1092	  Say Y if you plan on running a kernel with a little-endian userspace.
1093	  This is usually the case for distributions targeting arm64.
1094
1095endchoice
1096
1097config SCHED_MC
1098	bool "Multi-core scheduler support"
1099	help
1100	  Multi-core scheduler support improves the CPU scheduler's decision
1101	  making when dealing with multi-core CPU chips at a cost of slightly
1102	  increased overhead in some places. If unsure say N here.
1103
1104config SCHED_CLUSTER
1105	bool "Cluster scheduler support"
1106	help
1107	  Cluster scheduler support improves the CPU scheduler's decision
1108	  making when dealing with machines that have clusters of CPUs.
1109	  Cluster usually means a couple of CPUs which are placed closely
1110	  by sharing mid-level caches, last-level cache tags or internal
1111	  busses.
1112
1113config SCHED_SMT
1114	bool "SMT scheduler support"
1115	help
1116	  Improves the CPU scheduler's decision making when dealing with
1117	  MultiThreading at a cost of slightly increased overhead in some
1118	  places. If unsure say N here.
1119
1120config NR_CPUS
1121	int "Maximum number of CPUs (2-4096)"
1122	range 2 4096
1123	default "256"
1124
1125config HOTPLUG_CPU
1126	bool "Support for hot-pluggable CPUs"
1127	select GENERIC_IRQ_MIGRATION
1128	help
1129	  Say Y here to experiment with turning CPUs off and on.  CPUs
1130	  can be controlled through /sys/devices/system/cpu.
1131
1132# Common NUMA Features
1133config NUMA
1134	bool "NUMA Memory Allocation and Scheduler Support"
1135	select GENERIC_ARCH_NUMA
1136	select ACPI_NUMA if ACPI
1137	select OF_NUMA
1138	help
1139	  Enable NUMA (Non-Uniform Memory Access) support.
1140
1141	  The kernel will try to allocate memory used by a CPU on the
1142	  local memory of the CPU and add some more
1143	  NUMA awareness to the kernel.
1144
1145config NODES_SHIFT
1146	int "Maximum NUMA Nodes (as a power of 2)"
1147	range 1 10
1148	default "4"
1149	depends on NUMA
1150	help
1151	  Specify the maximum number of NUMA Nodes available on the target
1152	  system.  Increases memory reserved to accommodate various tables.
1153
1154config USE_PERCPU_NUMA_NODE_ID
1155	def_bool y
1156	depends on NUMA
1157
1158config HAVE_SETUP_PER_CPU_AREA
1159	def_bool y
1160	depends on NUMA
1161
1162config NEED_PER_CPU_EMBED_FIRST_CHUNK
1163	def_bool y
1164	depends on NUMA
1165
1166config NEED_PER_CPU_PAGE_FIRST_CHUNK
1167	def_bool y
1168	depends on NUMA
1169
1170source "kernel/Kconfig.hz"
1171
1172config ARCH_SPARSEMEM_ENABLE
1173	def_bool y
1174	select SPARSEMEM_VMEMMAP_ENABLE
1175	select SPARSEMEM_VMEMMAP
1176
1177config HW_PERF_EVENTS
1178	def_bool y
1179	depends on ARM_PMU
1180
1181config ARCH_HAS_FILTER_PGPROT
1182	def_bool y
1183
1184# Supported by clang >= 7.0
1185config CC_HAVE_SHADOW_CALL_STACK
1186	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1187
1188config PARAVIRT
1189	bool "Enable paravirtualization code"
1190	help
1191	  This changes the kernel so it can modify itself when it is run
1192	  under a hypervisor, potentially improving performance significantly
1193	  over full virtualization.
1194
1195config PARAVIRT_TIME_ACCOUNTING
1196	bool "Paravirtual steal time accounting"
1197	select PARAVIRT
1198	help
1199	  Select this option to enable fine granularity task steal time
1200	  accounting. Time spent executing other tasks in parallel with
1201	  the current vCPU is discounted from the vCPU power. To account for
1202	  that, there can be a small performance impact.
1203
1204	  If in doubt, say N here.
1205
1206config KEXEC
1207	depends on PM_SLEEP_SMP
1208	select KEXEC_CORE
1209	bool "kexec system call"
1210	help
1211	  kexec is a system call that implements the ability to shutdown your
1212	  current kernel, and to start another kernel.  It is like a reboot
1213	  but it is independent of the system firmware.   And like a reboot
1214	  you can start any kernel with it, not just Linux.
1215
1216config KEXEC_FILE
1217	bool "kexec file based system call"
1218	select KEXEC_CORE
1219	select HAVE_IMA_KEXEC if IMA
1220	help
1221	  This is new version of kexec system call. This system call is
1222	  file based and takes file descriptors as system call argument
1223	  for kernel and initramfs as opposed to list of segments as
1224	  accepted by previous system call.
1225
1226config KEXEC_SIG
1227	bool "Verify kernel signature during kexec_file_load() syscall"
1228	depends on KEXEC_FILE
1229	help
1230	  Select this option to verify a signature with loaded kernel
1231	  image. If configured, any attempt of loading a image without
1232	  valid signature will fail.
1233
1234	  In addition to that option, you need to enable signature
1235	  verification for the corresponding kernel image type being
1236	  loaded in order for this to work.
1237
1238config KEXEC_IMAGE_VERIFY_SIG
1239	bool "Enable Image signature verification support"
1240	default y
1241	depends on KEXEC_SIG
1242	depends on EFI && SIGNED_PE_FILE_VERIFICATION
1243	help
1244	  Enable Image signature verification support.
1245
1246comment "Support for PE file signature verification disabled"
1247	depends on KEXEC_SIG
1248	depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1249
1250config CRASH_DUMP
1251	bool "Build kdump crash kernel"
1252	help
1253	  Generate crash dump after being started by kexec. This should
1254	  be normally only set in special crash dump kernels which are
1255	  loaded in the main kernel with kexec-tools into a specially
1256	  reserved region and then later executed after a crash by
1257	  kdump/kexec.
1258
1259	  For more details see Documentation/admin-guide/kdump/kdump.rst
1260
1261config TRANS_TABLE
1262	def_bool y
1263	depends on HIBERNATION || KEXEC_CORE
1264
1265config XEN_DOM0
1266	def_bool y
1267	depends on XEN
1268
1269config XEN
1270	bool "Xen guest support on ARM64"
1271	depends on ARM64 && OF
1272	select SWIOTLB_XEN
1273	select PARAVIRT
1274	help
1275	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1276
1277config FORCE_MAX_ZONEORDER
1278	int
1279	default "14" if ARM64_64K_PAGES
1280	default "12" if ARM64_16K_PAGES
1281	default "11"
1282	help
1283	  The kernel memory allocator divides physically contiguous memory
1284	  blocks into "zones", where each zone is a power of two number of
1285	  pages.  This option selects the largest power of two that the kernel
1286	  keeps in the memory allocator.  If you need to allocate very large
1287	  blocks of physically contiguous memory, then you may need to
1288	  increase this value.
1289
1290	  This config option is actually maximum order plus one. For example,
1291	  a value of 11 means that the largest free memory block is 2^10 pages.
1292
1293	  We make sure that we can allocate upto a HugePage size for each configuration.
1294	  Hence we have :
1295		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1296
1297	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1298	  4M allocations matching the default size used by generic code.
1299
1300config UNMAP_KERNEL_AT_EL0
1301	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1302	default y
1303	help
1304	  Speculation attacks against some high-performance processors can
1305	  be used to bypass MMU permission checks and leak kernel data to
1306	  userspace. This can be defended against by unmapping the kernel
1307	  when running in userspace, mapping it back in on exception entry
1308	  via a trampoline page in the vector table.
1309
1310	  If unsure, say Y.
1311
1312config RODATA_FULL_DEFAULT_ENABLED
1313	bool "Apply r/o permissions of VM areas also to their linear aliases"
1314	default y
1315	help
1316	  Apply read-only attributes of VM areas to the linear alias of
1317	  the backing pages as well. This prevents code or read-only data
1318	  from being modified (inadvertently or intentionally) via another
1319	  mapping of the same memory page. This additional enhancement can
1320	  be turned off at runtime by passing rodata=[off|on] (and turned on
1321	  with rodata=full if this option is set to 'n')
1322
1323	  This requires the linear region to be mapped down to pages,
1324	  which may adversely affect performance in some cases.
1325
1326config ARM64_SW_TTBR0_PAN
1327	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1328	help
1329	  Enabling this option prevents the kernel from accessing
1330	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1331	  zeroed area and reserved ASID. The user access routines
1332	  restore the valid TTBR0_EL1 temporarily.
1333
1334config ARM64_TAGGED_ADDR_ABI
1335	bool "Enable the tagged user addresses syscall ABI"
1336	default y
1337	help
1338	  When this option is enabled, user applications can opt in to a
1339	  relaxed ABI via prctl() allowing tagged addresses to be passed
1340	  to system calls as pointer arguments. For details, see
1341	  Documentation/arm64/tagged-address-abi.rst.
1342
1343menuconfig COMPAT
1344	bool "Kernel support for 32-bit EL0"
1345	depends on ARM64_4K_PAGES || EXPERT
1346	select HAVE_UID16
1347	select OLD_SIGSUSPEND3
1348	select COMPAT_OLD_SIGACTION
1349	help
1350	  This option enables support for a 32-bit EL0 running under a 64-bit
1351	  kernel at EL1. AArch32-specific components such as system calls,
1352	  the user helper functions, VFP support and the ptrace interface are
1353	  handled appropriately by the kernel.
1354
1355	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1356	  that you will only be able to execute AArch32 binaries that were compiled
1357	  with page size aligned segments.
1358
1359	  If you want to execute 32-bit userspace applications, say Y.
1360
1361if COMPAT
1362
1363config KUSER_HELPERS
1364	bool "Enable kuser helpers page for 32-bit applications"
1365	default y
1366	help
1367	  Warning: disabling this option may break 32-bit user programs.
1368
1369	  Provide kuser helpers to compat tasks. The kernel provides
1370	  helper code to userspace in read only form at a fixed location
1371	  to allow userspace to be independent of the CPU type fitted to
1372	  the system. This permits binaries to be run on ARMv4 through
1373	  to ARMv8 without modification.
1374
1375	  See Documentation/arm/kernel_user_helpers.rst for details.
1376
1377	  However, the fixed address nature of these helpers can be used
1378	  by ROP (return orientated programming) authors when creating
1379	  exploits.
1380
1381	  If all of the binaries and libraries which run on your platform
1382	  are built specifically for your platform, and make no use of
1383	  these helpers, then you can turn this option off to hinder
1384	  such exploits. However, in that case, if a binary or library
1385	  relying on those helpers is run, it will not function correctly.
1386
1387	  Say N here only if you are absolutely certain that you do not
1388	  need these helpers; otherwise, the safe option is to say Y.
1389
1390config COMPAT_VDSO
1391	bool "Enable vDSO for 32-bit applications"
1392	depends on !CPU_BIG_ENDIAN
1393	depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1394	select GENERIC_COMPAT_VDSO
1395	default y
1396	help
1397	  Place in the process address space of 32-bit applications an
1398	  ELF shared object providing fast implementations of gettimeofday
1399	  and clock_gettime.
1400
1401	  You must have a 32-bit build of glibc 2.22 or later for programs
1402	  to seamlessly take advantage of this.
1403
1404config THUMB2_COMPAT_VDSO
1405	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1406	depends on COMPAT_VDSO
1407	default y
1408	help
1409	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1410	  otherwise with '-marm'.
1411
1412menuconfig ARMV8_DEPRECATED
1413	bool "Emulate deprecated/obsolete ARMv8 instructions"
1414	depends on SYSCTL
1415	help
1416	  Legacy software support may require certain instructions
1417	  that have been deprecated or obsoleted in the architecture.
1418
1419	  Enable this config to enable selective emulation of these
1420	  features.
1421
1422	  If unsure, say Y
1423
1424if ARMV8_DEPRECATED
1425
1426config SWP_EMULATION
1427	bool "Emulate SWP/SWPB instructions"
1428	help
1429	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1430	  they are always undefined. Say Y here to enable software
1431	  emulation of these instructions for userspace using LDXR/STXR.
1432	  This feature can be controlled at runtime with the abi.swp
1433	  sysctl which is disabled by default.
1434
1435	  In some older versions of glibc [<=2.8] SWP is used during futex
1436	  trylock() operations with the assumption that the code will not
1437	  be preempted. This invalid assumption may be more likely to fail
1438	  with SWP emulation enabled, leading to deadlock of the user
1439	  application.
1440
1441	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1442	  on an external transaction monitoring block called a global
1443	  monitor to maintain update atomicity. If your system does not
1444	  implement a global monitor, this option can cause programs that
1445	  perform SWP operations to uncached memory to deadlock.
1446
1447	  If unsure, say Y
1448
1449config CP15_BARRIER_EMULATION
1450	bool "Emulate CP15 Barrier instructions"
1451	help
1452	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1453	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1454	  strongly recommended to use the ISB, DSB, and DMB
1455	  instructions instead.
1456
1457	  Say Y here to enable software emulation of these
1458	  instructions for AArch32 userspace code. When this option is
1459	  enabled, CP15 barrier usage is traced which can help
1460	  identify software that needs updating. This feature can be
1461	  controlled at runtime with the abi.cp15_barrier sysctl.
1462
1463	  If unsure, say Y
1464
1465config SETEND_EMULATION
1466	bool "Emulate SETEND instruction"
1467	help
1468	  The SETEND instruction alters the data-endianness of the
1469	  AArch32 EL0, and is deprecated in ARMv8.
1470
1471	  Say Y here to enable software emulation of the instruction
1472	  for AArch32 userspace code. This feature can be controlled
1473	  at runtime with the abi.setend sysctl.
1474
1475	  Note: All the cpus on the system must have mixed endian support at EL0
1476	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1477	  endian - is hotplugged in after this feature has been enabled, there could
1478	  be unexpected results in the applications.
1479
1480	  If unsure, say Y
1481endif
1482
1483endif
1484
1485menu "ARMv8.1 architectural features"
1486
1487config ARM64_HW_AFDBM
1488	bool "Support for hardware updates of the Access and Dirty page flags"
1489	default y
1490	help
1491	  The ARMv8.1 architecture extensions introduce support for
1492	  hardware updates of the access and dirty information in page
1493	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1494	  capable processors, accesses to pages with PTE_AF cleared will
1495	  set this bit instead of raising an access flag fault.
1496	  Similarly, writes to read-only pages with the DBM bit set will
1497	  clear the read-only bit (AP[2]) instead of raising a
1498	  permission fault.
1499
1500	  Kernels built with this configuration option enabled continue
1501	  to work on pre-ARMv8.1 hardware and the performance impact is
1502	  minimal. If unsure, say Y.
1503
1504config ARM64_PAN
1505	bool "Enable support for Privileged Access Never (PAN)"
1506	default y
1507	help
1508	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1509	 prevents the kernel or hypervisor from accessing user-space (EL0)
1510	 memory directly.
1511
1512	 Choosing this option will cause any unprotected (not using
1513	 copy_to_user et al) memory access to fail with a permission fault.
1514
1515	 The feature is detected at runtime, and will remain as a 'nop'
1516	 instruction if the cpu does not implement the feature.
1517
1518config AS_HAS_LDAPR
1519	def_bool $(as-instr,.arch_extension rcpc)
1520
1521config AS_HAS_LSE_ATOMICS
1522	def_bool $(as-instr,.arch_extension lse)
1523
1524config ARM64_LSE_ATOMICS
1525	bool
1526	default ARM64_USE_LSE_ATOMICS
1527	depends on AS_HAS_LSE_ATOMICS
1528
1529config ARM64_USE_LSE_ATOMICS
1530	bool "Atomic instructions"
1531	depends on JUMP_LABEL
1532	default y
1533	help
1534	  As part of the Large System Extensions, ARMv8.1 introduces new
1535	  atomic instructions that are designed specifically to scale in
1536	  very large systems.
1537
1538	  Say Y here to make use of these instructions for the in-kernel
1539	  atomic routines. This incurs a small overhead on CPUs that do
1540	  not support these instructions and requires the kernel to be
1541	  built with binutils >= 2.25 in order for the new instructions
1542	  to be used.
1543
1544endmenu
1545
1546menu "ARMv8.2 architectural features"
1547
1548config ARM64_PMEM
1549	bool "Enable support for persistent memory"
1550	select ARCH_HAS_PMEM_API
1551	select ARCH_HAS_UACCESS_FLUSHCACHE
1552	help
1553	  Say Y to enable support for the persistent memory API based on the
1554	  ARMv8.2 DCPoP feature.
1555
1556	  The feature is detected at runtime, and the kernel will use DC CVAC
1557	  operations if DC CVAP is not supported (following the behaviour of
1558	  DC CVAP itself if the system does not define a point of persistence).
1559
1560config ARM64_RAS_EXTN
1561	bool "Enable support for RAS CPU Extensions"
1562	default y
1563	help
1564	  CPUs that support the Reliability, Availability and Serviceability
1565	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1566	  errors, classify them and report them to software.
1567
1568	  On CPUs with these extensions system software can use additional
1569	  barriers to determine if faults are pending and read the
1570	  classification from a new set of registers.
1571
1572	  Selecting this feature will allow the kernel to use these barriers
1573	  and access the new registers if the system supports the extension.
1574	  Platform RAS features may additionally depend on firmware support.
1575
1576config ARM64_CNP
1577	bool "Enable support for Common Not Private (CNP) translations"
1578	default y
1579	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1580	help
1581	  Common Not Private (CNP) allows translation table entries to
1582	  be shared between different PEs in the same inner shareable
1583	  domain, so the hardware can use this fact to optimise the
1584	  caching of such entries in the TLB.
1585
1586	  Selecting this option allows the CNP feature to be detected
1587	  at runtime, and does not affect PEs that do not implement
1588	  this feature.
1589
1590endmenu
1591
1592menu "ARMv8.3 architectural features"
1593
1594config ARM64_PTR_AUTH
1595	bool "Enable support for pointer authentication"
1596	default y
1597	help
1598	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1599	  instructions for signing and authenticating pointers against secret
1600	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1601	  and other attacks.
1602
1603	  This option enables these instructions at EL0 (i.e. for userspace).
1604	  Choosing this option will cause the kernel to initialise secret keys
1605	  for each process at exec() time, with these keys being
1606	  context-switched along with the process.
1607
1608	  The feature is detected at runtime. If the feature is not present in
1609	  hardware it will not be advertised to userspace/KVM guest nor will it
1610	  be enabled.
1611
1612	  If the feature is present on the boot CPU but not on a late CPU, then
1613	  the late CPU will be parked. Also, if the boot CPU does not have
1614	  address auth and the late CPU has then the late CPU will still boot
1615	  but with the feature disabled. On such a system, this option should
1616	  not be selected.
1617
1618config ARM64_PTR_AUTH_KERNEL
1619	bool "Use pointer authentication for kernel"
1620	default y
1621	depends on ARM64_PTR_AUTH
1622	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1623	# Modern compilers insert a .note.gnu.property section note for PAC
1624	# which is only understood by binutils starting with version 2.33.1.
1625	depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1626	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1627	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1628	help
1629	  If the compiler supports the -mbranch-protection or
1630	  -msign-return-address flag (e.g. GCC 7 or later), then this option
1631	  will cause the kernel itself to be compiled with return address
1632	  protection. In this case, and if the target hardware is known to
1633	  support pointer authentication, then CONFIG_STACKPROTECTOR can be
1634	  disabled with minimal loss of protection.
1635
1636	  This feature works with FUNCTION_GRAPH_TRACER option only if
1637	  DYNAMIC_FTRACE_WITH_REGS is enabled.
1638
1639config CC_HAS_BRANCH_PROT_PAC_RET
1640	# GCC 9 or later, clang 8 or later
1641	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1642
1643config CC_HAS_SIGN_RETURN_ADDRESS
1644	# GCC 7, 8
1645	def_bool $(cc-option,-msign-return-address=all)
1646
1647config AS_HAS_PAC
1648	def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1649
1650config AS_HAS_CFI_NEGATE_RA_STATE
1651	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1652
1653endmenu
1654
1655menu "ARMv8.4 architectural features"
1656
1657config ARM64_AMU_EXTN
1658	bool "Enable support for the Activity Monitors Unit CPU extension"
1659	default y
1660	help
1661	  The activity monitors extension is an optional extension introduced
1662	  by the ARMv8.4 CPU architecture. This enables support for version 1
1663	  of the activity monitors architecture, AMUv1.
1664
1665	  To enable the use of this extension on CPUs that implement it, say Y.
1666
1667	  Note that for architectural reasons, firmware _must_ implement AMU
1668	  support when running on CPUs that present the activity monitors
1669	  extension. The required support is present in:
1670	    * Version 1.5 and later of the ARM Trusted Firmware
1671
1672	  For kernels that have this configuration enabled but boot with broken
1673	  firmware, you may need to say N here until the firmware is fixed.
1674	  Otherwise you may experience firmware panics or lockups when
1675	  accessing the counter registers. Even if you are not observing these
1676	  symptoms, the values returned by the register reads might not
1677	  correctly reflect reality. Most commonly, the value read will be 0,
1678	  indicating that the counter is not enabled.
1679
1680config AS_HAS_ARMV8_4
1681	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1682
1683config ARM64_TLB_RANGE
1684	bool "Enable support for tlbi range feature"
1685	default y
1686	depends on AS_HAS_ARMV8_4
1687	help
1688	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1689	  range of input addresses.
1690
1691	  The feature introduces new assembly instructions, and they were
1692	  support when binutils >= 2.30.
1693
1694endmenu
1695
1696menu "ARMv8.5 architectural features"
1697
1698config AS_HAS_ARMV8_5
1699	def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1700
1701config ARM64_BTI
1702	bool "Branch Target Identification support"
1703	default y
1704	help
1705	  Branch Target Identification (part of the ARMv8.5 Extensions)
1706	  provides a mechanism to limit the set of locations to which computed
1707	  branch instructions such as BR or BLR can jump.
1708
1709	  To make use of BTI on CPUs that support it, say Y.
1710
1711	  BTI is intended to provide complementary protection to other control
1712	  flow integrity protection mechanisms, such as the Pointer
1713	  authentication mechanism provided as part of the ARMv8.3 Extensions.
1714	  For this reason, it does not make sense to enable this option without
1715	  also enabling support for pointer authentication.  Thus, when
1716	  enabling this option you should also select ARM64_PTR_AUTH=y.
1717
1718	  Userspace binaries must also be specifically compiled to make use of
1719	  this mechanism.  If you say N here or the hardware does not support
1720	  BTI, such binaries can still run, but you get no additional
1721	  enforcement of branch destinations.
1722
1723config ARM64_BTI_KERNEL
1724	bool "Use Branch Target Identification for kernel"
1725	default y
1726	depends on ARM64_BTI
1727	depends on ARM64_PTR_AUTH_KERNEL
1728	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1729	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1730	depends on !CC_IS_GCC || GCC_VERSION >= 100100
1731	# https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1732	depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1733	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1734	help
1735	  Build the kernel with Branch Target Identification annotations
1736	  and enable enforcement of this for kernel code. When this option
1737	  is enabled and the system supports BTI all kernel code including
1738	  modular code must have BTI enabled.
1739
1740config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1741	# GCC 9 or later, clang 8 or later
1742	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1743
1744config ARM64_E0PD
1745	bool "Enable support for E0PD"
1746	default y
1747	help
1748	  E0PD (part of the ARMv8.5 extensions) allows us to ensure
1749	  that EL0 accesses made via TTBR1 always fault in constant time,
1750	  providing similar benefits to KASLR as those provided by KPTI, but
1751	  with lower overhead and without disrupting legitimate access to
1752	  kernel memory such as SPE.
1753
1754	  This option enables E0PD for TTBR1 where available.
1755
1756config ARCH_RANDOM
1757	bool "Enable support for random number generation"
1758	default y
1759	help
1760	  Random number generation (part of the ARMv8.5 Extensions)
1761	  provides a high bandwidth, cryptographically secure
1762	  hardware random number generator.
1763
1764config ARM64_AS_HAS_MTE
1765	# Initial support for MTE went in binutils 2.32.0, checked with
1766	# ".arch armv8.5-a+memtag" below. However, this was incomplete
1767	# as a late addition to the final architecture spec (LDGM/STGM)
1768	# is only supported in the newer 2.32.x and 2.33 binutils
1769	# versions, hence the extra "stgm" instruction check below.
1770	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1771
1772config ARM64_MTE
1773	bool "Memory Tagging Extension support"
1774	default y
1775	depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1776	depends on AS_HAS_ARMV8_5
1777	depends on AS_HAS_LSE_ATOMICS
1778	# Required for tag checking in the uaccess routines
1779	depends on ARM64_PAN
1780	select ARCH_USES_HIGH_VMA_FLAGS
1781	help
1782	  Memory Tagging (part of the ARMv8.5 Extensions) provides
1783	  architectural support for run-time, always-on detection of
1784	  various classes of memory error to aid with software debugging
1785	  to eliminate vulnerabilities arising from memory-unsafe
1786	  languages.
1787
1788	  This option enables the support for the Memory Tagging
1789	  Extension at EL0 (i.e. for userspace).
1790
1791	  Selecting this option allows the feature to be detected at
1792	  runtime. Any secondary CPU not implementing this feature will
1793	  not be allowed a late bring-up.
1794
1795	  Userspace binaries that want to use this feature must
1796	  explicitly opt in. The mechanism for the userspace is
1797	  described in:
1798
1799	  Documentation/arm64/memory-tagging-extension.rst.
1800
1801endmenu
1802
1803menu "ARMv8.7 architectural features"
1804
1805config ARM64_EPAN
1806	bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1807	default y
1808	depends on ARM64_PAN
1809	help
1810	 Enhanced Privileged Access Never (EPAN) allows Privileged
1811	 Access Never to be used with Execute-only mappings.
1812
1813	 The feature is detected at runtime, and will remain disabled
1814	 if the cpu does not implement the feature.
1815endmenu
1816
1817config ARM64_SVE
1818	bool "ARM Scalable Vector Extension support"
1819	default y
1820	help
1821	  The Scalable Vector Extension (SVE) is an extension to the AArch64
1822	  execution state which complements and extends the SIMD functionality
1823	  of the base architecture to support much larger vectors and to enable
1824	  additional vectorisation opportunities.
1825
1826	  To enable use of this extension on CPUs that implement it, say Y.
1827
1828	  On CPUs that support the SVE2 extensions, this option will enable
1829	  those too.
1830
1831	  Note that for architectural reasons, firmware _must_ implement SVE
1832	  support when running on SVE capable hardware.  The required support
1833	  is present in:
1834
1835	    * version 1.5 and later of the ARM Trusted Firmware
1836	    * the AArch64 boot wrapper since commit 5e1261e08abf
1837	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
1838
1839	  For other firmware implementations, consult the firmware documentation
1840	  or vendor.
1841
1842	  If you need the kernel to boot on SVE-capable hardware with broken
1843	  firmware, you may need to say N here until you get your firmware
1844	  fixed.  Otherwise, you may experience firmware panics or lockups when
1845	  booting the kernel.  If unsure and you are not observing these
1846	  symptoms, you should assume that it is safe to say Y.
1847
1848config ARM64_MODULE_PLTS
1849	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1850	depends on MODULES
1851	select HAVE_MOD_ARCH_SPECIFIC
1852	help
1853	  Allocate PLTs when loading modules so that jumps and calls whose
1854	  targets are too far away for their relative offsets to be encoded
1855	  in the instructions themselves can be bounced via veneers in the
1856	  module's PLT. This allows modules to be allocated in the generic
1857	  vmalloc area after the dedicated module memory area has been
1858	  exhausted.
1859
1860	  When running with address space randomization (KASLR), the module
1861	  region itself may be too far away for ordinary relative jumps and
1862	  calls, and so in that case, module PLTs are required and cannot be
1863	  disabled.
1864
1865	  Specific errata workaround(s) might also force module PLTs to be
1866	  enabled (ARM64_ERRATUM_843419).
1867
1868config ARM64_PSEUDO_NMI
1869	bool "Support for NMI-like interrupts"
1870	select ARM_GIC_V3
1871	help
1872	  Adds support for mimicking Non-Maskable Interrupts through the use of
1873	  GIC interrupt priority. This support requires version 3 or later of
1874	  ARM GIC.
1875
1876	  This high priority configuration for interrupts needs to be
1877	  explicitly enabled by setting the kernel parameter
1878	  "irqchip.gicv3_pseudo_nmi" to 1.
1879
1880	  If unsure, say N
1881
1882if ARM64_PSEUDO_NMI
1883config ARM64_DEBUG_PRIORITY_MASKING
1884	bool "Debug interrupt priority masking"
1885	help
1886	  This adds runtime checks to functions enabling/disabling
1887	  interrupts when using priority masking. The additional checks verify
1888	  the validity of ICC_PMR_EL1 when calling concerned functions.
1889
1890	  If unsure, say N
1891endif
1892
1893config RELOCATABLE
1894	bool "Build a relocatable kernel image" if EXPERT
1895	select ARCH_HAS_RELR
1896	default y
1897	help
1898	  This builds the kernel as a Position Independent Executable (PIE),
1899	  which retains all relocation metadata required to relocate the
1900	  kernel binary at runtime to a different virtual address than the
1901	  address it was linked at.
1902	  Since AArch64 uses the RELA relocation format, this requires a
1903	  relocation pass at runtime even if the kernel is loaded at the
1904	  same address it was linked at.
1905
1906config RANDOMIZE_BASE
1907	bool "Randomize the address of the kernel image"
1908	select ARM64_MODULE_PLTS if MODULES
1909	select RELOCATABLE
1910	help
1911	  Randomizes the virtual address at which the kernel image is
1912	  loaded, as a security feature that deters exploit attempts
1913	  relying on knowledge of the location of kernel internals.
1914
1915	  It is the bootloader's job to provide entropy, by passing a
1916	  random u64 value in /chosen/kaslr-seed at kernel entry.
1917
1918	  When booting via the UEFI stub, it will invoke the firmware's
1919	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1920	  to the kernel proper. In addition, it will randomise the physical
1921	  location of the kernel Image as well.
1922
1923	  If unsure, say N.
1924
1925config RANDOMIZE_MODULE_REGION_FULL
1926	bool "Randomize the module region over a 2 GB range"
1927	depends on RANDOMIZE_BASE
1928	default y
1929	help
1930	  Randomizes the location of the module region inside a 2 GB window
1931	  covering the core kernel. This way, it is less likely for modules
1932	  to leak information about the location of core kernel data structures
1933	  but it does imply that function calls between modules and the core
1934	  kernel will need to be resolved via veneers in the module PLT.
1935
1936	  When this option is not set, the module region will be randomized over
1937	  a limited range that contains the [_stext, _etext] interval of the
1938	  core kernel, so branch relocations are almost always in range unless
1939	  ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
1940	  particular case of region exhaustion, modules might be able to fall
1941	  back to a larger 2GB area.
1942
1943config CC_HAVE_STACKPROTECTOR_SYSREG
1944	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1945
1946config STACKPROTECTOR_PER_TASK
1947	def_bool y
1948	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1949
1950endmenu
1951
1952menu "Boot options"
1953
1954config ARM64_ACPI_PARKING_PROTOCOL
1955	bool "Enable support for the ARM64 ACPI parking protocol"
1956	depends on ACPI
1957	help
1958	  Enable support for the ARM64 ACPI parking protocol. If disabled
1959	  the kernel will not allow booting through the ARM64 ACPI parking
1960	  protocol even if the corresponding data is present in the ACPI
1961	  MADT table.
1962
1963config CMDLINE
1964	string "Default kernel command string"
1965	default ""
1966	help
1967	  Provide a set of default command-line options at build time by
1968	  entering them here. As a minimum, you should specify the the
1969	  root device (e.g. root=/dev/nfs).
1970
1971choice
1972	prompt "Kernel command line type" if CMDLINE != ""
1973	default CMDLINE_FROM_BOOTLOADER
1974	help
1975	  Choose how the kernel will handle the provided default kernel
1976	  command line string.
1977
1978config CMDLINE_FROM_BOOTLOADER
1979	bool "Use bootloader kernel arguments if available"
1980	help
1981	  Uses the command-line options passed by the boot loader. If
1982	  the boot loader doesn't provide any, the default kernel command
1983	  string provided in CMDLINE will be used.
1984
1985config CMDLINE_FORCE
1986	bool "Always use the default kernel command string"
1987	help
1988	  Always use the default kernel command string, even if the boot
1989	  loader passes other arguments to the kernel.
1990	  This is useful if you cannot or don't want to change the
1991	  command-line options your boot loader passes to the kernel.
1992
1993endchoice
1994
1995config EFI_STUB
1996	bool
1997
1998config EFI
1999	bool "UEFI runtime support"
2000	depends on OF && !CPU_BIG_ENDIAN
2001	depends on KERNEL_MODE_NEON
2002	select ARCH_SUPPORTS_ACPI
2003	select LIBFDT
2004	select UCS2_STRING
2005	select EFI_PARAMS_FROM_FDT
2006	select EFI_RUNTIME_WRAPPERS
2007	select EFI_STUB
2008	select EFI_GENERIC_STUB
2009	imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2010	default y
2011	help
2012	  This option provides support for runtime services provided
2013	  by UEFI firmware (such as non-volatile variables, realtime
2014          clock, and platform reset). A UEFI stub is also provided to
2015	  allow the kernel to be booted as an EFI application. This
2016	  is only useful on systems that have UEFI firmware.
2017
2018config DMI
2019	bool "Enable support for SMBIOS (DMI) tables"
2020	depends on EFI
2021	default y
2022	help
2023	  This enables SMBIOS/DMI feature for systems.
2024
2025	  This option is only useful on systems that have UEFI firmware.
2026	  However, even with this option, the resultant kernel should
2027	  continue to boot on existing non-UEFI platforms.
2028
2029endmenu
2030
2031config SYSVIPC_COMPAT
2032	def_bool y
2033	depends on COMPAT && SYSVIPC
2034
2035menu "Power management options"
2036
2037source "kernel/power/Kconfig"
2038
2039config ARCH_HIBERNATION_POSSIBLE
2040	def_bool y
2041	depends on CPU_PM
2042
2043config ARCH_HIBERNATION_HEADER
2044	def_bool y
2045	depends on HIBERNATION
2046
2047config ARCH_SUSPEND_POSSIBLE
2048	def_bool y
2049
2050endmenu
2051
2052menu "CPU Power Management"
2053
2054source "drivers/cpuidle/Kconfig"
2055
2056source "drivers/cpufreq/Kconfig"
2057
2058endmenu
2059
2060source "drivers/acpi/Kconfig"
2061
2062source "arch/arm64/kvm/Kconfig"
2063
2064if CRYPTO
2065source "arch/arm64/crypto/Kconfig"
2066endif
2067