1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 4 * 5 * Based on davinci_dvevm.h. Original Copyrights follow: 6 * 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * Board 15 */ 16 17 /* 18 * SoC Configuration 19 */ 20 #define CONFIG_MACH_OMAPL138_LCDK 21 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 22 #define CONFIG_SYS_OSCIN_FREQ 24000000 23 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 24 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 25 #define CONFIG_SYS_HZ 1000 26 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY 27 28 /* 29 * Memory Info 30 */ 31 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 32 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 33 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 34 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 35 36 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE 37 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 38 39 /* memtest start addr */ 40 41 /* memtest will be run on 16MB */ 42 43 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 44 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 45 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 46 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 47 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 48 DAVINCI_SYSCFG_SUSPSRC_I2C) 49 50 /* 51 * PLL configuration 52 */ 53 54 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ 55 #define CONFIG_SYS_DA850_PLL0_PLLM 18 56 #define CONFIG_SYS_DA850_PLL1_PLLM 21 57 58 /* 59 * DDR2 memory configuration 60 */ 61 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 62 DV_DDR_PHY_EXT_STRBEN | \ 63 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 64 65 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 66 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 67 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 68 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 69 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 70 (4 << DV_DDR_SDCR_CL_SHIFT) | \ 71 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 72 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 73 74 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 75 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 76 77 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 78 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 79 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ 80 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 81 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ 82 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 83 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 84 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 85 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 86 87 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 88 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 89 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 90 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 91 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 92 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 93 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 94 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 95 96 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 97 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 98 99 /* 100 * Serial Driver info 101 */ 102 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 103 104 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE 105 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) 106 107 /* 108 * I2C Configuration 109 */ 110 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 111 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 112 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 113 114 /* 115 * Flash & Environment 116 */ 117 #ifdef CONFIG_MTD_RAW_NAND 118 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 119 #define CONFIG_SYS_NAND_PAGE_2K 120 #define CONFIG_SYS_NAND_CS 3 121 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 122 #define CONFIG_SYS_NAND_MASK_CLE 0x10 123 #define CONFIG_SYS_NAND_MASK_ALE 0x8 124 #undef CONFIG_SYS_NAND_HW_ECC 125 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 126 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 127 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC 128 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 129 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 130 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 131 #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K 132 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 133 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 134 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 135 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 136 CONFIG_SYS_MALLOC_LEN - \ 137 GENERATED_GBL_DATA_SIZE) 138 #define CONFIG_SYS_NAND_ECCPOS { \ 139 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 140 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 141 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 142 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } 143 #define CONFIG_SYS_NAND_PAGE_COUNT 64 144 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 145 #define CONFIG_SYS_NAND_ECCSIZE 512 146 #define CONFIG_SYS_NAND_ECCBYTES 10 147 #define CONFIG_SYS_NAND_OOBSIZE 64 148 #define CONFIG_SPL_NAND_LOAD 149 #endif 150 151 /* 152 * Network & Ethernet Configuration 153 */ 154 #ifdef CONFIG_DRIVER_TI_EMAC 155 #define CONFIG_NET_RETRY_COUNT 10 156 #endif 157 158 /* 159 * U-Boot general configuration 160 */ 161 #define CONFIG_BOOTFILE "zImage" /* Boot file name */ 162 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 163 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 164 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 165 166 /* 167 * USB Configs 168 */ 169 #define CONFIG_USB_OHCI_NEW 170 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 171 172 /* 173 * Linux Information 174 */ 175 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 176 #define CONFIG_CMDLINE_TAG 177 #define CONFIG_REVISION_TAG 178 #define CONFIG_SETUP_MEMORY_TAGS 179 #define CONFIG_BOOTCOMMAND \ 180 "run envboot; " \ 181 "run mmcboot; " 182 183 #define DEFAULT_LINUX_BOOT_ENV \ 184 "loadaddr=0xc0700000\0" \ 185 "fdtaddr=0xc0600000\0" \ 186 "scriptaddr=0xc0600000\0" 187 188 #include <environment/ti/mmc.h> 189 190 #define CONFIG_EXTRA_ENV_SETTINGS \ 191 DEFAULT_LINUX_BOOT_ENV \ 192 DEFAULT_MMC_TI_ARGS \ 193 "bootpart=0:2\0" \ 194 "bootdir=/boot\0" \ 195 "bootfile=zImage\0" \ 196 "fdtfile=da850-lcdk.dtb\0" \ 197 "boot_fdt=yes\0" \ 198 "boot_fit=0\0" \ 199 "console=ttyS2,115200n8\0" 200 201 #ifdef CONFIG_CMD_BDI 202 #define CONFIG_CLOCKS 203 #endif 204 205 /* SD/MMC */ 206 207 /* defines for SPL */ 208 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 209 CONFIG_SYS_MALLOC_LEN) 210 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 211 #define CONFIG_SPL_STACK 0x8001ff00 212 #define CONFIG_SPL_MAX_FOOTPRINT 32768 213 #define CONFIG_SPL_PAD_TO 32768 214 215 /* additions for new relocation code, must added to all boards */ 216 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 217 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 218 GENERATED_GBL_DATA_SIZE) 219 220 #include <asm/arch/hardware.h> 221 222 #endif /* __CONFIG_H */ 223