1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select ROM_EXCEPTION_VECTORS 18 select SUPPORTS_BIG_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select SUPPORTS_LITTLE_ENDIAN 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_INSERT_BOOT_CONFIG 32 select MIPS_L1_CACHE_SHIFT_6 33 select MIPS_L2_CACHE 34 select OF_CONTROL 35 select OF_ISA_BUS 36 select ROM_EXCEPTION_VECTORS 37 select SUPPORTS_BIG_ENDIAN 38 select SUPPORTS_CPU_MIPS32_R1 39 select SUPPORTS_CPU_MIPS32_R2 40 select SUPPORTS_CPU_MIPS32_R6 41 select SUPPORTS_CPU_MIPS64_R1 42 select SUPPORTS_CPU_MIPS64_R2 43 select SUPPORTS_CPU_MIPS64_R6 44 select SUPPORTS_LITTLE_ENDIAN 45 select SWAP_IO_SPACE 46 imply CMD_DM 47 48config TARGET_VCT 49 bool "Support vct" 50 select ROM_EXCEPTION_VECTORS 51 select SUPPORTS_BIG_ENDIAN 52 select SUPPORTS_CPU_MIPS32_R1 53 select SUPPORTS_CPU_MIPS32_R2 54 select SYS_MIPS_CACHE_INIT_RAM_LOAD 55 56config ARCH_ATH79 57 bool "Support QCA/Atheros ath79" 58 select DM 59 select OF_CONTROL 60 imply CMD_DM 61 62config ARCH_MSCC 63 bool "Support MSCC VCore-III" 64 select OF_CONTROL 65 select DM 66 67config ARCH_BMIPS 68 bool "Support BMIPS SoCs" 69 select CLK 70 select CPU 71 select DM 72 select OF_CONTROL 73 select RAM 74 select SYSRESET 75 imply CMD_DM 76 77config ARCH_MTMIPS 78 bool "Support MediaTek MIPS platforms" 79 select CLK 80 imply CMD_DM 81 select DISPLAY_CPUINFO 82 select DM 83 imply DM_ETH 84 imply DM_GPIO 85 select DM_RESET 86 select DM_SERIAL 87 select PINCTRL 88 select PINMUX 89 select PINCONF 90 select RESET_MTMIPS 91 imply DM_SPI 92 imply DM_SPI_FLASH 93 select LAST_STAGE_INIT 94 select MIPS_TUNE_24KC 95 select OF_CONTROL 96 select ROM_EXCEPTION_VECTORS 97 select SUPPORTS_CPU_MIPS32_R1 98 select SUPPORTS_CPU_MIPS32_R2 99 select SUPPORTS_LITTLE_ENDIAN 100 select SUPPORT_SPL 101 102config ARCH_JZ47XX 103 bool "Support Ingenic JZ47xx" 104 select SUPPORT_SPL 105 select OF_CONTROL 106 select DM 107 108config ARCH_OCTEON 109 bool "Support Marvell Octeon CN7xxx platforms" 110 select CPU_CAVIUM_OCTEON 111 select DISPLAY_CPUINFO 112 select DMA_ADDR_T_64BIT 113 select DM 114 select DM_ETH 115 select DM_GPIO 116 select DM_I2C 117 select DM_SERIAL 118 select DM_SPI 119 select MIPS_L2_CACHE 120 select MIPS_MACH_EARLY_INIT 121 select MIPS_TUNE_OCTEON3 122 select ROM_EXCEPTION_VECTORS 123 select SUPPORTS_BIG_ENDIAN 124 select SUPPORTS_CPU_MIPS64_OCTEON 125 select PHYS_64BIT 126 select OF_CONTROL 127 select OF_LIVE 128 imply CMD_DM 129 130config MACH_PIC32 131 bool "Support Microchip PIC32" 132 select DM 133 select OF_CONTROL 134 imply CMD_DM 135 136config TARGET_BOSTON 137 bool "Support Boston" 138 select DM 139 select DM_SERIAL 140 select MIPS_CM 141 select MIPS_L1_CACHE_SHIFT_6 142 select MIPS_L2_CACHE 143 select OF_BOARD_SETUP 144 select OF_CONTROL 145 select ROM_EXCEPTION_VECTORS 146 select SUPPORTS_BIG_ENDIAN 147 select SUPPORTS_CPU_MIPS32_R1 148 select SUPPORTS_CPU_MIPS32_R2 149 select SUPPORTS_CPU_MIPS32_R6 150 select SUPPORTS_CPU_MIPS64_R1 151 select SUPPORTS_CPU_MIPS64_R2 152 select SUPPORTS_CPU_MIPS64_R6 153 select SUPPORTS_LITTLE_ENDIAN 154 imply CMD_DM 155 156config TARGET_XILFPGA 157 bool "Support Imagination Xilfpga" 158 select DM 159 select DM_ETH 160 select DM_GPIO 161 select DM_SERIAL 162 select MIPS_L1_CACHE_SHIFT_4 163 select OF_CONTROL 164 select ROM_EXCEPTION_VECTORS 165 select SUPPORTS_CPU_MIPS32_R1 166 select SUPPORTS_CPU_MIPS32_R2 167 select SUPPORTS_LITTLE_ENDIAN 168 imply CMD_DM 169 help 170 This supports IMGTEC MIPSfpga platform 171 172endchoice 173 174source "board/imgtec/boston/Kconfig" 175source "board/imgtec/malta/Kconfig" 176source "board/imgtec/xilfpga/Kconfig" 177source "board/qemu-mips/Kconfig" 178source "arch/mips/mach-ath79/Kconfig" 179source "arch/mips/mach-mscc/Kconfig" 180source "arch/mips/mach-bmips/Kconfig" 181source "arch/mips/mach-jz47xx/Kconfig" 182source "arch/mips/mach-pic32/Kconfig" 183source "arch/mips/mach-mtmips/Kconfig" 184source "arch/mips/mach-octeon/Kconfig" 185 186if MIPS 187 188choice 189 prompt "Endianness selection" 190 help 191 Some MIPS boards can be configured for either little or big endian 192 byte order. These modes require different U-Boot images. In general there 193 is one preferred byteorder for a particular system but some systems are 194 just as commonly used in the one or the other endianness. 195 196config SYS_BIG_ENDIAN 197 bool "Big endian" 198 depends on SUPPORTS_BIG_ENDIAN 199 200config SYS_LITTLE_ENDIAN 201 bool "Little endian" 202 depends on SUPPORTS_LITTLE_ENDIAN 203 204endchoice 205 206choice 207 prompt "CPU selection" 208 default CPU_MIPS32_R2 209 210config CPU_MIPS32_R1 211 bool "MIPS32 Release 1" 212 depends on SUPPORTS_CPU_MIPS32_R1 213 select 32BIT 214 help 215 Choose this option to build an U-Boot for release 1 through 5 of the 216 MIPS32 architecture. 217 218config CPU_MIPS32_R2 219 bool "MIPS32 Release 2" 220 depends on SUPPORTS_CPU_MIPS32_R2 221 select 32BIT 222 help 223 Choose this option to build an U-Boot for release 2 through 5 of the 224 MIPS32 architecture. 225 226config CPU_MIPS32_R6 227 bool "MIPS32 Release 6" 228 depends on SUPPORTS_CPU_MIPS32_R6 229 select 32BIT 230 help 231 Choose this option to build an U-Boot for release 6 or later of the 232 MIPS32 architecture. 233 234config CPU_MIPS64_R1 235 bool "MIPS64 Release 1" 236 depends on SUPPORTS_CPU_MIPS64_R1 237 select 64BIT 238 help 239 Choose this option to build a kernel for release 1 through 5 of the 240 MIPS64 architecture. 241 242config CPU_MIPS64_R2 243 bool "MIPS64 Release 2" 244 depends on SUPPORTS_CPU_MIPS64_R2 245 select 64BIT 246 help 247 Choose this option to build a kernel for release 2 through 5 of the 248 MIPS64 architecture. 249 250config CPU_MIPS64_R6 251 bool "MIPS64 Release 6" 252 depends on SUPPORTS_CPU_MIPS64_R6 253 select 64BIT 254 help 255 Choose this option to build a kernel for release 6 or later of the 256 MIPS64 architecture. 257 258config CPU_MIPS64_OCTEON 259 bool "Marvell Octeon series of CPUs" 260 depends on SUPPORTS_CPU_MIPS64_OCTEON 261 select 64BIT 262 help 263 Choose this option for Marvell Octeon CPUs. These CPUs are between 264 MIPS64 R5 and R6 with other extensions. 265 266endchoice 267 268menu "General setup" 269 270config ROM_EXCEPTION_VECTORS 271 bool "Build U-Boot image with exception vectors" 272 help 273 Enable this to include exception vectors in the U-Boot image. This is 274 required if the U-Boot entry point is equal to the address of the 275 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 276 U-Boot booted from parallel NOR flash). 277 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 278 In that case the image size will be reduced by 0x500 bytes. 279 280config MIPS_CM_BASE 281 hex "MIPS CM GCR Base Address" 282 depends on MIPS_CM 283 default 0x16100000 if TARGET_BOSTON 284 default 0x1fbf8000 285 help 286 The physical base address at which to map the MIPS Coherence Manager 287 Global Configuration Registers (GCRs). This should be set such that 288 the GCRs occupy a region of the physical address space which is 289 otherwise unused, or at minimum that software doesn't need to access. 290 291config MIPS_CACHE_INDEX_BASE 292 hex "Index base address for cache initialisation" 293 default 0x80000000 if CPU_MIPS32 294 default 0xffffffff80000000 if CPU_MIPS64 295 help 296 This is the base address for a memory block, which is used for 297 initialising the cache lines. This is also the base address of a memory 298 block which is used for loading and filling cache lines when 299 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. 300 Normally this is CKSEG0. If the MIPS system needs to move this block 301 to some SRAM or ScratchPad RAM, adapt this option accordingly. 302 303config MIPS_MACH_EARLY_INIT 304 bool "Enable mach specific very early init code" 305 help 306 Use this to enable the call to mips_mach_early_init() very early 307 from start.S. This function can be used e.g. to do some very early 308 CPU / SoC intitialization or image copying. Its called very early 309 and at this stage the PC might not match the linking address 310 (CONFIG_TEXT_BASE) - no absolute jump done until this call. 311 312config MIPS_CACHE_SETUP 313 bool "Allow generic start code to initialize and setup caches" 314 default n if SKIP_LOWLEVEL_INIT 315 default y 316 help 317 This allows the generic start code to invoke the generic initialization 318 of the CPU caches. Disabling this can be useful for RAM boot scenarios 319 (EJTAG, SPL payload) or for machines which don't need cache initialization 320 or which want to provide their own cache implementation. 321 322 If unsure, say yes. 323 324config MIPS_CACHE_DISABLE 325 bool "Allow generic start code to initially disable caches" 326 default n if SKIP_LOWLEVEL_INIT 327 default y 328 help 329 This allows the generic start code to initially disable the CPU caches 330 and run uncached until the caches are initialized and enabled. Disabling 331 this can be useful on machines which don't need cache initialization or 332 which want to provide their own cache implementation. 333 334 If unsure, say yes. 335 336config MIPS_RELOCATION_TABLE_SIZE 337 hex "Relocation table size" 338 range 0x100 0x10000 339 default "0x8000" 340 ---help--- 341 A table of relocation data will be appended to the U-Boot binary 342 and parsed in relocate_code() to fix up all offsets in the relocated 343 U-Boot. 344 345 This option allows the amount of space reserved for the table to be 346 adjusted in a range from 256 up to 64k. The default is 32k and should 347 be ok in most cases. Reduce this value to shrink the size of U-Boot 348 binary. 349 350 The build will fail and a valid size suggested if this is too small. 351 352 If unsure, leave at the default value. 353 354config RESTORE_EXCEPTION_VECTOR_BASE 355 bool "Restore exception vector base before booting linux kernel" 356 default n 357 help 358 In U-Boot the exception vector base will be moved to top of memory, 359 to be used to display register dump when exception occurs. 360 But some old linux kernel does not honor the base set in CP0_EBASE. 361 A modified exception vector base will cause kernel crash. 362 363 This option will restore the exception vector base to its previous 364 value. 365 366 If unsure, say N. 367 368config OVERRIDE_EXCEPTION_VECTOR_BASE 369 bool "Override the exception vector base to be restored" 370 depends on RESTORE_EXCEPTION_VECTOR_BASE 371 default n 372 help 373 Enable this option if you want to use a different exception vector 374 base rather than the previously saved one. 375 376config NEW_EXCEPTION_VECTOR_BASE 377 hex "New exception vector base" 378 depends on OVERRIDE_EXCEPTION_VECTOR_BASE 379 range 0x80000000 0xbffff000 380 default 0x80000000 381 help 382 The exception vector base to be restored before booting linux kernel 383 384config INIT_STACK_WITHOUT_MALLOC_F 385 bool "Do not reserve malloc space on initial stack" 386 default n 387 help 388 Enable this option if you don't want to reserve malloc space on 389 initial stack. This is useful if the initial stack can't hold large 390 malloc space. Platform should set the malloc_base later when DRAM is 391 ready to use. 392 393config SPL_INIT_STACK_WITHOUT_MALLOC_F 394 bool "Do not reserve malloc space on initial stack in SPL" 395 default n 396 help 397 Enable this option if you don't want to reserve malloc space on 398 initial stack. This is useful if the initial stack can't hold large 399 malloc space. Platform should set the malloc_base later when DRAM is 400 ready to use. 401 402config SPL_LOADER_SUPPORT 403 bool 404 default n 405 help 406 Enable this option if you want to use SPL loaders without DM enabled. 407 408endmenu 409 410menu "OS boot interface" 411 412config MIPS_BOOT_CMDLINE_LEGACY 413 bool "Hand over legacy command line to Linux kernel" 414 default y 415 help 416 Enable this option if you want U-Boot to hand over the Yamon-style 417 command line to the kernel. All bootargs will be prepared as argc/argv 418 compatible list. The argument count (argc) is stored in register $a0. 419 The address of the argument list (argv) is stored in register $a1. 420 421config MIPS_BOOT_ENV_LEGACY 422 bool "Hand over legacy environment to Linux kernel" 423 default y 424 help 425 Enable this option if you want U-Boot to hand over the Yamon-style 426 environment to the kernel. Information like memory size, initrd 427 address and size will be prepared as zero-terminated key/value list. 428 The address of the environment is stored in register $a2. 429 430config MIPS_BOOT_FDT 431 bool "Hand over a flattened device tree to Linux kernel" 432 default n 433 help 434 Enable this option if you want U-Boot to hand over a flattened 435 device tree to the kernel. According to UHI register $a0 will be set 436 to -2 and the FDT address is stored in $a1. 437 438endmenu 439 440config SUPPORTS_BIG_ENDIAN 441 bool 442 443config SUPPORTS_LITTLE_ENDIAN 444 bool 445 446config SUPPORTS_CPU_MIPS32_R1 447 bool 448 449config SUPPORTS_CPU_MIPS32_R2 450 bool 451 452config SUPPORTS_CPU_MIPS32_R6 453 bool 454 455config SUPPORTS_CPU_MIPS64_R1 456 bool 457 458config SUPPORTS_CPU_MIPS64_R2 459 bool 460 461config SUPPORTS_CPU_MIPS64_R6 462 bool 463 464config SUPPORTS_CPU_MIPS64_OCTEON 465 bool 466 467config CPU_CAVIUM_OCTEON 468 bool 469 470config CPU_MIPS32 471 bool 472 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 473 474config CPU_MIPS64 475 bool 476 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 477 default y if CPU_MIPS64_OCTEON 478 479config MIPS_TUNE_4KC 480 bool 481 482config MIPS_TUNE_14KC 483 bool 484 485config MIPS_TUNE_24KC 486 bool 487 488config MIPS_TUNE_34KC 489 bool 490 491config MIPS_TUNE_74KC 492 bool 493 494config MIPS_TUNE_OCTEON3 495 bool 496 497config 32BIT 498 bool 499 500config 64BIT 501 bool 502 503config SWAP_IO_SPACE 504 bool 505 506config SYS_MIPS_CACHE_INIT_RAM_LOAD 507 bool 508 509config MIPS_INIT_STACK_IN_SRAM 510 bool 511 default n 512 help 513 Select this if the initial stack frame could be setup in SRAM. 514 Normally the initial stack frame is set up in DRAM which is often 515 only available after lowlevel_init. With this option the initial 516 stack frame and the early C environment is set up before 517 lowlevel_init. Thus lowlevel_init does not need to be implemented 518 in assembler. 519 520config MIPS_SRAM_INIT 521 bool 522 default n 523 depends on MIPS_INIT_STACK_IN_SRAM 524 help 525 Select this if the SRAM for initial stack needs to be initialized 526 before it can be used. If enabled, a function mips_sram_init() will 527 be called just before setup_stack_gd. 528 529config DMA_ADDR_T_64BIT 530 bool 531 help 532 Select this to enable 64-bit DMA addressing 533 534config SYS_DCACHE_SIZE 535 int 536 default 0 537 help 538 The total size of the L1 Dcache, if known at compile time. 539 540config SYS_DCACHE_LINE_SIZE 541 int 542 default 0 543 help 544 The size of L1 Dcache lines, if known at compile time. 545 546config SYS_ICACHE_SIZE 547 int 548 default 0 549 help 550 The total size of the L1 ICache, if known at compile time. 551 552config SYS_ICACHE_LINE_SIZE 553 int 554 default 0 555 help 556 The size of L1 Icache lines, if known at compile time. 557 558config SYS_SCACHE_LINE_SIZE 559 int 560 default 0 561 help 562 The size of L2 cache lines, if known at compile time. 563 564 565config SYS_CACHE_SIZE_AUTO 566 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 567 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \ 568 SYS_SCACHE_LINE_SIZE = 0 569 help 570 Select this (or let it be auto-selected by not defining any cache 571 sizes) in order to allow U-Boot to automatically detect the sizes 572 of caches at runtime. This has a small cost in code size & runtime 573 so if you know the cache configuration for your system at compile 574 time it would be beneficial to configure it. 575 576config MIPS_L1_CACHE_SHIFT_4 577 bool 578 579config MIPS_L1_CACHE_SHIFT_5 580 bool 581 582config MIPS_L1_CACHE_SHIFT_6 583 bool 584 585config MIPS_L1_CACHE_SHIFT_7 586 bool 587 588config MIPS_L1_CACHE_SHIFT 589 int 590 default "7" if MIPS_L1_CACHE_SHIFT_7 591 default "6" if MIPS_L1_CACHE_SHIFT_6 592 default "5" if MIPS_L1_CACHE_SHIFT_5 593 default "4" if MIPS_L1_CACHE_SHIFT_4 594 default "5" 595 596config MIPS_L2_CACHE 597 bool 598 help 599 Select this if your system includes an L2 cache and you want U-Boot 600 to initialise & maintain it. 601 602config DYNAMIC_IO_PORT_BASE 603 bool 604 605config MIPS_CM 606 bool 607 help 608 Select this if your system contains a MIPS Coherence Manager and you 609 wish U-Boot to configure it or make use of it to retrieve system 610 information such as cache configuration. 611 612config MIPS_INSERT_BOOT_CONFIG 613 bool 614 default n 615 help 616 Enable this to insert some board-specific boot configuration in 617 the U-Boot binary at offset 0x10. 618 619config MIPS_BOOT_CONFIG_WORD0 620 hex 621 depends on MIPS_INSERT_BOOT_CONFIG 622 default 0x420 if TARGET_MALTA 623 default 0x0 624 help 625 Value which is inserted as boot config word 0. 626 627config MIPS_BOOT_CONFIG_WORD1 628 hex 629 depends on MIPS_INSERT_BOOT_CONFIG 630 default 0x0 631 help 632 Value which is inserted as boot config word 1. 633 634endif 635 636endmenu 637