1 2menuconfig MTD_RAW_NAND 3 bool "Raw NAND Device Support" 4if MTD_RAW_NAND 5 6config SYS_NAND_SELF_INIT 7 bool 8 help 9 This option, if enabled, provides more flexible and linux-like 10 NAND initialization process. 11 12config SYS_NAND_DRIVER_ECC_LAYOUT 13 bool 14 help 15 Omit standard ECC layouts to safe space. Select this if your driver 16 is known to provide its own ECC layout. 17 18config SYS_NAND_USE_FLASH_BBT 19 bool "Enable BBT (Bad Block Table) support" 20 help 21 Enable the BBT (Bad Block Table) usage. 22 23config NAND_ATMEL 24 bool "Support Atmel NAND controller" 25 imply SYS_NAND_USE_FLASH_BBT 26 help 27 Enable this driver for NAND flash platforms using an Atmel NAND 28 controller. 29 30if NAND_ATMEL 31 32config ATMEL_NAND_HWECC 33 bool "Atmel Hardware ECC" 34 default n 35 36config ATMEL_NAND_HW_PMECC 37 bool "Atmel Programmable Multibit ECC (PMECC)" 38 select ATMEL_NAND_HWECC 39 default n 40 help 41 The Programmable Multibit ECC (PMECC) controller is a programmable 42 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. 43 44config PMECC_CAP 45 int "PMECC Correctable ECC Bits" 46 depends on ATMEL_NAND_HW_PMECC 47 default 2 48 help 49 Correctable ECC bits, can be 2, 4, 8, 12, and 24. 50 51config PMECC_SECTOR_SIZE 52 int "PMECC Sector Size" 53 depends on ATMEL_NAND_HW_PMECC 54 default 512 55 help 56 Sector size, in bytes, can be 512 or 1024. 57 58config SPL_GENERATE_ATMEL_PMECC_HEADER 59 bool "Atmel PMECC Header Generation" 60 select ATMEL_NAND_HWECC 61 select ATMEL_NAND_HW_PMECC 62 default n 63 help 64 Generate Programmable Multibit ECC (PMECC) header for SPL image. 65 66endif 67 68config NAND_BRCMNAND 69 bool "Support Broadcom NAND controller" 70 depends on OF_CONTROL && DM && DM_MTD 71 help 72 Enable the driver for NAND flash on platforms using a Broadcom NAND 73 controller. 74 75config NAND_BRCMNAND_6368 76 bool "Support Broadcom NAND controller on bcm6368" 77 depends on NAND_BRCMNAND && ARCH_BMIPS 78 help 79 Enable support for broadcom nand driver on bcm6368. 80 81config NAND_BRCMNAND_68360 82 bool "Support Broadcom NAND controller on bcm68360" 83 depends on NAND_BRCMNAND && ARCH_BCM68360 84 help 85 Enable support for broadcom nand driver on bcm68360. 86 87config NAND_BRCMNAND_6838 88 bool "Support Broadcom NAND controller on bcm6838" 89 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 90 help 91 Enable support for broadcom nand driver on bcm6838. 92 93config NAND_BRCMNAND_6858 94 bool "Support Broadcom NAND controller on bcm6858" 95 depends on NAND_BRCMNAND && ARCH_BCM6858 96 help 97 Enable support for broadcom nand driver on bcm6858. 98 99config NAND_BRCMNAND_63158 100 bool "Support Broadcom NAND controller on bcm63158" 101 depends on NAND_BRCMNAND && ARCH_BCM63158 102 help 103 Enable support for broadcom nand driver on bcm63158. 104 105config NAND_DAVINCI 106 bool "Support TI Davinci NAND controller" 107 help 108 Enable this driver for NAND flash controllers available in TI Davinci 109 and Keystone2 platforms 110 111config NAND_DENALI 112 bool 113 select SYS_NAND_SELF_INIT 114 imply CMD_NAND 115 116config NAND_DENALI_DT 117 bool "Support Denali NAND controller as a DT device" 118 select NAND_DENALI 119 depends on OF_CONTROL && DM_MTD 120 help 121 Enable the driver for NAND flash on platforms using a Denali NAND 122 controller as a DT device. 123 124config NAND_LPC32XX_SLC 125 bool "Support LPC32XX_SLC controller" 126 help 127 Enable the LPC32XX SLC NAND controller. 128 129config NAND_OMAP_GPMC 130 bool "Support OMAP GPMC NAND controller" 131 depends on ARCH_OMAP2PLUS 132 help 133 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. 134 GPMC controller is used for parallel NAND flash devices, and can 135 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 136 and BCH16 ECC algorithms. 137 138config NAND_OMAP_GPMC_PREFETCH 139 bool "Enable GPMC Prefetch" 140 depends on NAND_OMAP_GPMC 141 default y 142 help 143 On OMAP platforms that use the GPMC controller 144 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that 145 uses the prefetch mode to speed up read operations. 146 147config NAND_OMAP_ELM 148 bool "Enable ELM driver for OMAPxx and AMxx platforms." 149 depends on NAND_OMAP_GPMC && !OMAP34XX 150 help 151 ELM controller is used for ECC error detection (not ECC calculation) 152 of BCH4, BCH8 and BCH16 ECC algorithms. 153 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 154 thus such SoC platforms need to depend on software library for ECC error 155 detection. However ECC calculation on such plaforms would still be 156 done by GPMC controller. 157 158config NAND_VF610_NFC 159 bool "Support for Freescale NFC for VF610" 160 select SYS_NAND_SELF_INIT 161 select SYS_NAND_DRIVER_ECC_LAYOUT 162 imply CMD_NAND 163 help 164 Enables support for NAND Flash Controller on some Freescale 165 processors like the VF610, MCF54418 or Kinetis K70. 166 The driver supports a maximum 2k page size. The driver 167 currently does not support hardware ECC. 168 169if NAND_VF610_NFC 170 171config NAND_VF610_NFC_DT 172 bool "Support Vybrid's vf610 NAND controller as a DT device" 173 depends on OF_CONTROL && DM_MTD 174 help 175 Enable the driver for Vybrid's vf610 NAND flash on platforms 176 using device tree. 177 178choice 179 prompt "Hardware ECC strength" 180 depends on NAND_VF610_NFC 181 default SYS_NAND_VF610_NFC_45_ECC_BYTES 182 help 183 Select the ECC strength used in the hardware BCH ECC block. 184 185config SYS_NAND_VF610_NFC_45_ECC_BYTES 186 bool "24-error correction (45 ECC bytes)" 187 188config SYS_NAND_VF610_NFC_60_ECC_BYTES 189 bool "32-error correction (60 ECC bytes)" 190 191endchoice 192 193endif 194 195config NAND_PXA3XX 196 bool "Support for NAND on PXA3xx and Armada 370/XP/38x" 197 select SYS_NAND_SELF_INIT 198 select DM_MTD 199 select REGMAP 200 select SYSCON 201 imply CMD_NAND 202 help 203 This enables the driver for the NAND flash device found on 204 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). 205 206config NAND_SUNXI 207 bool "Support for NAND on Allwinner SoCs" 208 default ARCH_SUNXI 209 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I 210 select SYS_NAND_SELF_INIT 211 select SYS_NAND_U_BOOT_LOCATIONS 212 select SPL_NAND_SUPPORT 213 imply CMD_NAND 214 ---help--- 215 Enable support for NAND. This option enables the standard and 216 SPL drivers. 217 The SPL driver only supports reading from the NAND using DMA 218 transfers. 219 220if NAND_SUNXI 221 222config NAND_SUNXI_SPL_ECC_STRENGTH 223 int "Allwinner NAND SPL ECC Strength" 224 default 64 225 226config NAND_SUNXI_SPL_ECC_SIZE 227 int "Allwinner NAND SPL ECC Step Size" 228 default 1024 229 230config NAND_SUNXI_SPL_USABLE_PAGE_SIZE 231 int "Allwinner NAND SPL Usable Page Size" 232 default 1024 233 234endif 235 236config NAND_ARASAN 237 bool "Configure Arasan Nand" 238 select SYS_NAND_SELF_INIT 239 depends on DM_MTD 240 imply CMD_NAND 241 help 242 This enables Nand driver support for Arasan nand flash 243 controller. This uses the hardware ECC for read and 244 write operations. 245 246config NAND_MXC 247 bool "MXC NAND support" 248 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 249 imply CMD_NAND 250 help 251 This enables the NAND driver for the NAND flash controller on the 252 i.MX27 / i.MX31 / i.MX5 rocessors. 253 254config NAND_MXS 255 bool "MXS NAND support" 256 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M 257 select SYS_NAND_SELF_INIT 258 imply CMD_NAND 259 select APBH_DMA 260 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M 261 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M 262 help 263 This enables NAND driver for the NAND flash controller on the 264 MXS processors. 265 266if NAND_MXS 267 268config NAND_MXS_DT 269 bool "Support MXS NAND controller as a DT device" 270 depends on OF_CONTROL && DM_MTD 271 help 272 Enable the driver for MXS NAND flash on platforms using 273 device tree. 274 275config NAND_MXS_USE_MINIMUM_ECC 276 bool "Use minimum ECC strength supported by the controller" 277 default false 278 279endif 280 281config NAND_ZYNQ 282 bool "Support for Zynq Nand controller" 283 select SYS_NAND_SELF_INIT 284 select DM_MTD 285 imply CMD_NAND 286 help 287 This enables Nand driver support for Nand flash controller 288 found on Zynq SoC. 289 290config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 291 bool "Enable use of 1st stage bootloader timing for NAND" 292 depends on NAND_ZYNQ 293 help 294 This flag prevent U-boot reconfigure NAND flash controller and reuse 295 the NAND timing from 1st stage bootloader. 296 297config NAND_OCTEONTX 298 bool "Support for OcteonTX NAND controller" 299 select SYS_NAND_SELF_INIT 300 imply CMD_NAND 301 help 302 This enables Nand flash controller hardware found on the OcteonTX 303 processors. 304 305config NAND_OCTEONTX_HW_ECC 306 bool "Support Hardware ECC for OcteonTX NAND controller" 307 depends on NAND_OCTEONTX 308 default y 309 help 310 This enables Hardware BCH engine found on the OcteonTX processors to 311 support ECC for NAND flash controller. 312 313config NAND_STM32_FMC2 314 bool "Support for NAND controller on STM32MP SoCs" 315 depends on ARCH_STM32MP 316 select SYS_NAND_SELF_INIT 317 imply CMD_NAND 318 help 319 Enables support for NAND Flash chips on SoCs containing the FMC2 320 NAND controller. This controller is found on STM32MP SoCs. 321 The controller supports a maximum 8k page size and supports 322 a maximum 8-bit correction error per sector of 512 bytes. 323 324config CORTINA_NAND 325 bool "Support for NAND controller on Cortina-Access SoCs" 326 depends on CORTINA_PLATFORM 327 select SYS_NAND_SELF_INIT 328 select DM_MTD 329 imply CMD_NAND 330 help 331 Enables support for NAND Flash chips on Coartina-Access SoCs platform 332 This controller is found on Presidio/Venus SoCs. 333 The controller supports a maximum 8k page size and supports 334 a maximum 40-bit error correction per sector of 1024 bytes. 335 336comment "Generic NAND options" 337 338config SYS_NAND_BLOCK_SIZE 339 hex "NAND chip eraseblock size" 340 depends on ARCH_SUNXI 341 help 342 Number of data bytes in one eraseblock for the NAND chip on the 343 board. This is the multiple of NAND_PAGE_SIZE and the number of 344 pages. 345 346config SYS_NAND_PAGE_SIZE 347 hex "NAND chip page size" 348 depends on ARCH_SUNXI 349 help 350 Number of data bytes in one page for the NAND chip on the 351 board, not including the OOB area. 352 353config SYS_NAND_OOBSIZE 354 hex "NAND chip OOB size" 355 depends on ARCH_SUNXI 356 help 357 Number of bytes in the Out-Of-Band area for the NAND chip on 358 the board. 359 360# Enhance depends when converting drivers to Kconfig which use this config 361# option (mxc_nand, ndfc, omap_gpmc). 362config SYS_NAND_BUSWIDTH_16BIT 363 bool "Use 16-bit NAND interface" 364 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI 365 help 366 Indicates that NAND device has 16-bit wide data-bus. In absence of this 367 config, bus-width of NAND device is assumed to be either 8-bit and later 368 determined by reading ONFI params. 369 Above config is useful when NAND device's bus-width information cannot 370 be determined from on-chip ONFI params, like in following scenarios: 371 - SPL boot does not support reading of ONFI parameters. This is done to 372 keep SPL code foot-print small. 373 - In current U-Boot flow using nand_init(), driver initialization 374 happens in board_nand_init() which is called before any device probe 375 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are 376 not available while configuring controller. So a static CONFIG_NAND_xx 377 is needed to know the device's bus-width in advance. 378 379config SYS_NAND_MAX_CHIPS 380 int "NAND max chips" 381 default 1 382 depends on NAND_ARASAN 383 help 384 The maximum number of NAND chips per device to be supported. 385 386if SPL 387 388config SYS_NAND_U_BOOT_LOCATIONS 389 bool "Define U-boot binaries locations in NAND" 390 help 391 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. 392 This option should not be enabled when compiling U-boot for boards 393 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h 394 file. 395 396config SYS_NAND_U_BOOT_OFFS 397 hex "Location in NAND to read U-Boot from" 398 default 0x800000 if NAND_SUNXI 399 depends on SYS_NAND_U_BOOT_LOCATIONS 400 help 401 Set the offset from the start of the nand where u-boot should be 402 loaded from. 403 404config SYS_NAND_U_BOOT_OFFS_REDUND 405 hex "Location in NAND to read U-Boot from" 406 default SYS_NAND_U_BOOT_OFFS 407 depends on SYS_NAND_U_BOOT_LOCATIONS 408 help 409 Set the offset from the start of the nand where the redundant u-boot 410 should be loaded from. 411 412config SPL_NAND_AM33XX_BCH 413 bool "Enables SPL-NAND driver which supports ELM based" 414 depends on NAND_OMAP_GPMC && !OMAP34XX 415 default y 416 help 417 Hardware ECC correction. This is useful for platforms which have ELM 418 hardware engine and use NAND boot mode. 419 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 420 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling 421 SPL-NAND driver with software ECC correction support. 422 423config SPL_NAND_DENALI 424 bool "Support Denali NAND controller for SPL" 425 help 426 This is a small implementation of the Denali NAND controller 427 for use on SPL. 428 429config NAND_DENALI_SPARE_AREA_SKIP_BYTES 430 int "Number of bytes skipped in OOB area" 431 depends on SPL_NAND_DENALI 432 range 0 63 433 help 434 This option specifies the number of bytes to skip from the beginning 435 of OOB area before last ECC sector data starts. This is potentially 436 used to preserve the bad block marker in the OOB area. 437 438config SPL_NAND_SIMPLE 439 bool "Use simple SPL NAND driver" 440 depends on !SPL_NAND_AM33XX_BCH 441 help 442 Support for NAND boot using simple NAND drivers that 443 expose the cmd_ctrl() interface. 444endif 445 446endif # if NAND 447