1config 64BIT
2	bool
3	default "$(ARCH)" != "arm32"
4	help
5	  Say yes to build a 64-bit Xen
6	  Say no to build a 32-bit Xen
7
8config ARM_32
9	def_bool y
10	depends on !64BIT
11
12config ARM_64
13	def_bool y
14	depends on 64BIT
15	select HAS_FAST_MULTIPLY
16
17config ARM
18	def_bool y
19	select HAS_ALTERNATIVE
20	select HAS_DEVICE_TREE
21	select HAS_PASSTHROUGH
22	select HAS_PDX
23	select IOMMU_FORCE_PT_SHARE
24
25config ARCH_DEFCONFIG
26	string
27	default "arch/arm/configs/arm32_defconfig" if ARM_32
28	default "arch/arm/configs/arm64_defconfig" if ARM_64
29
30menu "Architecture Features"
31
32source "arch/Kconfig"
33
34config ACPI
35	bool "ACPI (Advanced Configuration and Power Interface) Support" if EXPERT
36	depends on ARM_64
37	---help---
38
39	  Advanced Configuration and Power Interface (ACPI) support for Xen is
40	  an alternative to device tree on ARM64.
41
42config GICV3
43	bool "GICv3 driver"
44	depends on ARM_64 && !NEW_VGIC
45	default y
46	---help---
47
48	  Driver for the ARM Generic Interrupt Controller v3.
49	  If unsure, say Y
50
51config HAS_ITS
52        bool "GICv3 ITS MSI controller support" if EXPERT
53        depends on GICV3 && !NEW_VGIC
54
55config HVM
56        def_bool y
57
58config NEW_VGIC
59	bool
60	prompt "Use new VGIC implementation"
61	select NEEDS_LIST_SORT
62	---help---
63
64	This is an alternative implementation of the ARM GIC interrupt
65	controller emulation, based on the Linux/KVM VGIC. It has a better
66	design and fixes many shortcomings of the existing GIC emulation in
67	Xen. It will eventually replace the existing/old VGIC.
68	However at the moment it lacks support for Dom0 using the ITS for
69	using MSIs.
70	Say Y if you want to help testing this new code or if you experience
71	problems with the standard emulation.
72	At the moment this implementation is not security supported.
73
74config SBSA_VUART_CONSOLE
75	bool "Emulated SBSA UART console support"
76	default y
77	---help---
78	  Allows a guest to use SBSA Generic UART as a console. The
79	  SBSA Generic UART implements a subset of ARM PL011 UART.
80
81config ARM_SSBD
82	bool "Speculative Store Bypass Disable" if EXPERT
83	depends on HAS_ALTERNATIVE
84	default y
85	help
86	  This enables mitigation of bypassing of previous stores by speculative
87	  loads.
88
89	  If unsure, say Y.
90
91config HARDEN_BRANCH_PREDICTOR
92	bool "Harden the branch predictor against aliasing attacks" if EXPERT
93	default y
94	help
95	  Speculation attacks against some high-performance processors rely on
96	  being able to manipulate the branch predictor for a victim context by
97	  executing aliasing branches in the attacker context.  Such attacks
98	  can be partially mitigated against by clearing internal branch
99	  predictor state and limiting the prediction logic in some situations.
100
101	  This config option will take CPU-specific actions to harden the
102	  branch predictor against aliasing attacks and may rely on specific
103	  instruction sequences or control bits being set by the system
104	  firmware.
105
106	  If unsure, say Y.
107
108config TEE
109	bool "Enable TEE mediators support" if EXPERT
110	default n
111	help
112	  This option enables generic TEE mediators support. It allows guests
113	  to access real TEE via one of TEE mediators implemented in XEN.
114
115source "arch/arm/tee/Kconfig"
116
117endmenu
118
119menu "ARM errata workaround via the alternative framework"
120	depends on HAS_ALTERNATIVE
121
122config ARM64_ERRATUM_827319
123	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
124	default y
125	depends on ARM_64
126	help
127	  This option adds an alternative code sequence to work around ARM
128	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
129	  master interface and an L2 cache.
130
131	  Under certain conditions this erratum can cause a clean line eviction
132	  to occur at the same time as another transaction to the same address
133	  on the AMBA 5 CHI interface, which can cause data corruption if the
134	  interconnect reorders the two transactions.
135
136	  The workaround promotes data cache clean instructions to
137	  data cache clean-and-invalidate.
138	  Please note that this does not necessarily enable the workaround,
139	  as it depends on the alternative framework, which will only patch
140	  the kernel if an affected CPU is detected.
141
142	  If unsure, say Y.
143
144config ARM64_ERRATUM_824069
145	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
146	default y
147	depends on ARM_64
148	help
149	  This option adds an alternative code sequence to work around ARM
150	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
151	  to a coherent interconnect.
152
153	  If a Cortex-A53 processor is executing a store or prefetch for
154	  write instruction at the same time as a processor in another
155	  cluster is executing a cache maintenance operation to the same
156	  address, then this erratum might cause a clean cache line to be
157	  incorrectly marked as dirty.
158
159	  The workaround promotes data cache clean instructions to
160	  data cache clean-and-invalidate.
161	  Please note that this option does not necessarily enable the
162	  workaround, as it depends on the alternative framework, which will
163	  only patch the kernel if an affected CPU is detected.
164
165	  If unsure, say Y.
166
167config ARM64_ERRATUM_819472
168	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
169	default y
170	depends on ARM_64
171	help
172	  This option adds an alternative code sequence to work around ARM
173	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
174	  present when it is connected to a coherent interconnect.
175
176	  If the processor is executing a load and store exclusive sequence at
177	  the same time as a processor in another cluster is executing a cache
178	  maintenance operation to the same address, then this erratum might
179	  cause data corruption.
180
181	  The workaround promotes data cache clean instructions to
182	  data cache clean-and-invalidate.
183	  Please note that this does not necessarily enable the workaround,
184	  as it depends on the alternative framework, which will only patch
185	  the kernel if an affected CPU is detected.
186
187	  If unsure, say Y.
188
189config ARM64_ERRATUM_832075
190	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
191	default y
192	depends on ARM_64
193	help
194	  This option adds an alternative code sequence to work around ARM
195	  erratum 832075 on Cortex-A57 parts up to r1p2.
196
197	  Affected Cortex-A57 parts might deadlock when exclusive load/store
198	  instructions to Write-Back memory are mixed with Device loads.
199
200	  The workaround is to promote device loads to use Load-Acquire
201	  semantics.
202	  Please note that this does not necessarily enable the workaround,
203	  as it depends on the alternative framework, which will only patch
204	  the kernel if an affected CPU is detected.
205
206	  If unsure, say Y.
207
208config ARM64_ERRATUM_834220
209	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
210	default y
211	depends on ARM_64
212	help
213	  This option adds an alternative code sequence to work around ARM
214	  erratum 834220 on Cortex-A57 parts up to r1p2.
215
216	  Affected Cortex-A57 parts might report a Stage 2 translation
217	  fault as the result of a Stage 1 fault for load crossing a
218	  page boundary when there is a permission or device memory
219	  alignment fault at Stage 1 and a translation fault at Stage 2.
220
221	  The workaround is to verify that the Stage 1 translation
222	  doesn't generate a fault before handling the Stage 2 fault.
223	  Please note that this does not necessarily enable the workaround,
224	  as it depends on the alternative framework, which will only patch
225	  the kernel if an affected CPU is detected.
226
227	  If unsure, say Y.
228
229endmenu
230
231config ARM64_HARDEN_BRANCH_PREDICTOR
232    def_bool y if ARM_64 && HARDEN_BRANCH_PREDICTOR
233
234config ARM32_HARDEN_BRANCH_PREDICTOR
235    def_bool y if ARM_32 && HARDEN_BRANCH_PREDICTOR
236
237source "arch/arm/platforms/Kconfig"
238
239source "common/Kconfig"
240
241source "drivers/Kconfig"
242