1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2016 Keymile AG 4 * Rainer Boschung <rainer.boschung@keymile.com> 5 * 6 */ 7 8 #ifndef __KMCENT2_H 9 #define __KMCENT2_H 10 11 #define CONFIG_HOSTNAME "kmcent2" 12 #define KM_BOARD_NAME CONFIG_HOSTNAME 13 14 /* 15 * The Linux fsl_fman driver needs to be able to process frames with more 16 * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot 17 * parameters 18 */ 19 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558" 20 21 #include "km/keymile-common.h" 22 23 /* Application IFC chip selects */ 24 #define SYS_LAWAPP_BASE 0xc0000000 25 #define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE) 26 27 /* Application IFC CS4 MRAM */ 28 #define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE 29 #define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS 30 #define SYS_MRAM_CSPR_EXT (0x0f) 31 #define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \ 32 CSPR_PORT_SIZE_8 | /* 8 bit */ \ 33 CSPR_MSEL_GPCM | /* msel = gpcm */ \ 34 CSPR_V /* bank is valid */) 35 #define SYS_MRAM_AMASK IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */ 36 #define SYS_MRAM_CSOR CSOR_GPCM_TRHZ_40 37 /* MRAM Timing parameters for IFC CS4 */ 38 #define SYS_MRAM_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ 39 FTIM0_GPCM_TEADC(0x8) | \ 40 FTIM0_GPCM_TEAHC(0x2)) 41 #define SYS_MRAM_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ 42 FTIM1_GPCM_TRAD(0xe)) 43 #define SYS_MRAM_FTIM2 (FTIM2_GPCM_TCS(0x2) | \ 44 FTIM2_GPCM_TCH(0x2) | \ 45 FTIM2_GPCM_TWP(0x8)) 46 #define SYS_MRAM_FTIM3 0x04000000 47 #define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT 48 #define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR 49 #define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK 50 #define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR 51 #define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 52 #define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 53 #define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 54 #define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3 55 56 /* Application IFC CS6: BFTIC */ 57 #define SYS_BFTIC_BASE 0xd0000000 58 #define SYS_BFTIC_BASE_PHYS (0xf00000000ull | SYS_BFTIC_BASE) 59 #define SYS_BFTIC_CSPR_EXT (0x0f) 60 #define SYS_BFTIC_CSPR (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \ 61 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ 62 CSPR_MSEL_GPCM | /* MSEL = GPCM */\ 63 CSPR_V) /* valid */ 64 #define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024) /* 64kB */ 65 #define SYS_BFTIC_CSOR CSOR_GPCM_TRHZ_40 66 /* BFTIC Timing parameters for IFC CS6 */ 67 #define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ 68 FTIM0_GPCM_TEADC(0x8) | \ 69 FTIM0_GPCM_TEAHC(0x2)) 70 #define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ 71 FTIM1_GPCM_TRAD(0x12)) 72 #define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ 73 FTIM2_GPCM_TCH(0x1) | \ 74 FTIM2_GPCM_TWP(0x12)) 75 #define SYS_BFTIC_FTIM3 0x04000000 76 #define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT 77 #define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR 78 #define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK 79 #define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR 80 #define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 81 #define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 82 #define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 83 #define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3 84 85 /* Application IFC CS7 PAXE */ 86 #define CONFIG_SYS_PAXE_BASE 0xd8000000 87 #define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE) 88 #define SYS_PAXE_CSPR_EXT (0x0f) 89 #define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \ 90 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ 91 CSPR_MSEL_GPCM | /* MSEL = GPCM */\ 92 CSPR_V) /* valid */ 93 #define SYS_PAXE_AMASK IFC_AMASK(64 * 1024) /* 64kB */ 94 #define SYS_PAXE_CSOR CSOR_GPCM_TRHZ_40 95 /* PAXE Timing parameters for IFC CS7 */ 96 #define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ 97 FTIM0_GPCM_TEADC(0x8) | \ 98 FTIM0_GPCM_TEAHC(0x2)) 99 #define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ 100 FTIM1_GPCM_TRAD(0x12)) 101 #define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ 102 FTIM2_GPCM_TCH(0x1) | \ 103 FTIM2_GPCM_TWP(0x12)) 104 #define SYS_PAXE_FTIM3 0x04000000 105 #define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT 106 #define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR 107 #define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK 108 #define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR 109 #define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 110 #define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 111 #define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 112 #define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3 113 114 /* PRST */ 115 #define KM_BFTIC4_RST 0 116 #define KM_DPAXE_RST 1 117 #define KM_FEMT_RST 3 118 #define KM_FOAM_RST 4 119 #define KM_EFE_RST 5 120 #define KM_ES_PHY_RST 6 121 #define KM_XES_PHY_RST 7 122 #define KM_ZL30158_RST 8 123 #define KM_ZL30364_RST 9 124 #define KM_BOBCAT_RST 10 125 #define KM_ETHSW_DDR_RST 12 126 #define KM_CFE_RST 13 127 #define KM_PEXSW_RST 14 128 #define KM_PEXSW_NT_RST 15 129 130 /* QRIO GPIOs used for deblocking */ 131 #define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A 132 #define KM_I2C_DEBLOCK_SCL 20 133 #define KM_I2C_DEBLOCK_SDA 21 134 135 /* High Level Configuration Options */ 136 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 137 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 138 139 #define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc 140 141 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 142 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 143 #define CONFIG_PCIE1 /* PCIE controller 1 */ 144 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 145 146 /* Environment in parallel NOR-Flash */ 147 #define CONFIG_ENV_TOTAL_SIZE 0x040000 148 #define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/ 149 150 #define CONFIG_SYS_CLK_FREQ 66666666 151 152 /* 153 * These can be toggled for performance analysis, otherwise use default. 154 */ 155 #define CONFIG_SYS_CACHE_STASHING 156 #define CONFIG_BACKSIDE_L2_CACHE 157 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 158 #define CONFIG_BTB /* toggle branch predition */ 159 160 #define CONFIG_ENABLE_36BIT_PHYS 161 162 /* POST memory regions test */ 163 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS 164 165 /* 166 * Config the L3 Cache as L3 SRAM 167 */ 168 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 169 #define CONFIG_SYS_L3_SIZE 256 << 10 170 171 #define CONFIG_SYS_DCSRBAR 0xf0000000 172 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 173 174 /* 175 * DDR Setup 176 */ 177 #define CONFIG_VERY_BIG_RAM 178 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 179 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 180 #define CONFIG_DDR_CLK_FREQ 66666666 181 182 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 183 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 184 185 #define CONFIG_DDR_SPD 186 187 #define CONFIG_SYS_SPD_BUS_NUM 0 188 #define SPD_EEPROM_ADDRESS 0x54 189 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 190 191 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 192 #define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR 193 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 194 195 /****************************************************************************** 196 * (PRAM usage) 197 * ... ------------------------------------------------------- 198 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 199 * ... |<------------------- pram -------------------------->| 200 * ... ------------------------------------------------------- 201 * @END_OF_RAM: 202 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 203 * @CONFIG_KM_PHRAM: address for /var 204 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 205 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 206 */ 207 208 /* size of rootfs in RAM */ 209 #define CONFIG_KM_ROOTFSSIZE 0x0 210 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable 211 * is not valid yet, which is the case for when u-boot copies itself to RAM 212 */ 213 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10) 214 215 /* 216 * IFC Definitions 217 */ 218 /* NOR flash on IFC CS0 */ 219 #define CONFIG_SYS_FLASH_BASE 0xe8000000 220 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ 221 CONFIG_SYS_FLASH_BASE) 222 223 #define CONFIG_SYS_NOR_CSPR_EXT (0x0f) 224 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 225 CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\ 226 0x00000010 | /* drive TE high */\ 227 CSPR_MSEL_NOR | /* MSEL = NOR */\ 228 CSPR_V) /* valid */ 229 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */ 230 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\ 231 CSOR_NOR_TRHZ_20 | \ 232 CSOR_NOR_BCTLD) 233 234 /* NOR Flash Timing Params */ 235 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 236 FTIM0_NOR_TEADC(0x7) | \ 237 FTIM0_NOR_TEAHC(0x1)) 238 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 239 FTIM1_NOR_TRAD_NOR(0x21) | \ 240 FTIM1_NOR_TSEQRAD_NOR(0x21)) 241 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \ 242 FTIM2_NOR_TCS(0x1) | \ 243 FTIM2_NOR_TWP(0xb) | \ 244 FTIM2_NOR_TWPH(0x6)) 245 #define CONFIG_SYS_NOR_FTIM3 0x0 246 247 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 248 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 249 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 250 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 251 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 252 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 253 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 254 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 255 256 /* More NOR Flash params */ 257 #define CONFIG_SYS_FLASH_QUIET_TEST 258 259 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 260 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 261 262 #define CONFIG_SYS_FLASH_EMPTY_INFO 263 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 264 265 /* NAND Flash on IFC CS1*/ 266 #define CONFIG_NAND_FSL_IFC 267 #define CONFIG_SYS_NAND_BASE 0xfa000000 268 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 269 270 #define CONFIG_SYS_NAND_CSPR_EXT (0x0f) 271 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ 272 CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\ 273 0x00000010 | /* drive TE high */\ 274 CSPR_MSEL_NAND | /* MSEL = NAND */\ 275 CSPR_V) /* valid */ 276 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */ 277 278 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \ 279 CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \ 280 CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \ 281 CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \ 282 CSOR_NAND_PGS_2K | /* Page size = 2K */ \ 283 CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \ 284 CSOR_NAND_PB(64) | /* 64 Pages/Block */ \ 285 CSOR_NAND_TRHZ_40 | /**/ \ 286 CSOR_NAND_BCTLD) /**/ 287 288 #define CONFIG_SYS_NAND_ONFI_DETECTION 289 290 /* ONFI NAND Flash mode0 Timing Params */ 291 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ 292 FTIM0_NAND_TWP(0x8) | \ 293 FTIM0_NAND_TWCHT(0x3) | \ 294 FTIM0_NAND_TWH(0x5)) 295 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ 296 FTIM1_NAND_TWBE(0x1e) | \ 297 FTIM1_NAND_TRR(0x6) | \ 298 FTIM1_NAND_TRP(0x8)) 299 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ 300 FTIM2_NAND_TREH(0x5) | \ 301 FTIM2_NAND_TWHRE(0x3c)) 302 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) 303 304 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 305 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 306 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 307 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 308 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 309 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 310 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 311 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 312 313 /* More NAND Flash Params */ 314 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 315 #define CONFIG_SYS_MAX_NAND_DEVICE 1 316 317 /* QRIO on IFC CS2 */ 318 #define CONFIG_SYS_QRIO_BASE 0xfb000000 319 #define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE) 320 #define SYS_QRIO_CSPR_EXT (0x0f) 321 #define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ 322 CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ 323 0x00000010 | /* drive TE high */\ 324 CSPR_MSEL_GPCM | /* MSEL = GPCM */\ 325 CSPR_V) /* valid */ 326 #define SYS_QRIO_AMASK IFC_AMASK(64 * 1024) /* 64kB */ 327 #define SYS_QRIO_CSOR (CSOR_GPCM_TRHZ_20 |\ 328 CSOR_GPCM_BCTLD) 329 /* QRIO Timing parameters for IFC CS2 */ 330 #define SYS_QRIO_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ 331 FTIM0_GPCM_TEADC(0x8) | \ 332 FTIM0_GPCM_TEAHC(0x2)) 333 #define SYS_QRIO_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ 334 FTIM1_GPCM_TRAD(0x6)) 335 #define SYS_QRIO_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ 336 FTIM2_GPCM_TCH(0x1) | \ 337 FTIM2_GPCM_TWP(0x7)) 338 #define SYS_QRIO_FTIM3 0x04000000 339 #define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT 340 #define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR 341 #define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK 342 #define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR 343 #define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 344 #define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 345 #define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 346 #define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 347 348 #define CONFIG_MISC_INIT_F 349 #define CONFIG_HWCONFIG 350 351 /* define to use L1 as initial stack */ 352 #define CONFIG_SYS_INIT_RAM_LOCK 353 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 354 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 355 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 356 /* The assembler doesn't like typecast */ 357 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 358 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 359 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 360 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 361 362 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 363 GENERATED_GBL_DATA_SIZE) 364 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 365 366 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 367 #define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */ 368 369 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 370 371 /* 372 * Serial Port - controlled on board with jumper J8 373 * open - index 2 374 * shorted - index 1 375 * Retain non-DM serial port for debug purposes. 376 */ 377 #if !defined(CONFIG_DM_SERIAL) 378 #define CONFIG_CONS_INDEX 1 379 #define CONFIG_SYS_NS16550_SERIAL 380 #define CONFIG_SYS_NS16550_REG_SIZE 1 381 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) 382 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) 383 #endif 384 385 #ifndef __ASSEMBLY__ 386 void set_sda(int state); 387 void set_scl(int state); 388 int get_sda(void); 389 int get_scl(void); 390 #endif 391 392 /* 393 * General PCI 394 * Memory space is mapped 1-1, but I/O space must start from 0. 395 */ 396 /* controller 1 */ 397 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 398 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 399 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 400 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 401 402 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 403 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 404 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 405 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 406 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 407 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 408 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 409 CONFIG_SYS_BMAN_CENA_SIZE) 410 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 411 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 412 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 413 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 414 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 415 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 416 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 417 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 418 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 419 CONFIG_SYS_QMAN_CENA_SIZE) 420 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 421 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 422 423 #define CONFIG_SYS_DPAA_FMAN 424 #define CONFIG_SYS_DPAA_PME 425 426 /* Default address of microcode for the Linux Fman driver */ 427 #define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000 428 #define CONFIG_SYS_QE_FW_ADDR 0xE8040000 429 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 430 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 431 432 /* Qman / Bman */ 433 /* RGMII (FM1@DTESC5) is local managemant interface */ 434 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 435 #define CONFIG_ETHPRIME "fm1-mac5" 436 437 /* 438 * Hardware Watchdog 439 */ 440 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */ 441 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ 442 443 /* 444 * For booting Linux, the board info and command line data 445 * have to be in the first 64 MB of memory, since this is 446 * the maximum mapped by the Linux kernel during initialization. 447 */ 448 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 449 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 450 451 /* 452 * Environment Configuration 453 */ 454 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 455 #define CONFIG_KM_DEF_ENV 456 #endif 457 458 #define __USB_PHY_TYPE utmi 459 460 #define CONFIG_KM_DEF_ENV_CPU \ 461 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 462 "cramfsloadfdt=" \ 463 "cramfsload ${fdt_addr_r} " \ 464 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 465 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ 466 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 467 " +${filesize} && " \ 468 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ 469 " +${filesize} && " \ 470 "cp.b ${load_addr_r} " \ 471 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ 472 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ 473 " +${filesize}\0" \ 474 "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ 475 " +${filesize} && " \ 476 "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ 477 " +${filesize} && " \ 478 "cp.b ${load_addr_r} " \ 479 __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ 480 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ 481 " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \ 482 "set_fdthigh=true\0" \ 483 "checkfdt=true\0" \ 484 "fpgacfg=true\0" \ 485 "" 486 487 #define CONFIG_HW_ENV_SETTINGS \ 488 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 489 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 490 "usb_dr_mode=host\0" 491 492 #define CONFIG_KM_NEW_ENV \ 493 "newenv=protect off " __stringify(ENV_DEL_ADDR) \ 494 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ 495 "erase " __stringify(ENV_DEL_ADDR) \ 496 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ 497 "protect on " __stringify(ENV_DEL_ADDR) \ 498 " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" 499 500 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 501 #ifndef CONFIG_KM_DEF_ARCH 502 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 503 #endif 504 505 #define CONFIG_EXTRA_ENV_SETTINGS \ 506 CONFIG_KM_DEF_ENV \ 507 CONFIG_KM_DEF_ARCH \ 508 CONFIG_KM_NEW_ENV \ 509 CONFIG_HW_ENV_SETTINGS \ 510 "EEprom_ivm=pca9547:70:9\0" \ 511 "" 512 513 #endif /* __KMCENT2_H */ 514