1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7config CMD_ERRATA 8 bool "Enable the 'errata' command" 9 depends on MPC85xx 10 default y 11 help 12 This enables the 'errata' command which displays a list of errata 13 work-arounds which are enabled for the current board. 14 15choice 16 prompt "Target select" 17 optional 18 19config TARGET_SBC8548 20 bool "Support sbc8548" 21 select ARCH_MPC8548 22 23config TARGET_SOCRATES 24 bool "Support socrates" 25 select ARCH_MPC8544 26 27config TARGET_P3041DS 28 bool "Support P3041DS" 29 select PHYS_64BIT 30 select ARCH_P3041 31 select BOARD_LATE_INIT if CHAIN_OF_TRUST 32 imply CMD_SATA 33 imply PANIC_HANG 34 35config TARGET_P4080DS 36 bool "Support P4080DS" 37 select PHYS_64BIT 38 select ARCH_P4080 39 select BOARD_LATE_INIT if CHAIN_OF_TRUST 40 imply CMD_SATA 41 imply PANIC_HANG 42 43config TARGET_P5040DS 44 bool "Support P5040DS" 45 select PHYS_64BIT 46 select ARCH_P5040 47 select BOARD_LATE_INIT if CHAIN_OF_TRUST 48 imply CMD_SATA 49 imply PANIC_HANG 50 51config TARGET_MPC8541CDS 52 bool "Support MPC8541CDS" 53 select ARCH_MPC8541 54 select FSL_VIA 55 56config TARGET_MPC8548CDS 57 bool "Support MPC8548CDS" 58 select ARCH_MPC8548 59 select FSL_VIA 60 61config TARGET_MPC8555CDS 62 bool "Support MPC8555CDS" 63 select ARCH_MPC8555 64 select FSL_VIA 65 66config TARGET_MPC8568MDS 67 bool "Support MPC8568MDS" 68 select ARCH_MPC8568 69 70config TARGET_P1010RDB_PA 71 bool "Support P1010RDB_PA" 72 select ARCH_P1010 73 select BOARD_LATE_INIT if CHAIN_OF_TRUST 74 select SUPPORT_SPL 75 select SUPPORT_TPL 76 imply CMD_EEPROM 77 imply CMD_SATA 78 imply PANIC_HANG 79 80config TARGET_P1010RDB_PB 81 bool "Support P1010RDB_PB" 82 select ARCH_P1010 83 select BOARD_LATE_INIT if CHAIN_OF_TRUST 84 select SUPPORT_SPL 85 select SUPPORT_TPL 86 imply CMD_EEPROM 87 imply CMD_SATA 88 imply PANIC_HANG 89 90config TARGET_P1020RDB_PC 91 bool "Support P1020RDB-PC" 92 select SUPPORT_SPL 93 select SUPPORT_TPL 94 select ARCH_P1020 95 imply CMD_EEPROM 96 imply CMD_SATA 97 imply PANIC_HANG 98 99config TARGET_P1020RDB_PD 100 bool "Support P1020RDB-PD" 101 select SUPPORT_SPL 102 select SUPPORT_TPL 103 select ARCH_P1020 104 imply CMD_EEPROM 105 imply CMD_SATA 106 imply PANIC_HANG 107 108config TARGET_P2020RDB 109 bool "Support P2020RDB-PC" 110 select SUPPORT_SPL 111 select SUPPORT_TPL 112 select ARCH_P2020 113 imply CMD_EEPROM 114 imply CMD_SATA 115 imply SATA_SIL 116 117config TARGET_P2041RDB 118 bool "Support P2041RDB" 119 select ARCH_P2041 120 select BOARD_LATE_INIT if CHAIN_OF_TRUST 121 select PHYS_64BIT 122 imply CMD_SATA 123 imply FSL_SATA 124 125config TARGET_QEMU_PPCE500 126 bool "Support qemu-ppce500" 127 select ARCH_QEMU_E500 128 select PHYS_64BIT 129 130config TARGET_T1023RDB 131 bool "Support T1023RDB" 132 select ARCH_T1023 133 select BOARD_LATE_INIT if CHAIN_OF_TRUST 134 select SUPPORT_SPL 135 select PHYS_64BIT 136 select FSL_DDR_INTERACTIVE 137 imply CMD_EEPROM 138 imply PANIC_HANG 139 140config TARGET_T1024RDB 141 bool "Support T1024RDB" 142 select ARCH_T1024 143 select BOARD_LATE_INIT if CHAIN_OF_TRUST 144 select SUPPORT_SPL 145 select PHYS_64BIT 146 select FSL_DDR_INTERACTIVE 147 imply CMD_EEPROM 148 imply PANIC_HANG 149 150config TARGET_T1040RDB 151 bool "Support T1040RDB" 152 select ARCH_T1040 153 select BOARD_LATE_INIT if CHAIN_OF_TRUST 154 select SUPPORT_SPL 155 select PHYS_64BIT 156 imply CMD_SATA 157 imply PANIC_HANG 158 159config TARGET_T1040D4RDB 160 bool "Support T1040D4RDB" 161 select ARCH_T1040 162 select BOARD_LATE_INIT if CHAIN_OF_TRUST 163 select SUPPORT_SPL 164 select PHYS_64BIT 165 imply CMD_SATA 166 imply PANIC_HANG 167 168config TARGET_T1042RDB 169 bool "Support T1042RDB" 170 select ARCH_T1042 171 select BOARD_LATE_INIT if CHAIN_OF_TRUST 172 select SUPPORT_SPL 173 select PHYS_64BIT 174 imply CMD_SATA 175 176config TARGET_T1042D4RDB 177 bool "Support T1042D4RDB" 178 select ARCH_T1042 179 select BOARD_LATE_INIT if CHAIN_OF_TRUST 180 select SUPPORT_SPL 181 select PHYS_64BIT 182 imply CMD_SATA 183 imply PANIC_HANG 184 185config TARGET_T1042RDB_PI 186 bool "Support T1042RDB_PI" 187 select ARCH_T1042 188 select BOARD_LATE_INIT if CHAIN_OF_TRUST 189 select SUPPORT_SPL 190 select PHYS_64BIT 191 imply CMD_SATA 192 imply PANIC_HANG 193 194config TARGET_T2080QDS 195 bool "Support T2080QDS" 196 select ARCH_T2080 197 select BOARD_LATE_INIT if CHAIN_OF_TRUST 198 select SUPPORT_SPL 199 select PHYS_64BIT 200 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 201 select FSL_DDR_INTERACTIVE 202 imply CMD_SATA 203 204config TARGET_T2080RDB 205 bool "Support T2080RDB" 206 select ARCH_T2080 207 select BOARD_LATE_INIT if CHAIN_OF_TRUST 208 select SUPPORT_SPL 209 select PHYS_64BIT 210 imply CMD_SATA 211 imply PANIC_HANG 212 213config TARGET_T2081QDS 214 bool "Support T2081QDS" 215 select ARCH_T2081 216 select SUPPORT_SPL 217 select PHYS_64BIT 218 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 219 select FSL_DDR_INTERACTIVE 220 221config TARGET_T4160RDB 222 bool "Support T4160RDB" 223 select ARCH_T4160 224 select SUPPORT_SPL 225 select PHYS_64BIT 226 imply PANIC_HANG 227 228config TARGET_T4240RDB 229 bool "Support T4240RDB" 230 select ARCH_T4240 231 select SUPPORT_SPL 232 select PHYS_64BIT 233 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 234 imply CMD_SATA 235 imply PANIC_HANG 236 237config TARGET_CONTROLCENTERD 238 bool "Support controlcenterd" 239 select ARCH_P1022 240 241config TARGET_KMP204X 242 bool "Support kmp204x" 243 select VENDOR_KM 244 245config TARGET_KMCENT2 246 bool "Support kmcent2" 247 select VENDOR_KM 248 249config TARGET_XPEDITE520X 250 bool "Support xpedite520x" 251 select ARCH_MPC8548 252 253config TARGET_XPEDITE537X 254 bool "Support xpedite537x" 255 select ARCH_MPC8572 256# Use DDR3 controller with DDR2 DIMMs on this board 257 select SYS_FSL_DDRC_GEN3 258 259config TARGET_XPEDITE550X 260 bool "Support xpedite550x" 261 select ARCH_P2020 262 263config TARGET_UCP1020 264 bool "Support uCP1020" 265 select ARCH_P1020 266 imply CMD_SATA 267 imply PANIC_HANG 268 269config TARGET_CYRUS_P5020 270 bool "Support Varisys Cyrus P5020" 271 select ARCH_P5020 272 select PHYS_64BIT 273 imply PANIC_HANG 274 275config TARGET_CYRUS_P5040 276 bool "Support Varisys Cyrus P5040" 277 select ARCH_P5040 278 select PHYS_64BIT 279 imply PANIC_HANG 280 281endchoice 282 283config ARCH_B4420 284 bool 285 select E500MC 286 select E6500 287 select FSL_LAW 288 select SYS_FSL_DDR_VER_47 289 select SYS_FSL_ERRATUM_A004477 290 select SYS_FSL_ERRATUM_A005871 291 select SYS_FSL_ERRATUM_A006379 292 select SYS_FSL_ERRATUM_A006384 293 select SYS_FSL_ERRATUM_A006475 294 select SYS_FSL_ERRATUM_A006593 295 select SYS_FSL_ERRATUM_A007075 296 select SYS_FSL_ERRATUM_A007186 297 select SYS_FSL_ERRATUM_A007212 298 select SYS_FSL_ERRATUM_A009942 299 select SYS_FSL_HAS_DDR3 300 select SYS_FSL_HAS_SEC 301 select SYS_FSL_QORIQ_CHASSIS2 302 select SYS_FSL_SEC_BE 303 select SYS_FSL_SEC_COMPAT_4 304 select SYS_PPC64 305 select FSL_IFC 306 imply CMD_EEPROM 307 imply CMD_NAND 308 imply CMD_REGINFO 309 310config ARCH_B4860 311 bool 312 select E500MC 313 select E6500 314 select FSL_LAW 315 select SYS_FSL_DDR_VER_47 316 select SYS_FSL_ERRATUM_A004477 317 select SYS_FSL_ERRATUM_A005871 318 select SYS_FSL_ERRATUM_A006379 319 select SYS_FSL_ERRATUM_A006384 320 select SYS_FSL_ERRATUM_A006475 321 select SYS_FSL_ERRATUM_A006593 322 select SYS_FSL_ERRATUM_A007075 323 select SYS_FSL_ERRATUM_A007186 324 select SYS_FSL_ERRATUM_A007212 325 select SYS_FSL_ERRATUM_A007907 326 select SYS_FSL_ERRATUM_A009942 327 select SYS_FSL_HAS_DDR3 328 select SYS_FSL_HAS_SEC 329 select SYS_FSL_QORIQ_CHASSIS2 330 select SYS_FSL_SEC_BE 331 select SYS_FSL_SEC_COMPAT_4 332 select SYS_PPC64 333 select FSL_IFC 334 imply CMD_EEPROM 335 imply CMD_NAND 336 imply CMD_REGINFO 337 338config ARCH_BSC9131 339 bool 340 select FSL_LAW 341 select SYS_FSL_DDR_VER_44 342 select SYS_FSL_ERRATUM_A004477 343 select SYS_FSL_ERRATUM_A005125 344 select SYS_FSL_ERRATUM_ESDHC111 345 select SYS_FSL_HAS_DDR3 346 select SYS_FSL_HAS_SEC 347 select SYS_FSL_SEC_BE 348 select SYS_FSL_SEC_COMPAT_4 349 select FSL_IFC 350 imply CMD_EEPROM 351 imply CMD_NAND 352 imply CMD_REGINFO 353 354config ARCH_BSC9132 355 bool 356 select FSL_LAW 357 select SYS_FSL_DDR_VER_46 358 select SYS_FSL_ERRATUM_A004477 359 select SYS_FSL_ERRATUM_A005125 360 select SYS_FSL_ERRATUM_A005434 361 select SYS_FSL_ERRATUM_ESDHC111 362 select SYS_FSL_ERRATUM_I2C_A004447 363 select SYS_FSL_ERRATUM_IFC_A002769 364 select FSL_PCIE_RESET 365 select SYS_FSL_HAS_DDR3 366 select SYS_FSL_HAS_SEC 367 select SYS_FSL_SEC_BE 368 select SYS_FSL_SEC_COMPAT_4 369 select SYS_PPC_E500_USE_DEBUG_TLB 370 select FSL_IFC 371 imply CMD_EEPROM 372 imply CMD_MTDPARTS 373 imply CMD_NAND 374 imply CMD_PCI 375 imply CMD_REGINFO 376 377config ARCH_C29X 378 bool 379 select FSL_LAW 380 select SYS_FSL_DDR_VER_46 381 select SYS_FSL_ERRATUM_A005125 382 select SYS_FSL_ERRATUM_ESDHC111 383 select FSL_PCIE_RESET 384 select SYS_FSL_HAS_DDR3 385 select SYS_FSL_HAS_SEC 386 select SYS_FSL_SEC_BE 387 select SYS_FSL_SEC_COMPAT_6 388 select SYS_PPC_E500_USE_DEBUG_TLB 389 select FSL_IFC 390 imply CMD_NAND 391 imply CMD_PCI 392 imply CMD_REGINFO 393 394config ARCH_MPC8536 395 bool 396 select FSL_LAW 397 select SYS_FSL_ERRATUM_A004508 398 select SYS_FSL_ERRATUM_A005125 399 select FSL_PCIE_RESET 400 select SYS_FSL_HAS_DDR2 401 select SYS_FSL_HAS_DDR3 402 select SYS_FSL_HAS_SEC 403 select SYS_FSL_SEC_BE 404 select SYS_FSL_SEC_COMPAT_2 405 select SYS_PPC_E500_USE_DEBUG_TLB 406 select FSL_ELBC 407 imply CMD_NAND 408 imply CMD_SATA 409 imply CMD_REGINFO 410 411config ARCH_MPC8540 412 bool 413 select FSL_LAW 414 select SYS_FSL_HAS_DDR1 415 416config ARCH_MPC8541 417 bool 418 select FSL_LAW 419 select SYS_FSL_HAS_DDR1 420 select SYS_FSL_HAS_SEC 421 select SYS_FSL_SEC_BE 422 select SYS_FSL_SEC_COMPAT_2 423 424config ARCH_MPC8544 425 bool 426 select FSL_LAW 427 select SYS_FSL_ERRATUM_A005125 428 select FSL_PCIE_RESET 429 select SYS_FSL_HAS_DDR2 430 select SYS_FSL_HAS_SEC 431 select SYS_FSL_SEC_BE 432 select SYS_FSL_SEC_COMPAT_2 433 select SYS_PPC_E500_USE_DEBUG_TLB 434 select FSL_ELBC 435 436config ARCH_MPC8548 437 bool 438 select FSL_LAW 439 select SYS_FSL_ERRATUM_A005125 440 select SYS_FSL_ERRATUM_NMG_DDR120 441 select SYS_FSL_ERRATUM_NMG_LBC103 442 select SYS_FSL_ERRATUM_NMG_ETSEC129 443 select SYS_FSL_ERRATUM_I2C_A004447 444 select FSL_PCIE_RESET 445 select SYS_FSL_HAS_DDR2 446 select SYS_FSL_HAS_DDR1 447 select SYS_FSL_HAS_SEC 448 select SYS_FSL_SEC_BE 449 select SYS_FSL_SEC_COMPAT_2 450 select SYS_PPC_E500_USE_DEBUG_TLB 451 imply CMD_REGINFO 452 453config ARCH_MPC8555 454 bool 455 select FSL_LAW 456 select SYS_FSL_HAS_DDR1 457 select SYS_FSL_HAS_SEC 458 select SYS_FSL_SEC_BE 459 select SYS_FSL_SEC_COMPAT_2 460 461config ARCH_MPC8560 462 bool 463 select FSL_LAW 464 select SYS_FSL_HAS_DDR1 465 466config ARCH_MPC8568 467 bool 468 select FSL_LAW 469 select FSL_PCIE_RESET 470 select SYS_FSL_HAS_DDR2 471 select SYS_FSL_HAS_SEC 472 select SYS_FSL_SEC_BE 473 select SYS_FSL_SEC_COMPAT_2 474 475config ARCH_MPC8572 476 bool 477 select FSL_LAW 478 select SYS_FSL_ERRATUM_A004508 479 select SYS_FSL_ERRATUM_A005125 480 select SYS_FSL_ERRATUM_DDR_115 481 select SYS_FSL_ERRATUM_DDR111_DDR134 482 select FSL_PCIE_RESET 483 select SYS_FSL_HAS_DDR2 484 select SYS_FSL_HAS_DDR3 485 select SYS_FSL_HAS_SEC 486 select SYS_FSL_SEC_BE 487 select SYS_FSL_SEC_COMPAT_2 488 select SYS_PPC_E500_USE_DEBUG_TLB 489 select FSL_ELBC 490 imply CMD_NAND 491 492config ARCH_P1010 493 bool 494 select FSL_LAW 495 select SYS_FSL_ERRATUM_A004477 496 select SYS_FSL_ERRATUM_A004508 497 select SYS_FSL_ERRATUM_A005125 498 select SYS_FSL_ERRATUM_A005275 499 select SYS_FSL_ERRATUM_A006261 500 select SYS_FSL_ERRATUM_A007075 501 select SYS_FSL_ERRATUM_ESDHC111 502 select SYS_FSL_ERRATUM_I2C_A004447 503 select SYS_FSL_ERRATUM_IFC_A002769 504 select SYS_FSL_ERRATUM_P1010_A003549 505 select SYS_FSL_ERRATUM_SEC_A003571 506 select SYS_FSL_ERRATUM_IFC_A003399 507 select FSL_PCIE_RESET 508 select SYS_FSL_HAS_DDR3 509 select SYS_FSL_HAS_SEC 510 select SYS_FSL_SEC_BE 511 select SYS_FSL_SEC_COMPAT_4 512 select SYS_PPC_E500_USE_DEBUG_TLB 513 select FSL_IFC 514 imply CMD_EEPROM 515 imply CMD_MTDPARTS 516 imply CMD_NAND 517 imply CMD_SATA 518 imply CMD_PCI 519 imply CMD_REGINFO 520 imply FSL_SATA 521 522config ARCH_P1011 523 bool 524 select FSL_LAW 525 select SYS_FSL_ERRATUM_A004508 526 select SYS_FSL_ERRATUM_A005125 527 select SYS_FSL_ERRATUM_ELBC_A001 528 select SYS_FSL_ERRATUM_ESDHC111 529 select FSL_PCIE_DISABLE_ASPM 530 select SYS_FSL_HAS_DDR3 531 select SYS_FSL_HAS_SEC 532 select SYS_FSL_SEC_BE 533 select SYS_FSL_SEC_COMPAT_2 534 select SYS_PPC_E500_USE_DEBUG_TLB 535 select FSL_ELBC 536 537config ARCH_P1020 538 bool 539 select FSL_LAW 540 select SYS_FSL_ERRATUM_A004508 541 select SYS_FSL_ERRATUM_A005125 542 select SYS_FSL_ERRATUM_ELBC_A001 543 select SYS_FSL_ERRATUM_ESDHC111 544 select FSL_PCIE_DISABLE_ASPM 545 select FSL_PCIE_RESET 546 select SYS_FSL_HAS_DDR3 547 select SYS_FSL_HAS_SEC 548 select SYS_FSL_SEC_BE 549 select SYS_FSL_SEC_COMPAT_2 550 select SYS_PPC_E500_USE_DEBUG_TLB 551 select FSL_ELBC 552 imply CMD_NAND 553 imply CMD_SATA 554 imply CMD_PCI 555 imply CMD_REGINFO 556 imply SATA_SIL 557 558config ARCH_P1021 559 bool 560 select FSL_LAW 561 select SYS_FSL_ERRATUM_A004508 562 select SYS_FSL_ERRATUM_A005125 563 select SYS_FSL_ERRATUM_ELBC_A001 564 select SYS_FSL_ERRATUM_ESDHC111 565 select FSL_PCIE_DISABLE_ASPM 566 select FSL_PCIE_RESET 567 select SYS_FSL_HAS_DDR3 568 select SYS_FSL_HAS_SEC 569 select SYS_FSL_SEC_BE 570 select SYS_FSL_SEC_COMPAT_2 571 select SYS_PPC_E500_USE_DEBUG_TLB 572 select FSL_ELBC 573 imply CMD_REGINFO 574 imply CMD_NAND 575 imply CMD_SATA 576 imply CMD_REGINFO 577 imply SATA_SIL 578 579config ARCH_P1022 580 bool 581 select FSL_LAW 582 select SYS_FSL_ERRATUM_A004477 583 select SYS_FSL_ERRATUM_A004508 584 select SYS_FSL_ERRATUM_A005125 585 select SYS_FSL_ERRATUM_ELBC_A001 586 select SYS_FSL_ERRATUM_ESDHC111 587 select SYS_FSL_ERRATUM_SATA_A001 588 select FSL_PCIE_RESET 589 select SYS_FSL_HAS_DDR3 590 select SYS_FSL_HAS_SEC 591 select SYS_FSL_SEC_BE 592 select SYS_FSL_SEC_COMPAT_2 593 select SYS_PPC_E500_USE_DEBUG_TLB 594 select FSL_ELBC 595 596config ARCH_P1023 597 bool 598 select FSL_LAW 599 select SYS_FSL_ERRATUM_A004508 600 select SYS_FSL_ERRATUM_A005125 601 select SYS_FSL_ERRATUM_I2C_A004447 602 select FSL_PCIE_RESET 603 select SYS_FSL_HAS_DDR3 604 select SYS_FSL_HAS_SEC 605 select SYS_FSL_SEC_BE 606 select SYS_FSL_SEC_COMPAT_4 607 select FSL_ELBC 608 609config ARCH_P1024 610 bool 611 select FSL_LAW 612 select SYS_FSL_ERRATUM_A004508 613 select SYS_FSL_ERRATUM_A005125 614 select SYS_FSL_ERRATUM_ELBC_A001 615 select SYS_FSL_ERRATUM_ESDHC111 616 select FSL_PCIE_DISABLE_ASPM 617 select FSL_PCIE_RESET 618 select SYS_FSL_HAS_DDR3 619 select SYS_FSL_HAS_SEC 620 select SYS_FSL_SEC_BE 621 select SYS_FSL_SEC_COMPAT_2 622 select SYS_PPC_E500_USE_DEBUG_TLB 623 select FSL_ELBC 624 imply CMD_EEPROM 625 imply CMD_NAND 626 imply CMD_SATA 627 imply CMD_PCI 628 imply CMD_REGINFO 629 imply SATA_SIL 630 631config ARCH_P1025 632 bool 633 select FSL_LAW 634 select SYS_FSL_ERRATUM_A004508 635 select SYS_FSL_ERRATUM_A005125 636 select SYS_FSL_ERRATUM_ELBC_A001 637 select SYS_FSL_ERRATUM_ESDHC111 638 select FSL_PCIE_DISABLE_ASPM 639 select FSL_PCIE_RESET 640 select SYS_FSL_HAS_DDR3 641 select SYS_FSL_HAS_SEC 642 select SYS_FSL_SEC_BE 643 select SYS_FSL_SEC_COMPAT_2 644 select SYS_PPC_E500_USE_DEBUG_TLB 645 select FSL_ELBC 646 imply CMD_SATA 647 imply CMD_REGINFO 648 649config ARCH_P2020 650 bool 651 select FSL_LAW 652 select SYS_FSL_ERRATUM_A004477 653 select SYS_FSL_ERRATUM_A004508 654 select SYS_FSL_ERRATUM_A005125 655 select SYS_FSL_ERRATUM_ESDHC111 656 select SYS_FSL_ERRATUM_ESDHC_A001 657 select FSL_PCIE_RESET 658 select SYS_FSL_HAS_DDR3 659 select SYS_FSL_HAS_SEC 660 select SYS_FSL_SEC_BE 661 select SYS_FSL_SEC_COMPAT_2 662 select SYS_PPC_E500_USE_DEBUG_TLB 663 select FSL_ELBC 664 imply CMD_EEPROM 665 imply CMD_NAND 666 imply CMD_REGINFO 667 668config ARCH_P2041 669 bool 670 select E500MC 671 select FSL_LAW 672 select SYS_FSL_ERRATUM_A004510 673 select SYS_FSL_ERRATUM_A004849 674 select SYS_FSL_ERRATUM_A005275 675 select SYS_FSL_ERRATUM_A006261 676 select SYS_FSL_ERRATUM_CPU_A003999 677 select SYS_FSL_ERRATUM_DDR_A003 678 select SYS_FSL_ERRATUM_DDR_A003474 679 select SYS_FSL_ERRATUM_ESDHC111 680 select SYS_FSL_ERRATUM_I2C_A004447 681 select SYS_FSL_ERRATUM_NMG_CPU_A011 682 select SYS_FSL_ERRATUM_SRIO_A004034 683 select SYS_FSL_ERRATUM_USB14 684 select SYS_FSL_HAS_DDR3 685 select SYS_FSL_HAS_SEC 686 select SYS_FSL_QORIQ_CHASSIS1 687 select SYS_FSL_SEC_BE 688 select SYS_FSL_SEC_COMPAT_4 689 select FSL_ELBC 690 imply CMD_NAND 691 692config ARCH_P3041 693 bool 694 select E500MC 695 select FSL_LAW 696 select SYS_FSL_DDR_VER_44 697 select SYS_FSL_ERRATUM_A004510 698 select SYS_FSL_ERRATUM_A004849 699 select SYS_FSL_ERRATUM_A005275 700 select SYS_FSL_ERRATUM_A005812 701 select SYS_FSL_ERRATUM_A006261 702 select SYS_FSL_ERRATUM_CPU_A003999 703 select SYS_FSL_ERRATUM_DDR_A003 704 select SYS_FSL_ERRATUM_DDR_A003474 705 select SYS_FSL_ERRATUM_ESDHC111 706 select SYS_FSL_ERRATUM_I2C_A004447 707 select SYS_FSL_ERRATUM_NMG_CPU_A011 708 select SYS_FSL_ERRATUM_SRIO_A004034 709 select SYS_FSL_ERRATUM_USB14 710 select SYS_FSL_HAS_DDR3 711 select SYS_FSL_HAS_SEC 712 select SYS_FSL_QORIQ_CHASSIS1 713 select SYS_FSL_SEC_BE 714 select SYS_FSL_SEC_COMPAT_4 715 select FSL_ELBC 716 imply CMD_NAND 717 imply CMD_SATA 718 imply CMD_REGINFO 719 imply FSL_SATA 720 721config ARCH_P4080 722 bool 723 select E500MC 724 select FSL_LAW 725 select SYS_FSL_DDR_VER_44 726 select SYS_FSL_ERRATUM_A004510 727 select SYS_FSL_ERRATUM_A004580 728 select SYS_FSL_ERRATUM_A004849 729 select SYS_FSL_ERRATUM_A005812 730 select SYS_FSL_ERRATUM_A007075 731 select SYS_FSL_ERRATUM_CPC_A002 732 select SYS_FSL_ERRATUM_CPC_A003 733 select SYS_FSL_ERRATUM_CPU_A003999 734 select SYS_FSL_ERRATUM_DDR_A003 735 select SYS_FSL_ERRATUM_DDR_A003474 736 select SYS_FSL_ERRATUM_ELBC_A001 737 select SYS_FSL_ERRATUM_ESDHC111 738 select SYS_FSL_ERRATUM_ESDHC13 739 select SYS_FSL_ERRATUM_ESDHC135 740 select SYS_FSL_ERRATUM_I2C_A004447 741 select SYS_FSL_ERRATUM_NMG_CPU_A011 742 select SYS_FSL_ERRATUM_SRIO_A004034 743 select SYS_P4080_ERRATUM_CPU22 744 select SYS_P4080_ERRATUM_PCIE_A003 745 select SYS_P4080_ERRATUM_SERDES8 746 select SYS_P4080_ERRATUM_SERDES9 747 select SYS_P4080_ERRATUM_SERDES_A001 748 select SYS_P4080_ERRATUM_SERDES_A005 749 select SYS_FSL_HAS_DDR3 750 select SYS_FSL_HAS_SEC 751 select SYS_FSL_QORIQ_CHASSIS1 752 select SYS_FSL_SEC_BE 753 select SYS_FSL_SEC_COMPAT_4 754 select FSL_ELBC 755 imply CMD_SATA 756 imply CMD_REGINFO 757 imply SATA_SIL 758 759config ARCH_P5020 760 bool 761 select E500MC 762 select FSL_LAW 763 select SYS_FSL_DDR_VER_44 764 select SYS_FSL_ERRATUM_A004510 765 select SYS_FSL_ERRATUM_A005275 766 select SYS_FSL_ERRATUM_A006261 767 select SYS_FSL_ERRATUM_DDR_A003 768 select SYS_FSL_ERRATUM_DDR_A003474 769 select SYS_FSL_ERRATUM_ESDHC111 770 select SYS_FSL_ERRATUM_I2C_A004447 771 select SYS_FSL_ERRATUM_SRIO_A004034 772 select SYS_FSL_ERRATUM_USB14 773 select SYS_FSL_HAS_DDR3 774 select SYS_FSL_HAS_SEC 775 select SYS_FSL_QORIQ_CHASSIS1 776 select SYS_FSL_SEC_BE 777 select SYS_FSL_SEC_COMPAT_4 778 select SYS_PPC64 779 select FSL_ELBC 780 imply CMD_SATA 781 imply CMD_REGINFO 782 imply FSL_SATA 783 784config ARCH_P5040 785 bool 786 select E500MC 787 select FSL_LAW 788 select SYS_FSL_DDR_VER_44 789 select SYS_FSL_ERRATUM_A004510 790 select SYS_FSL_ERRATUM_A004699 791 select SYS_FSL_ERRATUM_A005275 792 select SYS_FSL_ERRATUM_A005812 793 select SYS_FSL_ERRATUM_A006261 794 select SYS_FSL_ERRATUM_DDR_A003 795 select SYS_FSL_ERRATUM_DDR_A003474 796 select SYS_FSL_ERRATUM_ESDHC111 797 select SYS_FSL_ERRATUM_USB14 798 select SYS_FSL_HAS_DDR3 799 select SYS_FSL_HAS_SEC 800 select SYS_FSL_QORIQ_CHASSIS1 801 select SYS_FSL_SEC_BE 802 select SYS_FSL_SEC_COMPAT_4 803 select SYS_PPC64 804 select FSL_ELBC 805 imply CMD_SATA 806 imply CMD_REGINFO 807 imply FSL_SATA 808 809config ARCH_QEMU_E500 810 bool 811 812config ARCH_T1023 813 bool 814 select E500MC 815 select FSL_LAW 816 select SYS_FSL_DDR_VER_50 817 select SYS_FSL_ERRATUM_A008378 818 select SYS_FSL_ERRATUM_A008109 819 select SYS_FSL_ERRATUM_A009663 820 select SYS_FSL_ERRATUM_A009942 821 select SYS_FSL_ERRATUM_ESDHC111 822 select SYS_FSL_HAS_DDR3 823 select SYS_FSL_HAS_DDR4 824 select SYS_FSL_HAS_SEC 825 select SYS_FSL_QORIQ_CHASSIS2 826 select SYS_FSL_SEC_BE 827 select SYS_FSL_SEC_COMPAT_5 828 select FSL_IFC 829 imply CMD_EEPROM 830 imply CMD_NAND 831 imply CMD_REGINFO 832 833config ARCH_T1024 834 bool 835 select E500MC 836 select FSL_LAW 837 select SYS_FSL_DDR_VER_50 838 select SYS_FSL_ERRATUM_A008378 839 select SYS_FSL_ERRATUM_A008109 840 select SYS_FSL_ERRATUM_A009663 841 select SYS_FSL_ERRATUM_A009942 842 select SYS_FSL_ERRATUM_ESDHC111 843 select SYS_FSL_HAS_DDR3 844 select SYS_FSL_HAS_DDR4 845 select SYS_FSL_HAS_SEC 846 select SYS_FSL_QORIQ_CHASSIS2 847 select SYS_FSL_SEC_BE 848 select SYS_FSL_SEC_COMPAT_5 849 select FSL_IFC 850 imply CMD_EEPROM 851 imply CMD_NAND 852 imply CMD_MTDPARTS 853 imply CMD_REGINFO 854 855config ARCH_T1040 856 bool 857 select E500MC 858 select FSL_LAW 859 select SYS_FSL_DDR_VER_50 860 select SYS_FSL_ERRATUM_A008044 861 select SYS_FSL_ERRATUM_A008378 862 select SYS_FSL_ERRATUM_A008109 863 select SYS_FSL_ERRATUM_A009663 864 select SYS_FSL_ERRATUM_A009942 865 select SYS_FSL_ERRATUM_ESDHC111 866 select SYS_FSL_HAS_DDR3 867 select SYS_FSL_HAS_DDR4 868 select SYS_FSL_HAS_SEC 869 select SYS_FSL_QORIQ_CHASSIS2 870 select SYS_FSL_SEC_BE 871 select SYS_FSL_SEC_COMPAT_5 872 select FSL_IFC 873 imply CMD_MTDPARTS 874 imply CMD_NAND 875 imply CMD_SATA 876 imply CMD_REGINFO 877 imply FSL_SATA 878 879config ARCH_T1042 880 bool 881 select E500MC 882 select FSL_LAW 883 select SYS_FSL_DDR_VER_50 884 select SYS_FSL_ERRATUM_A008044 885 select SYS_FSL_ERRATUM_A008378 886 select SYS_FSL_ERRATUM_A008109 887 select SYS_FSL_ERRATUM_A009663 888 select SYS_FSL_ERRATUM_A009942 889 select SYS_FSL_ERRATUM_ESDHC111 890 select SYS_FSL_HAS_DDR3 891 select SYS_FSL_HAS_DDR4 892 select SYS_FSL_HAS_SEC 893 select SYS_FSL_QORIQ_CHASSIS2 894 select SYS_FSL_SEC_BE 895 select SYS_FSL_SEC_COMPAT_5 896 select FSL_IFC 897 imply CMD_MTDPARTS 898 imply CMD_NAND 899 imply CMD_SATA 900 imply CMD_REGINFO 901 imply FSL_SATA 902 903config ARCH_T2080 904 bool 905 select E500MC 906 select E6500 907 select FSL_LAW 908 select SYS_FSL_DDR_VER_47 909 select SYS_FSL_ERRATUM_A006379 910 select SYS_FSL_ERRATUM_A006593 911 select SYS_FSL_ERRATUM_A007186 912 select SYS_FSL_ERRATUM_A007212 913 select SYS_FSL_ERRATUM_A007815 914 select SYS_FSL_ERRATUM_A007907 915 select SYS_FSL_ERRATUM_A008109 916 select SYS_FSL_ERRATUM_A009942 917 select SYS_FSL_ERRATUM_ESDHC111 918 select FSL_PCIE_RESET 919 select SYS_FSL_HAS_DDR3 920 select SYS_FSL_HAS_SEC 921 select SYS_FSL_QORIQ_CHASSIS2 922 select SYS_FSL_SEC_BE 923 select SYS_FSL_SEC_COMPAT_4 924 select SYS_PPC64 925 select FSL_IFC 926 imply CMD_SATA 927 imply CMD_NAND 928 imply CMD_REGINFO 929 imply FSL_SATA 930 931config ARCH_T2081 932 bool 933 select E500MC 934 select E6500 935 select FSL_LAW 936 select SYS_FSL_DDR_VER_47 937 select SYS_FSL_ERRATUM_A006379 938 select SYS_FSL_ERRATUM_A006593 939 select SYS_FSL_ERRATUM_A007186 940 select SYS_FSL_ERRATUM_A007212 941 select SYS_FSL_ERRATUM_A009942 942 select SYS_FSL_ERRATUM_ESDHC111 943 select FSL_PCIE_RESET 944 select SYS_FSL_HAS_DDR3 945 select SYS_FSL_HAS_SEC 946 select SYS_FSL_QORIQ_CHASSIS2 947 select SYS_FSL_SEC_BE 948 select SYS_FSL_SEC_COMPAT_4 949 select SYS_PPC64 950 select FSL_IFC 951 imply CMD_NAND 952 imply CMD_REGINFO 953 954config ARCH_T4160 955 bool 956 select E500MC 957 select E6500 958 select FSL_LAW 959 select SYS_FSL_DDR_VER_47 960 select SYS_FSL_ERRATUM_A004468 961 select SYS_FSL_ERRATUM_A005871 962 select SYS_FSL_ERRATUM_A006379 963 select SYS_FSL_ERRATUM_A006593 964 select SYS_FSL_ERRATUM_A007186 965 select SYS_FSL_ERRATUM_A007798 966 select SYS_FSL_ERRATUM_A009942 967 select SYS_FSL_HAS_DDR3 968 select SYS_FSL_HAS_SEC 969 select SYS_FSL_QORIQ_CHASSIS2 970 select SYS_FSL_SEC_BE 971 select SYS_FSL_SEC_COMPAT_4 972 select SYS_PPC64 973 select FSL_IFC 974 imply CMD_SATA 975 imply CMD_NAND 976 imply CMD_REGINFO 977 imply FSL_SATA 978 979config ARCH_T4240 980 bool 981 select E500MC 982 select E6500 983 select FSL_LAW 984 select SYS_FSL_DDR_VER_47 985 select SYS_FSL_ERRATUM_A004468 986 select SYS_FSL_ERRATUM_A005871 987 select SYS_FSL_ERRATUM_A006261 988 select SYS_FSL_ERRATUM_A006379 989 select SYS_FSL_ERRATUM_A006593 990 select SYS_FSL_ERRATUM_A007186 991 select SYS_FSL_ERRATUM_A007798 992 select SYS_FSL_ERRATUM_A007815 993 select SYS_FSL_ERRATUM_A007907 994 select SYS_FSL_ERRATUM_A008109 995 select SYS_FSL_ERRATUM_A009942 996 select SYS_FSL_HAS_DDR3 997 select SYS_FSL_HAS_SEC 998 select SYS_FSL_QORIQ_CHASSIS2 999 select SYS_FSL_SEC_BE 1000 select SYS_FSL_SEC_COMPAT_4 1001 select SYS_PPC64 1002 select FSL_IFC 1003 imply CMD_SATA 1004 imply CMD_NAND 1005 imply CMD_REGINFO 1006 imply FSL_SATA 1007 1008config MPC85XX_HAVE_RESET_VECTOR 1009 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc" 1010 depends on MPC85xx 1011 1012config BOOKE 1013 bool 1014 default y 1015 1016config E500 1017 bool 1018 default y 1019 help 1020 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 1021 1022config E500MC 1023 bool 1024 imply CMD_PCI 1025 help 1026 Enble PowerPC E500MC core 1027 1028config E6500 1029 bool 1030 help 1031 Enable PowerPC E6500 core 1032 1033config FSL_LAW 1034 bool 1035 help 1036 Use Freescale common code for Local Access Window 1037 1038config NXP_ESBC 1039 bool "NXP_ESBC" 1040 help 1041 Enable Freescale Secure Boot feature. Normally selected 1042 by defconfig. If unsure, do not change. 1043 1044config MAX_CPUS 1045 int "Maximum number of CPUs permitted for MPC85xx" 1046 default 12 if ARCH_T4240 1047 default 8 if ARCH_P4080 || \ 1048 ARCH_T4160 1049 default 4 if ARCH_B4860 || \ 1050 ARCH_P2041 || \ 1051 ARCH_P3041 || \ 1052 ARCH_P5040 || \ 1053 ARCH_T1040 || \ 1054 ARCH_T1042 || \ 1055 ARCH_T2080 || \ 1056 ARCH_T2081 1057 default 2 if ARCH_B4420 || \ 1058 ARCH_BSC9132 || \ 1059 ARCH_MPC8572 || \ 1060 ARCH_P1020 || \ 1061 ARCH_P1021 || \ 1062 ARCH_P1022 || \ 1063 ARCH_P1023 || \ 1064 ARCH_P1024 || \ 1065 ARCH_P1025 || \ 1066 ARCH_P2020 || \ 1067 ARCH_P5020 || \ 1068 ARCH_T1023 || \ 1069 ARCH_T1024 1070 default 1 1071 help 1072 Set this number to the maximum number of possible CPUs in the SoC. 1073 SoCs may have multiple clusters with each cluster may have multiple 1074 ports. If some ports are reserved but higher ports are used for 1075 cores, count the reserved ports. This will allocate enough memory 1076 in spin table to properly handle all cores. 1077 1078config SYS_CCSRBAR_DEFAULT 1079 hex "Default CCSRBAR address" 1080 default 0xff700000 if ARCH_BSC9131 || \ 1081 ARCH_BSC9132 || \ 1082 ARCH_C29X || \ 1083 ARCH_MPC8536 || \ 1084 ARCH_MPC8540 || \ 1085 ARCH_MPC8541 || \ 1086 ARCH_MPC8544 || \ 1087 ARCH_MPC8548 || \ 1088 ARCH_MPC8555 || \ 1089 ARCH_MPC8560 || \ 1090 ARCH_MPC8568 || \ 1091 ARCH_MPC8572 || \ 1092 ARCH_P1010 || \ 1093 ARCH_P1011 || \ 1094 ARCH_P1020 || \ 1095 ARCH_P1021 || \ 1096 ARCH_P1022 || \ 1097 ARCH_P1024 || \ 1098 ARCH_P1025 || \ 1099 ARCH_P2020 1100 default 0xff600000 if ARCH_P1023 1101 default 0xfe000000 if ARCH_B4420 || \ 1102 ARCH_B4860 || \ 1103 ARCH_P2041 || \ 1104 ARCH_P3041 || \ 1105 ARCH_P4080 || \ 1106 ARCH_P5020 || \ 1107 ARCH_P5040 || \ 1108 ARCH_T1023 || \ 1109 ARCH_T1024 || \ 1110 ARCH_T1040 || \ 1111 ARCH_T1042 || \ 1112 ARCH_T2080 || \ 1113 ARCH_T2081 || \ 1114 ARCH_T4160 || \ 1115 ARCH_T4240 1116 default 0xe0000000 if ARCH_QEMU_E500 1117 help 1118 Default value of CCSRBAR comes from power-on-reset. It 1119 is fixed on each SoC. Some SoCs can have different value 1120 if changed by pre-boot regime. The value here must match 1121 the current value in SoC. If not sure, do not change. 1122 1123config SYS_FSL_ERRATUM_A004468 1124 bool 1125 1126config SYS_FSL_ERRATUM_A004477 1127 bool 1128 1129config SYS_FSL_ERRATUM_A004508 1130 bool 1131 1132config SYS_FSL_ERRATUM_A004580 1133 bool 1134 1135config SYS_FSL_ERRATUM_A004699 1136 bool 1137 1138config SYS_FSL_ERRATUM_A004849 1139 bool 1140 1141config SYS_FSL_ERRATUM_A004510 1142 bool 1143 1144config SYS_FSL_ERRATUM_A004510_SVR_REV 1145 hex 1146 depends on SYS_FSL_ERRATUM_A004510 1147 default 0x20 if ARCH_P4080 1148 default 0x10 1149 1150config SYS_FSL_ERRATUM_A004510_SVR_REV2 1151 hex 1152 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1153 default 0x11 1154 1155config SYS_FSL_ERRATUM_A005125 1156 bool 1157 1158config SYS_FSL_ERRATUM_A005434 1159 bool 1160 1161config SYS_FSL_ERRATUM_A005812 1162 bool 1163 1164config SYS_FSL_ERRATUM_A005871 1165 bool 1166 1167config SYS_FSL_ERRATUM_A005275 1168 bool 1169 1170config SYS_FSL_ERRATUM_A006261 1171 bool 1172 1173config SYS_FSL_ERRATUM_A006379 1174 bool 1175 1176config SYS_FSL_ERRATUM_A006384 1177 bool 1178 1179config SYS_FSL_ERRATUM_A006475 1180 bool 1181 1182config SYS_FSL_ERRATUM_A006593 1183 bool 1184 1185config SYS_FSL_ERRATUM_A007075 1186 bool 1187 1188config SYS_FSL_ERRATUM_A007186 1189 bool 1190 1191config SYS_FSL_ERRATUM_A007212 1192 bool 1193 1194config SYS_FSL_ERRATUM_A007815 1195 bool 1196 1197config SYS_FSL_ERRATUM_A007798 1198 bool 1199 1200config SYS_FSL_ERRATUM_A007907 1201 bool 1202 1203config SYS_FSL_ERRATUM_A008044 1204 bool 1205 1206config SYS_FSL_ERRATUM_CPC_A002 1207 bool 1208 1209config SYS_FSL_ERRATUM_CPC_A003 1210 bool 1211 1212config SYS_FSL_ERRATUM_CPU_A003999 1213 bool 1214 1215config SYS_FSL_ERRATUM_ELBC_A001 1216 bool 1217 1218config SYS_FSL_ERRATUM_I2C_A004447 1219 bool 1220 1221config SYS_FSL_A004447_SVR_REV 1222 hex 1223 depends on SYS_FSL_ERRATUM_I2C_A004447 1224 default 0x00 if ARCH_MPC8548 1225 default 0x10 if ARCH_P1010 1226 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1227 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1228 1229config SYS_FSL_ERRATUM_IFC_A002769 1230 bool 1231 1232config SYS_FSL_ERRATUM_IFC_A003399 1233 bool 1234 1235config SYS_FSL_ERRATUM_NMG_CPU_A011 1236 bool 1237 1238config SYS_FSL_ERRATUM_NMG_ETSEC129 1239 bool 1240 1241config SYS_FSL_ERRATUM_NMG_LBC103 1242 bool 1243 1244config SYS_FSL_ERRATUM_P1010_A003549 1245 bool 1246 1247config SYS_FSL_ERRATUM_SATA_A001 1248 bool 1249 1250config SYS_FSL_ERRATUM_SEC_A003571 1251 bool 1252 1253config SYS_FSL_ERRATUM_SRIO_A004034 1254 bool 1255 1256config SYS_FSL_ERRATUM_USB14 1257 bool 1258 1259config SYS_P4080_ERRATUM_CPU22 1260 bool 1261 1262config SYS_P4080_ERRATUM_PCIE_A003 1263 bool 1264 1265config SYS_P4080_ERRATUM_SERDES8 1266 bool 1267 1268config SYS_P4080_ERRATUM_SERDES9 1269 bool 1270 1271config SYS_P4080_ERRATUM_SERDES_A001 1272 bool 1273 1274config SYS_P4080_ERRATUM_SERDES_A005 1275 bool 1276 1277config FSL_PCIE_DISABLE_ASPM 1278 bool 1279 1280config FSL_PCIE_RESET 1281 bool 1282 1283config SYS_FSL_QORIQ_CHASSIS1 1284 bool 1285 1286config SYS_FSL_QORIQ_CHASSIS2 1287 bool 1288 1289config SYS_FSL_NUM_LAWS 1290 int "Number of local access windows" 1291 depends on FSL_LAW 1292 default 32 if ARCH_B4420 || \ 1293 ARCH_B4860 || \ 1294 ARCH_P2041 || \ 1295 ARCH_P3041 || \ 1296 ARCH_P4080 || \ 1297 ARCH_P5020 || \ 1298 ARCH_P5040 || \ 1299 ARCH_T2080 || \ 1300 ARCH_T2081 || \ 1301 ARCH_T4160 || \ 1302 ARCH_T4240 1303 default 16 if ARCH_T1023 || \ 1304 ARCH_T1024 || \ 1305 ARCH_T1040 || \ 1306 ARCH_T1042 1307 default 12 if ARCH_BSC9131 || \ 1308 ARCH_BSC9132 || \ 1309 ARCH_C29X || \ 1310 ARCH_MPC8536 || \ 1311 ARCH_MPC8572 || \ 1312 ARCH_P1010 || \ 1313 ARCH_P1011 || \ 1314 ARCH_P1020 || \ 1315 ARCH_P1021 || \ 1316 ARCH_P1022 || \ 1317 ARCH_P1023 || \ 1318 ARCH_P1024 || \ 1319 ARCH_P1025 || \ 1320 ARCH_P2020 1321 default 10 if ARCH_MPC8544 || \ 1322 ARCH_MPC8548 || \ 1323 ARCH_MPC8568 1324 default 8 if ARCH_MPC8540 || \ 1325 ARCH_MPC8541 || \ 1326 ARCH_MPC8555 || \ 1327 ARCH_MPC8560 1328 help 1329 Number of local access windows. This is fixed per SoC. 1330 If not sure, do not change. 1331 1332config SYS_FSL_THREADS_PER_CORE 1333 int 1334 default 2 if E6500 1335 default 1 1336 1337config SYS_NUM_TLBCAMS 1338 int "Number of TLB CAM entries" 1339 default 64 if E500MC 1340 default 16 1341 help 1342 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1343 16 for other E500 SoCs. 1344 1345config SYS_PPC64 1346 bool 1347 1348config SYS_PPC_E500_USE_DEBUG_TLB 1349 bool 1350 1351config FSL_IFC 1352 bool 1353 1354config FSL_ELBC 1355 bool 1356 1357config SYS_PPC_E500_DEBUG_TLB 1358 int "Temporary TLB entry for external debugger" 1359 depends on SYS_PPC_E500_USE_DEBUG_TLB 1360 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1361 default 1 if ARCH_MPC8536 1362 default 2 if ARCH_MPC8572 || \ 1363 ARCH_P1011 || \ 1364 ARCH_P1020 || \ 1365 ARCH_P1021 || \ 1366 ARCH_P1022 || \ 1367 ARCH_P1024 || \ 1368 ARCH_P1025 || \ 1369 ARCH_P2020 1370 default 3 if ARCH_P1010 || \ 1371 ARCH_BSC9132 || \ 1372 ARCH_C29X 1373 help 1374 Select a temporary TLB entry to be used during boot to work 1375 around limitations in e500v1 and e500v2 external debugger 1376 support. This reduces the portions of the boot code where 1377 breakpoints and single stepping do not work. The value of this 1378 symbol should be set to the TLB1 entry to be used for this 1379 purpose. If unsure, do not change. 1380 1381config SYS_FSL_IFC_CLK_DIV 1382 int "Divider of platform clock" 1383 depends on FSL_IFC 1384 default 2 if ARCH_B4420 || \ 1385 ARCH_B4860 || \ 1386 ARCH_T1024 || \ 1387 ARCH_T1023 || \ 1388 ARCH_T1040 || \ 1389 ARCH_T1042 || \ 1390 ARCH_T4160 || \ 1391 ARCH_T4240 1392 default 1 1393 help 1394 Defines divider of platform clock(clock input to 1395 IFC controller). 1396 1397config SYS_FSL_LBC_CLK_DIV 1398 int "Divider of platform clock" 1399 depends on FSL_ELBC || ARCH_MPC8540 || \ 1400 ARCH_MPC8548 || ARCH_MPC8541 || \ 1401 ARCH_MPC8555 || ARCH_MPC8560 || \ 1402 ARCH_MPC8568 1403 1404 default 2 if ARCH_P2041 || \ 1405 ARCH_P3041 || \ 1406 ARCH_P4080 || \ 1407 ARCH_P5020 || \ 1408 ARCH_P5040 1409 default 1 1410 1411 help 1412 Defines divider of platform clock(clock input to 1413 eLBC controller). 1414 1415config FSL_VIA 1416 bool 1417 1418source "board/emulation/qemu-ppce500/Kconfig" 1419source "board/freescale/corenet_ds/Kconfig" 1420source "board/freescale/mpc8541cds/Kconfig" 1421source "board/freescale/mpc8548cds/Kconfig" 1422source "board/freescale/mpc8555cds/Kconfig" 1423source "board/freescale/mpc8568mds/Kconfig" 1424source "board/freescale/p1010rdb/Kconfig" 1425source "board/freescale/p1_p2_rdb_pc/Kconfig" 1426source "board/freescale/p2041rdb/Kconfig" 1427source "board/freescale/t102xrdb/Kconfig" 1428source "board/freescale/t104xrdb/Kconfig" 1429source "board/freescale/t208xqds/Kconfig" 1430source "board/freescale/t208xrdb/Kconfig" 1431source "board/freescale/t4rdb/Kconfig" 1432source "board/gdsys/p1022/Kconfig" 1433source "board/keymile/Kconfig" 1434source "board/sbc8548/Kconfig" 1435source "board/socrates/Kconfig" 1436source "board/varisys/cyrus/Kconfig" 1437source "board/xes/xpedite520x/Kconfig" 1438source "board/xes/xpedite537x/Kconfig" 1439source "board/xes/xpedite550x/Kconfig" 1440source "board/Arcturus/ucp1020/Kconfig" 1441 1442endmenu 1443