1 /* 2 * (C) Copyright 2013 3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4 * 5 * based on P1022DS.h 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #include <linux/stringify.h> 30 31 #ifdef CONFIG_SDCARD 32 #define CONFIG_RAMBOOT_SDCARD 33 #endif 34 35 #ifdef CONFIG_SPIFLASH 36 #define CONFIG_RAMBOOT_SPIFLASH 37 #endif 38 39 /* High Level Configuration Options */ 40 #define CONFIG_CONTROLCENTERD 41 42 #define CONFIG_ENABLE_36BIT_PHYS 43 44 #define CONFIG_L2_CACHE 45 #define CONFIG_BTB 46 47 #define CONFIG_SYS_CLK_FREQ 66666600 48 #define CONFIG_DDR_CLK_FREQ 66666600 49 50 #define CONFIG_SYS_RAMBOOT 51 52 #ifdef CONFIG_TRAILBLAZER 53 54 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 55 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 56 57 /* 58 * Config the L2 Cache 59 */ 60 #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000 61 #ifdef CONFIG_PHYS_64BIT 62 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull 63 #else 64 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 65 #endif 66 #define CONFIG_SYS_L2_SIZE (256 << 10) 67 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 68 69 #else /* CONFIG_TRAILBLAZER */ 70 71 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 72 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 73 74 #endif /* CONFIG_TRAILBLAZER */ 75 76 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 77 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 78 79 /* 80 * Memory map 81 * 82 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable 83 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable 84 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 85 * 86 * Localbus non-cacheable 87 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable 88 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable 89 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 90 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 91 */ 92 93 #define CONFIG_SYS_INIT_RAM_LOCK 94 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 95 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */ 96 #define CONFIG_SYS_GBL_DATA_OFFSET \ 97 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 98 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 99 100 #ifdef CONFIG_TRAILBLAZER 101 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */ 102 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 103 #else 104 #define CONFIG_SYS_CCSRBAR 0xffe00000 105 #endif 106 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 107 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200) 108 109 /* 110 * DDR Setup 111 */ 112 113 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 114 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 115 #define CONFIG_SYS_SDRAM_SIZE 1024 116 #define CONFIG_VERY_BIG_RAM 117 118 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 119 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 120 121 #ifdef CONFIG_TRAILBLAZER 122 #define CONFIG_SPD_EEPROM 123 #define SPD_EEPROM_ADDRESS 0x52 124 /*#define CONFIG_FSL_DDR_INTERACTIVE*/ 125 #endif 126 127 /* 128 * Local Bus Definitions 129 */ 130 131 #define CONFIG_SYS_ELBC_BASE 0xe0000000 132 #ifdef CONFIG_PHYS_64BIT 133 #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull 134 #else 135 #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE 136 #endif 137 138 #define CONFIG_UART_BR_PRELIM \ 139 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V) 140 #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7) 141 142 #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */ 143 #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */ 144 145 #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM 146 #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM 147 148 /* 149 * Serial Port 150 */ 151 #define CONFIG_SYS_NS16550_SERIAL 152 #define CONFIG_SYS_NS16550_REG_SIZE 1 153 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 154 155 #define CONFIG_SYS_BAUDRATE_TABLE \ 156 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 157 158 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 159 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 160 161 /* 162 * I2C 163 */ 164 #define CONFIG_SYS_I2C 165 #define CONFIG_SYS_I2C_FSL 166 #define CONFIG_SYS_FSL_I2C_SPEED 400000 167 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 168 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 169 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 170 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 171 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 172 173 #define CONFIG_PCA9698 /* NXP PCA9698 */ 174 175 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 176 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 177 178 /* 179 * MMC 180 */ 181 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 182 183 #ifndef CONFIG_TRAILBLAZER 184 185 /* 186 * Video 187 */ 188 #define CONFIG_FSL_DIU_FB 189 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 190 191 /* 192 * General PCI 193 * Memory space is mapped 1-1, but I/O space must start from 0. 194 */ 195 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 196 #define CONFIG_PCI_INDIRECT_BRIDGE 197 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 198 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 199 200 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 201 202 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 203 #ifdef CONFIG_PHYS_64BIT 204 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 205 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 206 #else 207 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 208 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 209 #endif 210 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 211 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 212 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 213 #ifdef CONFIG_PHYS_64BIT 214 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 215 #else 216 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 217 #endif 218 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 219 220 /* 221 * SATA 222 */ 223 #define CONFIG_LBA48 224 225 #define CONFIG_SYS_SATA_MAX_DEVICE 2 226 #define CONFIG_SATA1 227 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 228 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 229 #define CONFIG_SATA2 230 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 231 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 232 233 /* 234 * Ethernet 235 */ 236 237 #define CONFIG_TSECV2 238 239 #define CONFIG_TSEC1 1 240 #define CONFIG_TSEC1_NAME "eTSEC1" 241 #define CONFIG_TSEC2 1 242 #define CONFIG_TSEC2_NAME "eTSEC2" 243 244 #define TSEC1_PHY_ADDR 0 245 #define TSEC2_PHY_ADDR 1 246 247 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 248 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 249 250 #define TSEC1_PHYIDX 0 251 #define TSEC2_PHYIDX 0 252 253 #define CONFIG_ETHPRIME "eTSEC1" 254 255 /* 256 * USB 257 */ 258 259 #define CONFIG_HAS_FSL_DR_USB 260 #define CONFIG_USB_EHCI_FSL 261 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 262 263 #endif /* CONFIG_TRAILBLAZER */ 264 265 /* 266 * Environment 267 */ 268 #if defined(CONFIG_TRAILBLAZER) 269 #elif defined(CONFIG_RAMBOOT_SDCARD) 270 #define CONFIG_FSL_FIXED_MMC_LOCATION 271 #endif 272 273 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 274 275 #ifndef CONFIG_TRAILBLAZER 276 /* 277 * Board initialisation callbacks 278 */ 279 #endif /* CONFIG_TRAILBLAZER */ 280 281 /* 282 * Miscellaneous configurable options 283 */ 284 #define CONFIG_HW_WATCHDOG 285 #define CONFIG_LOADS_ECHO 286 #define CONFIG_SYS_LOADS_BAUD_CHANGE 287 288 /* 289 * For booting Linux, the board info and command line data 290 * have to be in the first 64 MB of memory, since this is 291 * the maximum mapped by the Linux kernel during initialization. 292 */ 293 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */ 294 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 295 296 /* 297 * Environment Configuration 298 */ 299 300 #ifdef CONFIG_TRAILBLAZER 301 #define CONFIG_EXTRA_ENV_SETTINGS \ 302 "mp_holdoff=1\0" 303 304 #else 305 306 #define CONFIG_HOSTNAME "controlcenterd" 307 #define CONFIG_ROOTPATH "/opt/nfsroot" 308 #define CONFIG_BOOTFILE "uImage" 309 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */ 310 311 #define CONFIG_LOADADDR 1000000 312 313 #define CONFIG_EXTRA_ENV_SETTINGS \ 314 "netdev=eth0\0" \ 315 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 316 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 317 "tftpflash=tftpboot $loadaddr $uboot && " \ 318 "protect off $ubootaddr +$filesize && " \ 319 "erase $ubootaddr +$filesize && " \ 320 "cp.b $loadaddr $ubootaddr $filesize && " \ 321 "protect on $ubootaddr +$filesize && " \ 322 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 323 "consoledev=ttyS1\0" \ 324 "ramdiskaddr=2000000\0" \ 325 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 326 "fdtaddr=1e00000\0" \ 327 "fdtfile=controlcenterd.dtb\0" \ 328 "bdev=sda3\0" 329 330 /* these are used and NUL-terminated in env_default.h */ 331 #define CONFIG_NFSBOOTCOMMAND \ 332 "setenv bootargs root=/dev/nfs rw " \ 333 "nfsroot=$serverip:$rootpath " \ 334 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 335 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 336 "tftp $loadaddr $bootfile;" \ 337 "tftp $fdtaddr $fdtfile;" \ 338 "bootm $loadaddr - $fdtaddr" 339 340 #define CONFIG_RAMBOOTCOMMAND \ 341 "setenv bootargs root=/dev/ram rw " \ 342 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 343 "tftp $ramdiskaddr $ramdiskfile;" \ 344 "tftp $loadaddr $bootfile;" \ 345 "tftp $fdtaddr $fdtfile;" \ 346 "bootm $loadaddr $ramdiskaddr $fdtaddr" 347 348 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 349 350 #endif /* CONFIG_TRAILBLAZER */ 351 352 #endif 353