1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright (c) 2015, Linaro Limited
4  * Copyright (c) 2019, Arm Limited. All rights reserved.
5  */
6 #ifndef ARM_H
7 #define ARM_H
8 
9 #include <stdbool.h>
10 #include <stdint.h>
11 #include <util.h>
12 
13 /* MIDR definitions */
14 #define MIDR_PRIMARY_PART_NUM_SHIFT	U(4)
15 #define MIDR_PRIMARY_PART_NUM_WIDTH	U(12)
16 #define MIDR_PRIMARY_PART_NUM_MASK	(BIT(MIDR_PRIMARY_PART_NUM_WIDTH) - 1)
17 
18 #define MIDR_IMPLEMENTER_SHIFT		U(24)
19 #define MIDR_IMPLEMENTER_WIDTH		U(8)
20 #define MIDR_IMPLEMENTER_MASK		(BIT(MIDR_IMPLEMENTER_WIDTH) - 1)
21 #define MIDR_IMPLEMENTER_ARM		U(0x41)
22 
23 #define CORTEX_A7_PART_NUM		U(0xC07)
24 #define CORTEX_A8_PART_NUM		U(0xC08)
25 #define CORTEX_A9_PART_NUM		U(0xC09)
26 #define CORTEX_A15_PART_NUM		U(0xC0F)
27 #define CORTEX_A17_PART_NUM		U(0xC0E)
28 #define CORTEX_A57_PART_NUM		U(0xD07)
29 #define CORTEX_A72_PART_NUM		U(0xD08)
30 #define CORTEX_A73_PART_NUM		U(0xD09)
31 #define CORTEX_A75_PART_NUM		U(0xD0A)
32 
33 /* MPIDR definitions */
34 #define MPIDR_AFFINITY_BITS	U(8)
35 #define MPIDR_AFFLVL_MASK	U(0xff)
36 #define MPIDR_AFF0_SHIFT	U(0)
37 #define MPIDR_AFF0_MASK		(MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)
38 #define MPIDR_AFF1_SHIFT	U(8)
39 #define MPIDR_AFF1_MASK		(MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)
40 #define MPIDR_AFF2_SHIFT	U(16)
41 #define MPIDR_AFF2_MASK		(MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)
42 
43 #define MPIDR_MT_SHIFT		U(24)
44 #define MPIDR_MT_MASK		BIT(MPIDR_MT_SHIFT)
45 
46 #define MPIDR_CPU_MASK		MPIDR_AFF0_MASK
47 #define MPIDR_CLUSTER_SHIFT	MPIDR_AFF1_SHIFT
48 #define MPIDR_CLUSTER_MASK	MPIDR_AFF1_MASK
49 
50 #define MPIDR_AARCH32_AFF_MASK	(MPIDR_AFF0_MASK | MPIDR_AFF1_MASK | \
51 				 MPIDR_AFF2_MASK)
52 
53 /* CLIDR definitions */
54 #define CLIDR_LOUIS_SHIFT	U(21)
55 #define CLIDR_LOC_SHIFT		U(24)
56 #define CLIDR_FIELD_WIDTH	U(3)
57 
58 /* CSSELR definitions */
59 #define CSSELR_LEVEL_SHIFT	U(1)
60 
61 /* CTR definitions */
62 #define CTR_CWG_SHIFT		U(24)
63 #define CTR_CWG_MASK		U(0xf)
64 #define CTR_ERG_SHIFT		U(20)
65 #define CTR_ERG_MASK		U(0xf)
66 #define CTR_DMINLINE_SHIFT	U(16)
67 #define CTR_DMINLINE_WIDTH	U(4)
68 #define CTR_DMINLINE_MASK	(BIT(4) - 1)
69 #define CTR_L1IP_SHIFT		U(14)
70 #define CTR_L1IP_MASK		U(0x3)
71 #define CTR_IMINLINE_SHIFT	U(0)
72 #define CTR_IMINLINE_MASK	U(0xf)
73 #define CTR_WORD_SIZE		U(4)
74 
75 #define ARM32_CPSR_MODE_MASK	U(0x1f)
76 #define ARM32_CPSR_MODE_USR	U(0x10)
77 #define ARM32_CPSR_MODE_FIQ	U(0x11)
78 #define ARM32_CPSR_MODE_IRQ	U(0x12)
79 #define ARM32_CPSR_MODE_SVC	U(0x13)
80 #define ARM32_CPSR_MODE_MON	U(0x16)
81 #define ARM32_CPSR_MODE_ABT	U(0x17)
82 #define ARM32_CPSR_MODE_UND	U(0x1b)
83 #define ARM32_CPSR_MODE_SYS	U(0x1f)
84 
85 #define ARM32_CPSR_T		BIT(5)
86 #define ARM32_CPSR_F_SHIFT	U(6)
87 #define ARM32_CPSR_F		BIT(6)
88 #define ARM32_CPSR_I		BIT(7)
89 #define ARM32_CPSR_A		BIT(8)
90 #define ARM32_CPSR_E		BIT(9)
91 #define ARM32_CPSR_FIA		(ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A)
92 #define ARM32_CPSR_IT_MASK	(ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2)
93 #define ARM32_CPSR_IT_MASK1	U(0x06000000)
94 #define ARM32_CPSR_IT_MASK2	U(0x0000fc00)
95 
96 /* ARM Generic timer definitions */
97 #define CNTKCTL_PL0PCTEN	BIT(0) /* physical counter el0 access enable */
98 #define CNTKCTL_PL0VCTEN	BIT(1) /* virtual counter el0 access enable */
99 
100 #ifdef ARM32
101 #include <arm32.h>
102 #endif
103 
104 #ifdef ARM64
105 #include <arm64.h>
106 #endif
107 
108 #ifndef __ASSEMBLER__
barrier_read_counter_timer(void)109 static inline __noprof uint64_t barrier_read_counter_timer(void)
110 {
111 	isb();
112 #ifdef CFG_CORE_SEL2_SPMC
113 	return read_cntvct();
114 #else
115 	return read_cntpct();
116 #endif
117 }
118 
feat_bti_is_implemented(void)119 static inline bool feat_bti_is_implemented(void)
120 {
121 #ifdef ARM32
122 	return false;
123 #else
124 	return ((read_id_aa64pfr1_el1() & ID_AA64PFR1_EL1_BT_MASK) ==
125 		FEAT_BTI_IMPLEMENTED);
126 #endif
127 }
128 #endif
129 
130 #endif /*ARM_H*/
131