1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A55_H 8 #define CORTEX_A55_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A55 MIDR for revision 0 */ 13 #define CORTEX_A55_MIDR U(0x410fd050) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions. 17 ******************************************************************************/ 18 #define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19 #define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 20 21 #define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25) 22 23 /******************************************************************************* 24 * CPU Auxiliary Control register specific definitions. 25 ******************************************************************************/ 26 #define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0 27 28 #define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24) 29 #define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31) 30 #define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49) 31 32 /******************************************************************************* 33 * CPU Identification register specific definitions. 34 ******************************************************************************/ 35 #define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1 36 37 #define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6) 38 39 /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ 40 #define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) 41 42 /* Instruction patching registers */ 43 #define CPUPSELR_EL3 S3_6_C15_C8_0 44 #define CPUPCR_EL3 S3_6_C15_C8_1 45 #define CPUPOR_EL3 S3_6_C15_C8_2 46 #define CPUPMR_EL3 S3_6_C15_C8_3 47 48 #endif /* CORTEX_A55_H */ 49