1 /*
2  * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_A73_H
8 #define CORTEX_A73_H
9 
10 #include <lib/utils_def.h>
11 
12 /* Cortex-A73 midr for revision 0 */
13 #define CORTEX_A73_MIDR			U(0x410FD090)
14 
15 /*******************************************************************************
16  * CPU Extended Control register specific definitions.
17  ******************************************************************************/
18 #define CORTEX_A73_CPUECTLR_EL1		S3_1_C15_C2_1	/* Instruction def. */
19 
20 #define CORTEX_A73_CPUECTLR_SMP_BIT	(ULL(1) << 6)
21 
22 /*******************************************************************************
23  * L2 Memory Error Syndrome register specific definitions.
24  ******************************************************************************/
25 #define CORTEX_A73_L2MERRSR_EL1		S3_1_C15_C2_3   /* Instruction def. */
26 
27 /*******************************************************************************
28  * CPU implementation defined register specific definitions.
29  ******************************************************************************/
30 #define CORTEX_A73_IMP_DEF_REG1		S3_0_C15_C0_0
31 
32 #define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE	(ULL(1) << 3)
33 
34 #define CORTEX_A73_DIAGNOSTIC_REGISTER	S3_0_C15_C0_1
35 
36 #define CORTEX_A73_IMP_DEF_REG2		S3_0_C15_C0_2
37 
38 /*******************************************************************************
39  * Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs
40  ******************************************************************************/
41 #ifndef __ASSEMBLER__
42 DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1)
43 #endif /* __ASSEMBLER__ */
44 
45 #endif /* CORTEX_A73_H */
46