1 /* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A76_H 8 #define CORTEX_A76_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A76 MIDR for revision 0 */ 13 #define CORTEX_A76_MIDR U(0x410fd0b0) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions. 17 ******************************************************************************/ 18 #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19 #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 20 21 #define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) 22 #define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51) 23 24 /******************************************************************************* 25 * CPU Auxiliary Control register specific definitions. 26 ******************************************************************************/ 27 #define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 28 29 #define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) 30 31 #define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 32 33 #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 34 35 #define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 36 37 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) 38 39 #define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 40 41 #define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 42 43 44 /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ 45 #define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) 46 47 #endif /* CORTEX_A76_H */ 48