1 /* 2 * Copyright (c) 2019-2021, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A78_H 8 #define CORTEX_A78_H 9 10 #include <lib/utils_def.h> 11 12 #define CORTEX_A78_MIDR U(0x410FD410) 13 14 /******************************************************************************* 15 * CPU Extended Control register specific definitions. 16 ******************************************************************************/ 17 #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 18 #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) 19 #define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) 20 #define CPUECTLR_EL1_PF_MODE_LSB U(6) 21 #define CPUECTLR_EL1_PF_MODE_WIDTH U(2) 22 23 /******************************************************************************* 24 * CPU Power Control register specific definitions 25 ******************************************************************************/ 26 #define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7 27 #define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 28 29 /******************************************************************************* 30 * CPU Auxiliary Control register specific definitions. 31 ******************************************************************************/ 32 #define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30) 33 34 #define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1 35 #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1) 36 #define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2) 37 38 /******************************************************************************* 39 * CPU Activity Monitor Unit register specific definitions. 40 ******************************************************************************/ 41 #define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4 42 #define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5 43 #define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0 44 #define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1 45 46 #define CORTEX_A78_AMU_GROUP0_MASK U(0xF) 47 #define CORTEX_A78_AMU_GROUP1_MASK U(0x7) 48 49 #endif /* CORTEX_A78_H */ 50