1 /* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SGI_BASE_PLATFORM_DEF_H 8 #define SGI_BASE_PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 #include <plat/arm/common/arm_def.h> 13 #include <plat/arm/common/arm_spm_def.h> 14 #include <plat/arm/css/common/css_def.h> 15 #include <plat/common/common_def.h> 16 17 #define PLATFORM_CORE_COUNT (CSS_SGI_CHIP_COUNT * \ 18 PLAT_ARM_CLUSTER_COUNT * \ 19 CSS_SGI_MAX_CPUS_PER_CLUSTER * \ 20 CSS_SGI_MAX_PE_PER_CPU) 21 22 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ 23 24 /* Remote chip address offset (4TB per chip) */ 25 #define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) ((ULL(1) << 42) * (n)) 26 27 /* 28 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 29 * plat_arm_mmap array defined for each BL stage. In addition to that, on 30 * multi-chip platforms, address regions on each of the remote chips are 31 * also mapped. In BL31, for instance, three address regions on the remote 32 * chips are accessed - secure ram, css device and soc device regions. 33 */ 34 #if defined(IMAGE_BL31) 35 # if SPM_MM 36 # define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) 37 # define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) 38 # define PLAT_SP_IMAGE_MMAP_REGIONS 9 39 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 11 40 # else 41 # define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) 42 # define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) 43 # endif 44 #elif defined(IMAGE_BL32) 45 # define PLAT_ARM_MMAP_ENTRIES 8 46 # define MAX_XLAT_TABLES 5 47 #elif defined(IMAGE_BL2) 48 # define PLAT_ARM_MMAP_ENTRIES (11 + (CSS_SGI_CHIP_COUNT - 1)) 49 50 /* 51 * MAX_XLAT_TABLES entries need to be doubled because when the address width 52 * exceeds 40 bits an additional level of translation is required. In case of 53 * multichip platforms peripherals also fall into address space with width 54 * > 40 bits 55 * 56 */ 57 # define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 2)) 58 #elif !USE_ROMLIB 59 # define PLAT_ARM_MMAP_ENTRIES 11 60 # define MAX_XLAT_TABLES 7 61 #else 62 # define PLAT_ARM_MMAP_ENTRIES 12 63 # define MAX_XLAT_TABLES 6 64 #endif 65 66 /* 67 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 68 * plus a little space for growth. 69 */ 70 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 71 72 /* 73 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 74 */ 75 76 #if USE_ROMLIB 77 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 78 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 79 #else 80 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 81 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 82 #endif 83 84 /* 85 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 86 * little space for growth. Additional 8KiB space is added per chip in 87 * order to accommodate the additional level of translation required for "TZC" 88 * peripheral access which lies in >4TB address space. 89 * 90 */ 91 #if TRUSTED_BOARD_BOOT 92 # define PLAT_ARM_MAX_BL2_SIZE (0x20000 + ((CSS_SGI_CHIP_COUNT - 1) * \ 93 0x2000)) 94 #else 95 # define PLAT_ARM_MAX_BL2_SIZE (0x14000 + ((CSS_SGI_CHIP_COUNT - 1) * \ 96 0x2000)) 97 #endif 98 99 /* 100 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 101 * calculated using the current BL31 PROGBITS debug size plus the sizes of 102 * BL2 and BL1-RW 103 */ 104 #define PLAT_ARM_MAX_BL31_SIZE 0x3B000 105 106 /* 107 * Size of cacheable stacks 108 */ 109 #if defined(IMAGE_BL1) 110 # if TRUSTED_BOARD_BOOT 111 # define PLATFORM_STACK_SIZE 0x1000 112 # else 113 # define PLATFORM_STACK_SIZE 0x440 114 # endif 115 #elif defined(IMAGE_BL2) 116 # if TRUSTED_BOARD_BOOT 117 # define PLATFORM_STACK_SIZE 0x1000 118 # else 119 # define PLATFORM_STACK_SIZE 0x400 120 # endif 121 #elif defined(IMAGE_BL2U) 122 # define PLATFORM_STACK_SIZE 0x400 123 #elif defined(IMAGE_BL31) 124 # if SPM_MM 125 # define PLATFORM_STACK_SIZE 0x500 126 # else 127 # define PLATFORM_STACK_SIZE 0x400 128 # endif 129 #elif defined(IMAGE_BL32) 130 # define PLATFORM_STACK_SIZE 0x440 131 #endif 132 133 134 #define PLAT_ARM_NSTIMER_FRAME_ID 0 135 136 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 137 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ 138 139 #define PLAT_ARM_NSRAM_BASE 0x06000000 140 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 141 142 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 143 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 144 145 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 146 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 147 148 #define CSS_SGI_DEVICE_BASE (0x20000000) 149 #define CSS_SGI_DEVICE_SIZE (0x20000000) 150 #define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \ 151 CSS_SGI_DEVICE_BASE, \ 152 CSS_SGI_DEVICE_SIZE, \ 153 MT_DEVICE | MT_RW | MT_SECURE) 154 155 #define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n) \ 156 MAP_REGION_FLAT( \ 157 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ 158 ARM_SHARED_RAM_BASE, \ 159 ARM_SHARED_RAM_SIZE, \ 160 MT_NON_CACHEABLE | MT_RW | MT_SECURE \ 161 ) 162 163 #define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \ 164 MAP_REGION_FLAT( \ 165 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ 166 CSS_SGI_DEVICE_BASE, \ 167 CSS_SGI_DEVICE_SIZE, \ 168 MT_DEVICE | MT_RW | MT_SECURE \ 169 ) 170 171 #define SOC_CSS_MAP_DEVICE_REMOTE_CHIP(n) \ 172 MAP_REGION_FLAT( \ 173 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ 174 SOC_CSS_DEVICE_BASE, \ 175 SOC_CSS_DEVICE_SIZE, \ 176 MT_DEVICE | MT_RW | MT_SECURE \ 177 ) 178 179 /* Map the secure region for access from S-EL0 */ 180 #define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \ 181 SOC_CSS_DEVICE_BASE, \ 182 SOC_CSS_DEVICE_SIZE, \ 183 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 184 185 #define PLAT_SP_PRI PLAT_RAS_PRI 186 187 #if SPM_MM && RAS_EXTENSION 188 /* 189 * CPER buffer memory of 128KB is reserved and it is placed adjacent to the 190 * memory shared between EL3 and S-EL0. 191 */ 192 #define CSS_SGI_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 193 PLAT_SP_IMAGE_NS_BUF_SIZE) 194 #define CSS_SGI_SP_CPER_BUF_SIZE ULL(0x20000) 195 #define CSS_SGI_SP_CPER_BUF_MMAP MAP_REGION2( \ 196 CSS_SGI_SP_CPER_BUF_BASE, \ 197 CSS_SGI_SP_CPER_BUF_BASE, \ 198 CSS_SGI_SP_CPER_BUF_SIZE, \ 199 MT_RW_DATA | MT_NS | MT_USER, \ 200 PAGE_SIZE) 201 202 /* 203 * Secure partition stack follows right after the memory space reserved for 204 * CPER buffer memory. 205 */ 206 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 207 PLAT_SP_IMAGE_NS_BUF_SIZE + \ 208 CSS_SGI_SP_CPER_BUF_SIZE) 209 #elif SPM_MM 210 /* 211 * Secure partition stack follows right after the memory region that is shared 212 * between EL3 and S-EL0. 213 */ 214 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 215 PLAT_SP_IMAGE_NS_BUF_SIZE) 216 #endif /* SPM_MM && RAS_EXTENSION */ 217 218 /* Platform ID address */ 219 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 220 #ifndef __ASSEMBLER__ 221 /* SSC_VERSION related accessors */ 222 /* Returns the part number of the platform */ 223 #define GET_SGI_PART_NUM \ 224 GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) 225 /* Returns the configuration number of the platform */ 226 #define GET_SGI_CONFIG_NUM \ 227 GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) 228 #endif /* __ASSEMBLER__ */ 229 230 /******************************************************************************* 231 * Memprotect definitions 232 ******************************************************************************/ 233 /* PSCI memory protect definitions: 234 * This variable is stored in a non-secure flash because some ARM reference 235 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 236 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 237 */ 238 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 239 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 240 241 /*Secure Watchdog Constants */ 242 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 243 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 244 245 /* Number of SCMI channels on the platform */ 246 #define PLAT_ARM_SCMI_CHANNEL_COUNT CSS_SGI_CHIP_COUNT 247 248 /* 249 * Mapping definition of the TrustZone Controller for ARM SGI/RD platforms 250 * where both the DRAM regions are marked for non-secure access. This applies 251 * to multi-chip platforms. 252 */ 253 #define SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n) \ 254 {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \ 255 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \ 256 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 257 {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \ 258 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \ 259 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 260 261 #endif /* SGI_BASE_PLATFORM_DEF_H */ 262