1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Xilinx Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef PLATFORM_CONFIG_H 30 #define PLATFORM_CONFIG_H 31 32 #include <mm/generic_ram_layout.h> 33 34 /* Make stacks aligned to data cache line length */ 35 #define CACHELINE_LEN 64 36 #define STACK_ALIGNMENT CACHELINE_LEN 37 38 #ifdef CFG_WITH_PAGER 39 #error "Pager not supported for zynqmp" 40 #endif 41 42 /* DDR Low area base */ 43 #define DRAM0_BASE 0 44 45 #ifdef ARM64 46 /* DDR High area base is only available when compiling for 64 bits */ 47 #define DRAM1_BASE 0x800000000 48 #endif 49 50 #if defined(PLATFORM_FLAVOR_zc1751_dc1) || \ 51 defined(PLATFORM_FLAVOR_zc1751_dc2) || \ 52 defined(PLATFORM_FLAVOR_zcu102) 53 54 #define GIC_BASE 0xF9010000 55 #define UART0_BASE 0xFF000000 56 #define UART1_BASE 0xFF010000 57 58 #define IT_UART0 53 59 #define IT_UART1 54 60 61 #define UART0_CLK_IN_HZ 100000000 62 #define UART1_CLK_IN_HZ 100000000 63 #define CONSOLE_UART_BASE UART0_BASE 64 #define IT_CONSOLE_UART IT_UART0 65 #define CONSOLE_UART_CLK_IN_HZ UART0_CLK_IN_HZ 66 67 #define GICD_OFFSET 0 68 #define GICC_OFFSET 0x20000 69 70 #elif defined(PLATFORM_FLAVOR_ultra96) 71 72 #define GIC_BASE 0xF9010000 73 #define UART0_BASE 0xFF000000 74 #define UART1_BASE 0xFF010000 75 76 #define IT_UART0 53 77 #define IT_UART1 54 78 79 #define UART0_CLK_IN_HZ 100000000 80 #define UART1_CLK_IN_HZ 100000000 81 #define CONSOLE_UART_BASE UART1_BASE 82 #define IT_CONSOLE_UART IT_UART1 83 #define CONSOLE_UART_CLK_IN_HZ UART1_CLK_IN_HZ 84 85 #define GICD_OFFSET 0 86 #define GICC_OFFSET 0x20000 87 88 #else 89 #error "Unknown platform flavor" 90 #endif 91 92 #define CSUDMA_BASE 0xFFC80000 93 #define CSUDMA_SIZE 0x1000 94 #define CSU_BASE 0xFFCA0000 95 #define CSU_SIZE 0x5038 96 97 #ifdef CFG_TEE_LOAD_ADDR 98 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR 99 #else 100 #define TEE_LOAD_ADDR TEE_RAM_START 101 #endif 102 103 #ifndef UART_BAUDRATE 104 #define UART_BAUDRATE 115200 105 #endif 106 #ifndef CONSOLE_BAUDRATE 107 #define CONSOLE_BAUDRATE UART_BAUDRATE 108 #endif 109 110 /* For virtual platforms where there isn't a clock */ 111 #ifndef CONSOLE_UART_CLK_IN_HZ 112 #define CONSOLE_UART_CLK_IN_HZ 1 113 #endif 114 115 #endif /*PLATFORM_CONFIG_H*/ 116