1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020 Intel Corporation. */
3
4 #ifndef __CXL_H__
5 #define __CXL_H__
6
7 #include <linux/libnvdimm.h>
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/io.h>
11
12 /**
13 * DOC: cxl objects
14 *
15 * The CXL core objects like ports, decoders, and regions are shared
16 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
17 * (port-driver, region-driver, nvdimm object-drivers... etc).
18 */
19
20 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
21 #define CXL_CM_OFFSET 0x1000
22 #define CXL_CM_CAP_HDR_OFFSET 0x0
23 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
24 #define CM_CAP_HDR_CAP_ID 1
25 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
26 #define CM_CAP_HDR_CAP_VERSION 1
27 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)
28 #define CM_CAP_HDR_CACHE_MEM_VERSION 1
29 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)
30 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)
31
32 #define CXL_CM_CAP_CAP_ID_HDM 0x5
33 #define CXL_CM_CAP_CAP_HDM_VERSION 1
34
35 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
36 #define CXL_HDM_DECODER_CAP_OFFSET 0x0
37 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
38 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
39 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET 0x10
40 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET 0x14
41 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET 0x18
42 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET 0x1c
43 #define CXL_HDM_DECODER0_CTRL_OFFSET 0x20
44
cxl_hdm_decoder_count(u32 cap_hdr)45 static inline int cxl_hdm_decoder_count(u32 cap_hdr)
46 {
47 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
48
49 return val ? val * 2 : 1;
50 }
51
52 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
53 #define CXLDEV_CAP_ARRAY_OFFSET 0x0
54 #define CXLDEV_CAP_ARRAY_CAP_ID 0
55 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
56 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
57 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */
58 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)
59 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */
60 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1
61 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2
62 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3
63 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000
64
65 /* CXL 2.0 8.2.8.4 Mailbox Registers */
66 #define CXLDEV_MBOX_CAPS_OFFSET 0x00
67 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)
68 #define CXLDEV_MBOX_CTRL_OFFSET 0x04
69 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0)
70 #define CXLDEV_MBOX_CMD_OFFSET 0x08
71 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
72 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
73 #define CXLDEV_MBOX_STATUS_OFFSET 0x10
74 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
75 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18
76 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
77
78 /*
79 * Using struct_group() allows for per register-block-type helper routines,
80 * without requiring block-type agnostic code to include the prefix.
81 */
82 struct cxl_regs {
83 /*
84 * Common set of CXL Component register block base pointers
85 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
86 */
87 struct_group_tagged(cxl_component_regs, component,
88 void __iomem *hdm_decoder;
89 );
90 /*
91 * Common set of CXL Device register block base pointers
92 * @status: CXL 2.0 8.2.8.3 Device Status Registers
93 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
94 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
95 */
96 struct_group_tagged(cxl_device_regs, device_regs,
97 void __iomem *status, *mbox, *memdev;
98 );
99 };
100
101 struct cxl_reg_map {
102 bool valid;
103 unsigned long offset;
104 unsigned long size;
105 };
106
107 struct cxl_component_reg_map {
108 struct cxl_reg_map hdm_decoder;
109 };
110
111 struct cxl_device_reg_map {
112 struct cxl_reg_map status;
113 struct cxl_reg_map mbox;
114 struct cxl_reg_map memdev;
115 };
116
117 /**
118 * struct cxl_register_map - DVSEC harvested register block mapping parameters
119 * @base: virtual base of the register-block-BAR + @block_offset
120 * @block_offset: offset to start of register block in @barno
121 * @reg_type: see enum cxl_regloc_type
122 * @barno: PCI BAR number containing the register block
123 * @component_map: cxl_reg_map for component registers
124 * @device_map: cxl_reg_maps for device registers
125 */
126 struct cxl_register_map {
127 void __iomem *base;
128 u64 block_offset;
129 u8 reg_type;
130 u8 barno;
131 union {
132 struct cxl_component_reg_map component_map;
133 struct cxl_device_reg_map device_map;
134 };
135 };
136
137 void cxl_probe_component_regs(struct device *dev, void __iomem *base,
138 struct cxl_component_reg_map *map);
139 void cxl_probe_device_regs(struct device *dev, void __iomem *base,
140 struct cxl_device_reg_map *map);
141 int cxl_map_component_regs(struct pci_dev *pdev,
142 struct cxl_component_regs *regs,
143 struct cxl_register_map *map);
144 int cxl_map_device_regs(struct pci_dev *pdev,
145 struct cxl_device_regs *regs,
146 struct cxl_register_map *map);
147
148 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
149 #define CXL_TARGET_STRLEN 20
150
151 /*
152 * cxl_decoder flags that define the type of memory / devices this
153 * decoder supports as well as configuration lock status See "CXL 2.0
154 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details.
155 */
156 #define CXL_DECODER_F_RAM BIT(0)
157 #define CXL_DECODER_F_PMEM BIT(1)
158 #define CXL_DECODER_F_TYPE2 BIT(2)
159 #define CXL_DECODER_F_TYPE3 BIT(3)
160 #define CXL_DECODER_F_LOCK BIT(4)
161 #define CXL_DECODER_F_MASK GENMASK(4, 0)
162
163 enum cxl_decoder_type {
164 CXL_DECODER_ACCELERATOR = 2,
165 CXL_DECODER_EXPANDER = 3,
166 };
167
168 /*
169 * Current specification goes up to 8, double that seems a reasonable
170 * software max for the foreseeable future
171 */
172 #define CXL_DECODER_MAX_INTERLEAVE 16
173
174 /**
175 * struct cxl_decoder - CXL address range decode configuration
176 * @dev: this decoder's device
177 * @id: kernel device name id
178 * @range: address range considered by this decoder
179 * @interleave_ways: number of cxl_dports in this decode
180 * @interleave_granularity: data stride per dport
181 * @target_type: accelerator vs expander (type2 vs type3) selector
182 * @flags: memory type capabilities and locking
183 * @nr_targets: number of elements in @target
184 * @target: active ordered target list in current decoder configuration
185 */
186 struct cxl_decoder {
187 struct device dev;
188 int id;
189 struct range range;
190 int interleave_ways;
191 int interleave_granularity;
192 enum cxl_decoder_type target_type;
193 unsigned long flags;
194 const int nr_targets;
195 struct cxl_dport *target[];
196 };
197
198
199 enum cxl_nvdimm_brige_state {
200 CXL_NVB_NEW,
201 CXL_NVB_DEAD,
202 CXL_NVB_ONLINE,
203 CXL_NVB_OFFLINE,
204 };
205
206 struct cxl_nvdimm_bridge {
207 int id;
208 struct device dev;
209 struct cxl_port *port;
210 struct nvdimm_bus *nvdimm_bus;
211 struct nvdimm_bus_descriptor nd_desc;
212 struct work_struct state_work;
213 enum cxl_nvdimm_brige_state state;
214 };
215
216 struct cxl_nvdimm {
217 struct device dev;
218 struct cxl_memdev *cxlmd;
219 struct nvdimm *nvdimm;
220 };
221
222 struct cxl_walk_context {
223 struct device *dev;
224 struct pci_bus *root;
225 struct cxl_port *port;
226 int error;
227 int count;
228 };
229
230 /**
231 * struct cxl_port - logical collection of upstream port devices and
232 * downstream port devices to construct a CXL memory
233 * decode hierarchy.
234 * @dev: this port's device
235 * @uport: PCI or platform device implementing the upstream port capability
236 * @id: id for port device-name
237 * @dports: cxl_dport instances referenced by decoders
238 * @decoder_ida: allocator for decoder ids
239 * @component_reg_phys: component register capability base address (optional)
240 */
241 struct cxl_port {
242 struct device dev;
243 struct device *uport;
244 int id;
245 struct list_head dports;
246 struct ida decoder_ida;
247 resource_size_t component_reg_phys;
248 };
249
250 /**
251 * struct cxl_dport - CXL downstream port
252 * @dport: PCI bridge or firmware device representing the downstream link
253 * @port_id: unique hardware identifier for dport in decoder target list
254 * @component_reg_phys: downstream port component registers
255 * @port: reference to cxl_port that contains this downstream port
256 * @list: node for a cxl_port's list of cxl_dport instances
257 */
258 struct cxl_dport {
259 struct device *dport;
260 int port_id;
261 resource_size_t component_reg_phys;
262 struct cxl_port *port;
263 struct list_head list;
264 };
265
266 struct cxl_port *to_cxl_port(struct device *dev);
267 struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
268 resource_size_t component_reg_phys,
269 struct cxl_port *parent_port);
270
271 int cxl_add_dport(struct cxl_port *port, struct device *dport, int port_id,
272 resource_size_t component_reg_phys);
273
274 struct cxl_decoder *to_cxl_decoder(struct device *dev);
275 bool is_root_decoder(struct device *dev);
276 struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, int nr_targets);
277 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
278 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
279
280 extern struct bus_type cxl_bus_type;
281
282 struct cxl_driver {
283 const char *name;
284 int (*probe)(struct device *dev);
285 void (*remove)(struct device *dev);
286 struct device_driver drv;
287 int id;
288 };
289
to_cxl_drv(struct device_driver * drv)290 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv)
291 {
292 return container_of(drv, struct cxl_driver, drv);
293 }
294
295 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner,
296 const char *modname);
297 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME)
298 void cxl_driver_unregister(struct cxl_driver *cxl_drv);
299
300 #define CXL_DEVICE_NVDIMM_BRIDGE 1
301 #define CXL_DEVICE_NVDIMM 2
302
303 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
304 #define CXL_MODALIAS_FMT "cxl:t%d"
305
306 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev);
307 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
308 struct cxl_port *port);
309 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
310 bool is_cxl_nvdimm(struct device *dev);
311 int devm_cxl_add_nvdimm(struct device *host, struct cxl_memdev *cxlmd);
312 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_nvdimm *cxl_nvd);
313
314 /*
315 * Unit test builds overrides this to __weak, find the 'strong' version
316 * of these symbols in tools/testing/cxl/.
317 */
318 #ifndef __mock
319 #define __mock static
320 #endif
321 #endif /* __CXL_H__ */
322