1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright 2020 NXP
4  */
5 
6 #ifndef __IMX6_DCP_H__
7 #define __IMX6_DCP_H__
8 
9 /* DCP base address */
10 #ifdef CFG_MX6ULL
11 #define DCP_BASE 0x2280000
12 #endif
13 #if defined(CFG_MX6SL) || defined(CFG_MX6SLL)
14 #define DCP_BASE 0x20FC000
15 #endif
16 
17 /* DCP registers address offset */
18 #define DCP_CTRL	   0x00
19 #define DCP_CTRL_SET	   0x04
20 #define DCP_CTRL_CLR	   0x08
21 #define DCP_STAT	   0x10
22 #define DCP_STAT_CLR	   0x18
23 #define DCP_CHANNELCTRL	   0x20
24 #define DCP_CAPABILITY0	   0x30
25 #define DCP_CAPABILITY1	   0x40
26 #define DCP_CONTEXT	   0x50
27 #define DCP_KEY		   0x60
28 #define DCP_KEYDATA	   0x70
29 #define DCP_PACKET0	   0x80
30 #define DCP_PACKET1	   0x90
31 #define DCP_PACKET2	   0xA0
32 #define DCP_PACKET3	   0xB0
33 #define DCP_PACKET4	   0xC0
34 #define DCP_PACKET5	   0xD0
35 #define DCP_PACKET6	   0xE0
36 #define DCP_CH_N_CMDPTR(n) (0x100 + (n) * 0x40)
37 #define DCP_CH_N_SEMA(n)   (0x110 + (n) * 0x40)
38 #define DCP_CH_N_STAT(n)   (0x120 + (n) * 0x40)
39 #define DCP_CHOCMDPTR	   0x100
40 #define DCP_CH0SEMA	   0x110
41 #define DCP_CH0STAT	   0x120
42 #define DCP_CH1CMDPTR	   0x140
43 #define DCP_CH2CMDPTR	   0x180
44 #define DCP_CH3CMDPTR	   0x1C0
45 
46 /* DCP CHANNELCTRL register configuration */
47 #define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK GENMASK_32(7, 0)
48 #define DCP_STAT_CLEAR			    GENMASK_32(31, 0)
49 #define DCP_CH_STAT_ERROR_MASK		    GENMASK_32(23, 0)
50 
51 /* DCP CTRL register configuration */
52 #define DCP_CTRL_SFTRST			  BIT32(31)
53 #define DCP_CTRL_CLKGATE		  BIT32(30)
54 #define DCP_CTRL_GATHER_RESIDUAL_WRITES	  BIT32(23)
55 #define DCP_CTRL_ENABLE_CONTEXT_CACHING	  BIT32(22)
56 #define DCP_CTRL_ENABLE_CONTEXT_SWITCHING BIT32(21)
57 #define DCP_CTRL_CH3_INTERRUPT_ENABLE	  BIT32(3)
58 #define DCP_CTRL_CH2_INTERRUPT_ENABLE	  BIT32(2)
59 #define DCP_CTRL_CH1_INTERRUPT_ENABLE	  BIT32(1)
60 #define DCP_CTRL_CH0_INTERRUPT_ENABLE	  BIT32(0)
61 
62 /* Work Packet control0 configuration */
63 #define DCP_CONTROL0_OUTPUT_WORDSWAP  BIT32(23)
64 #define DCP_CONTROL0_OUTPUT_BYTESWAP  BIT32(22)
65 #define DCP_CONTROL0_INPUT_WORDSWAP   BIT32(21)
66 #define DCP_CONTROL0_INPUT_BYTESWAP   BIT32(20)
67 #define DCP_CONTROL0_KEY_WORDSWAP     BIT32(19)
68 #define DCP_CONTROL0_KEY_BYTESWA      BIT32(18)
69 #define DCP_CONTROL0_TEST_SEMA_IRQ    BIT32(17)
70 #define DCP_CONTROL0_CONSTANT_FILL    BIT32(16)
71 #define DCP_CONTROL0_HASH_OUTPUT      BIT32(15)
72 #define DCP_CONTROL0_HASH_CHECK	      BIT32(14)
73 #define DCP_CONTROL0_HASH_TERM	      BIT32(13)
74 #define DCP_CONTROL0_HASH_INIT	      BIT32(12)
75 #define DCP_CONTROL0_PAYLOAD_KEY      BIT32(11)
76 #define DCP_CONTROL0_OTP_KEY	      BIT32(10)
77 #define DCP_CONTROL0_CIPHER_INIT      BIT32(9)
78 #define DCP_CONTROL0_CIPHER_ENCRYPT   BIT32(8)
79 #define DCP_CONTROL0_ENABLE_BLIT      BIT32(7)
80 #define DCP_CONTROL0_ENABLE_HASH      BIT32(6)
81 #define DCP_CONTROL0_ENABLE_CIPHER    BIT32(5)
82 #define DCP_CONTROL0_ENABLE_MEMCOPY   BIT32(4)
83 #define DCP_CONTROL0_CHAIN_CONTINUOUS BIT32(3)
84 #define DCP_CONTROL0_CHAIN	      BIT32(2)
85 #define DCP_CONTROL0_DECR_SEMAPHORE   BIT32(1)
86 #define DCP_CONTROL0_INTERRUPT_ENABLE BIT32(0)
87 
88 /* Work Packet control1 configuration */
89 #define DCP_CONTROL1_HASH_SELECT_SHA256	   SHIFT_U32(2, 16)
90 #define DCP_CONTROL1_HASH_SELECT_CRC32	   BIT32(16)
91 #define DCP_CONTROL1_HASH_SELECT_SHA1	   SHIFT_U32(0, 16)
92 #define DCP_CONTROL1_CIPHER_MODE_CBC	   BIT32(4)
93 #define DCP_CONTROL1_CIPHER_MODE_ECB	   SHIFT_U32(0, 4)
94 #define DCP_CONTROL1_CIPHER_SELECT_AES128  0
95 #define DCP_CONTROL1_KEY_SELECT_OTP_CRYPTO SHIFT_U32(0xfe, 8)
96 
97 #endif /* __IMX6_DCP_H__ */
98