1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AM654: DDRSS Register definitions and structures. 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 6 * Lokesh Vutla <lokeshvutla@ti.com> 7 * 8 */ 9 10 #ifndef __K3_AM654_DDRSS_H 11 #define __K3_AM654_DDRSS_H 12 13 /* DDRSS subsystem wrapper logic registers */ 14 #include <linux/bitops.h> 15 #define DDRSS_SS_ID_REV_REG 0x00000000 16 #define DDRSS_SS_CTL_REG 0x00000004 17 #define DDRSS_V2H_CTL_REG 0x00000020 18 19 #define SS_CTL_REG_CTL_ARST_SHIFT 0x0 20 #define SS_CTL_REG_CTL_ARST_MASK BIT(SS_CTL_REG_CTL_ARST_SHIFT) 21 22 /* DDRSS controller configuration registers */ 23 #define DDRSS_DDRCTL_MSTR 0x00000000 24 #define DDRSS_DDRCTL_STAT 0x00000004 25 #define DDRSS_DDRCTL_MRCTRL0 0x00000010 26 #define DDRSS_DDRCTL_MRCTRL1 0x00000014 27 #define DDRSS_DDRCTL_MRSTAT 0x00000018 28 #define DDRSS_DDRCTL_MRCTRL2 0x0000001C 29 #define DDRSS_DDRCTL_DERATEEN 0x00000020 30 #define DDRSS_DDRCTL_DERATEINT 0x00000024 31 #define DDRSS_DDRCTL_MSTR2 0x00000028 32 #define DDRSS_DDRCTL_PWRCTL 0x00000030 33 #define DDRSS_DDRCTL_PWRTMG 0x00000034 34 #define DDRSS_DDRCTL_HWLPCTL 0x00000038 35 #define DDRSS_DDRCTL_RFSHCTL0 0x00000050 36 #define DDRSS_DDRCTL_RFSHCTL1 0x00000054 37 #define DDRSS_DDRCTL_RFSHCTL2 0x00000058 38 #define DDRSS_DDRCTL_RFSHCTL3 0x00000060 39 #define DDRSS_DDRCTL_RFSHTMG 0x00000064 40 #define DDRSS_DDRCTL_ECCCFG0 0x00000070 41 #define DDRSS_DDRCTL_ECCCFG1 0x00000074 42 #define DDRSS_DDRCTL_ECCSTAT 0x00000078 43 #define DDRSS_DDRCTL_ECCCLR 0x0000007C 44 #define DDRSS_DDRCTL_ECCERRCNT 0x00000080 45 #define DDRSS_DDRCTL_ECCCADDR0 0x00000084 46 #define DDRSS_DDRCTL_ECCCADDR1 0x00000088 47 #define DDRSS_DDRCTL_ECCCSYN0 0x0000008C 48 #define DDRSS_DDRCTL_ECCCSYN2 0x00000094 49 #define DDRSS_DDRCTL_ECCBITMASK0 0x00000098 50 #define DDRSS_DDRCTL_ECCBITMASK2 0x000000A0 51 #define DDRSS_DDRCTL_ECCUADDR0 0x000000A4 52 #define DDRSS_DDRCTL_ECCUADDR1 0x000000A8 53 #define DDRSS_DDRCTL_ECCUSYN0 0x000000AC 54 #define DDRSS_DDRCTL_ECCUSYN2 0x000000B4 55 #define DDRSS_DDRCTL_ECCPOISONADDR0 0x000000B8 56 #define DDRSS_DDRCTL_ECCPOISONADDR1 0x000000BC 57 #define DDRSS_DDRCTL_CRCPARCTL0 0x000000C0 58 #define DDRSS_DDRCTL_CRCPARCTL1 0x000000C4 59 #define DDRSS_DDRCTL_CRCPARCTL2 0x000000C8 60 #define DDRSS_DDRCTL_CRCPARSTAT 0x000000CC 61 #define DDRSS_DDRCTL_INIT0 0x000000D0 62 #define DDRSS_DDRCTL_INIT1 0x000000D4 63 #define DDRSS_DDRCTL_INIT2 0x000000D8 64 #define DDRSS_DDRCTL_INIT3 0x000000DC 65 #define DDRSS_DDRCTL_INIT4 0x000000E0 66 #define DDRSS_DDRCTL_INIT5 0x000000E4 67 #define DDRSS_DDRCTL_INIT6 0x000000E8 68 #define DDRSS_DDRCTL_INIT7 0x000000EC 69 #define DDRSS_DDRCTL_DIMMCTL 0x000000F0 70 #define DDRSS_DDRCTL_RANKCTL 0x000000F4 71 #define DDRSS_DDRCTL_DRAMTMG0 0x00000100 72 #define DDRSS_DDRCTL_DRAMTMG1 0x00000104 73 #define DDRSS_DDRCTL_DRAMTMG2 0x00000108 74 #define DDRSS_DDRCTL_DRAMTMG3 0x0000010C 75 #define DDRSS_DDRCTL_DRAMTMG4 0x00000110 76 #define DDRSS_DDRCTL_DRAMTMG5 0x00000114 77 #define DDRSS_DDRCTL_DRAMTMG6 0x00000118 78 #define DDRSS_DDRCTL_DRAMTMG7 0x0000011C 79 #define DDRSS_DDRCTL_DRAMTMG8 0x00000120 80 #define DDRSS_DDRCTL_DRAMTMG9 0x00000124 81 #define DDRSS_DDRCTL_DRAMTMG10 0x00000128 82 #define DDRSS_DDRCTL_DRAMTMG11 0x0000012C 83 #define DDRSS_DDRCTL_DRAMTMG12 0x00000130 84 #define DDRSS_DDRCTL_DRAMTMG13 0x00000134 85 #define DDRSS_DDRCTL_DRAMTMG14 0x00000138 86 #define DDRSS_DDRCTL_DRAMTMG15 0x0000013C 87 #define DDRSS_DDRCTL_DRAMTMG17 0x00000144 88 #define DDRSS_DDRCTL_ZQCTL0 0x00000180 89 #define DDRSS_DDRCTL_ZQCTL1 0x00000184 90 #define DDRSS_DDRCTL_ZQCTL2 0x00000188 91 #define DDRSS_DDRCTL_ZQSTAT 0x0000018C 92 #define DDRSS_DDRCTL_DFITMG0 0x00000190 93 #define DDRSS_DDRCTL_DFITMG1 0x00000194 94 #define DDRSS_DDRCTL_DFILPCFG0 0x00000198 95 #define DDRSS_DDRCTL_DFILPCFG1 0x0000019C 96 #define DDRSS_DDRCTL_DFIUPD0 0x000001A0 97 #define DDRSS_DDRCTL_DFIUPD1 0x000001A4 98 #define DDRSS_DDRCTL_DFIUPD2 0x000001A8 99 #define DDRSS_DDRCTL_DFIMISC 0x000001B0 100 #define DDRSS_DDRCTL_DFITMG2 0x000001B4 101 #define DDRSS_DDRCTL_DFITMG3 0x000001B8 102 #define DDRSS_DDRCTL_DFISTAT 0x000001BC 103 #define DDRSS_DDRCTL_DBICTL 0x000001C0 104 #define DDRSS_DDRCTL_DFIPHYMSTR 0x000001C4 105 #define DDRSS_DDRCTL_ADDRMAP0 0x00000200 106 #define DDRSS_DDRCTL_ADDRMAP1 0x00000204 107 #define DDRSS_DDRCTL_ADDRMAP2 0x00000208 108 #define DDRSS_DDRCTL_ADDRMAP3 0x0000020C 109 #define DDRSS_DDRCTL_ADDRMAP4 0x00000210 110 #define DDRSS_DDRCTL_ADDRMAP5 0x00000214 111 #define DDRSS_DDRCTL_ADDRMAP6 0x00000218 112 #define DDRSS_DDRCTL_ADDRMAP7 0x0000021C 113 #define DDRSS_DDRCTL_ADDRMAP8 0x00000220 114 #define DDRSS_DDRCTL_ADDRMAP9 0x00000224 115 #define DDRSS_DDRCTL_ADDRMAP10 0x00000228 116 #define DDRSS_DDRCTL_ADDRMAP11 0x0000022C 117 #define DDRSS_DDRCTL_ODTCFG 0x00000240 118 #define DDRSS_DDRCTL_ODTMAP 0x00000244 119 #define DDRSS_DDRCTL_SCHED 0x00000250 120 #define DDRSS_DDRCTL_SCHED1 0x00000254 121 #define DDRSS_DDRCTL_PERFHPR1 0x0000025C 122 #define DDRSS_DDRCTL_PERFLPR1 0x00000264 123 #define DDRSS_DDRCTL_PERFWR1 0x0000026C 124 #define DDRSS_DDRCTL_DQMAP0 0x00000280 125 #define DDRSS_DDRCTL_DQMAP1 0x00000284 126 #define DDRSS_DDRCTL_DQMAP4 0x00000290 127 #define DDRSS_DDRCTL_DQMAP5 0x00000294 128 #define DDRSS_DDRCTL_DBG0 0x00000300 129 #define DDRSS_DDRCTL_DBG1 0x00000304 130 #define DDRSS_DDRCTL_DBGCAM 0x00000308 131 #define DDRSS_DDRCTL_DBGCMD 0x0000030C 132 #define DDRSS_DDRCTL_DBGSTAT 0x00000310 133 #define DDRSS_DDRCTL_SWCTL 0x00000320 134 #define DDRSS_DDRCTL_SWSTAT 0x00000324 135 #define DDRSS_DDRCTL_ADVECCINDEX 0x00000374 136 #define DDRSS_DDRCTL_ECCPOISONPAT0 0x0000037C 137 #define DDRSS_DDRCTL_ECCPOISONPAT2 0x00000384 138 #define DDRSS_DDRCTL_CAPARPOISONCTL 0x000003A0 139 #define DDRSS_DDRCTL_CAPARPOISONSTAT 0x000003A4 140 #define DDRSS_DDRCTL_DERATEEN_SHDW 0x00002020 141 #define DDRSS_DDRCTL_DERATEINT_SHDW 0x00002024 142 #define DDRSS_DDRCTL_RFSHCTL0_SHDW 0x00002050 143 #define DDRSS_DDRCTL_RFSHTMG_SHDW 0x00002064 144 #define DDRSS_DDRCTL_INIT3_SHDW 0x000020DC 145 #define DDRSS_DDRCTL_INIT4_SHDW 0x000020E0 146 #define DDRSS_DDRCTL_INIT6_SHDW 0x000020E8 147 #define DDRSS_DDRCTL_INIT7_SHDW 0x000020EC 148 #define DDRSS_DDRCTL_DRAMTMG0_SHDW 0x00002100 149 #define DDRSS_DDRCTL_DRAMTMG1_SHDW 0x00002104 150 #define DDRSS_DDRCTL_DRAMTMG2_SHDW 0x00002108 151 #define DDRSS_DDRCTL_DRAMTMG3_SHDW 0x0000210C 152 #define DDRSS_DDRCTL_DRAMTMG4_SHDW 0x00002110 153 #define DDRSS_DDRCTL_DRAMTMG5_SHDW 0x00002114 154 #define DDRSS_DDRCTL_DRAMTMG6_SHDW 0x00002118 155 #define DDRSS_DDRCTL_DRAMTMG7_SHDW 0x0000211C 156 #define DDRSS_DDRCTL_DRAMTMG8_SHDW 0x00002120 157 #define DDRSS_DDRCTL_DRAMTMG9_SHDW 0x00002124 158 #define DDRSS_DDRCTL_DRAMTMG10_SHDW 0x00002128 159 #define DDRSS_DDRCTL_DRAMTMG11_SHDW 0x0000212C 160 #define DDRSS_DDRCTL_DRAMTMG12_SHDW 0x00002130 161 #define DDRSS_DDRCTL_DRAMTMG13_SHDW 0x00002134 162 #define DDRSS_DDRCTL_DRAMTMG14_SHDW 0x00002138 163 #define DDRSS_DDRCTL_DRAMTMG15_SHDW 0x0000213C 164 #define DDRSS_DDRCTL_ZQCTL0_SHDW 0x00002180 165 #define DDRSS_DDRCTL_DFITMG0_SHDW 0x00002190 166 #define DDRSS_DDRCTL_DFITMG1_SHDW 0x00002194 167 #define DDRSS_DDRCTL_DFITMG2_SHDW 0x000021B4 168 #define DDRSS_DDRCTL_DFITMG3_SHDW 0x000021B8 169 #define DDRSS_DDRCTL_ODTCFG_SHDW 0x00002240 170 171 #define MSTR_DDR_TYPE_MASK GENMASK(5, 0) 172 #define DDR_TYPE_LPDDR4 0x20 173 #define DDR_TYPE_DDR4 0x10 174 #define DDR_TYPE_DDR3 0x1 175 176 #define DDR3_STAT_MODE_MASK GENMASK(1, 0) 177 #define DDR4_STAT_MODE_MASK GENMASK(2, 0) 178 #define DDR_MODE_NORMAL 0x1 179 180 /* DDRSS PHY configuration registers */ 181 #define DDRSS_DDRPHY_RIDR 0x00000000 182 #define DDRSS_DDRPHY_PIR 0x00000004 183 #define DDRSS_DDRPHY_PGCR0 0x00000010 184 #define DDRSS_DDRPHY_PGCR1 0x00000014 185 #define DDRSS_DDRPHY_PGCR2 0x00000018 186 #define DDRSS_DDRPHY_PGCR3 0x0000001C 187 #define DDRSS_DDRPHY_PGCR4 0x00000020 188 #define DDRSS_DDRPHY_PGCR5 0x00000024 189 #define DDRSS_DDRPHY_PGCR6 0x00000028 190 #define DDRSS_DDRPHY_PGCR7 0x0000002C 191 #define DDRSS_DDRPHY_PGSR0 0x00000030 192 #define DDRSS_DDRPHY_PGSR1 0x00000034 193 #define DDRSS_DDRPHY_PGSR2 0x00000038 194 #define DDRSS_DDRPHY_PTR0 0x00000040 195 #define DDRSS_DDRPHY_PTR1 0x00000044 196 #define DDRSS_DDRPHY_PTR2 0x00000048 197 #define DDRSS_DDRPHY_PTR3 0x0000004C 198 #define DDRSS_DDRPHY_PTR4 0x00000050 199 #define DDRSS_DDRPHY_PTR5 0x00000054 200 #define DDRSS_DDRPHY_PTR6 0x00000058 201 #define DDRSS_DDRPHY_PLLCR0 0x00000068 202 #define DDRSS_DDRPHY_PLLCR1 0x0000006C 203 #define DDRSS_DDRPHY_PLLCR2 0x00000070 204 #define DDRSS_DDRPHY_PLLCR3 0x00000074 205 #define DDRSS_DDRPHY_PLLCR4 0x00000078 206 #define DDRSS_DDRPHY_PLLCR5 0x0000007C 207 #define DDRSS_DDRPHY_DXCCR 0x00000088 208 #define DDRSS_DDRPHY_DSGCR 0x00000090 209 #define DDRSS_DDRPHY_ODTCR 0x00000098 210 #define DDRSS_DDRPHY_AACR 0x000000A0 211 #define DDRSS_DDRPHY_GPR0 0x000000C0 212 #define DDRSS_DDRPHY_GPR1 0x000000C4 213 #define DDRSS_DDRPHY_DCR 0x00000100 214 #define DDRSS_DDRPHY_DTPR0 0x00000110 215 #define DDRSS_DDRPHY_DTPR1 0x00000114 216 #define DDRSS_DDRPHY_DTPR2 0x00000118 217 #define DDRSS_DDRPHY_DTPR3 0x0000011C 218 #define DDRSS_DDRPHY_DTPR4 0x00000120 219 #define DDRSS_DDRPHY_DTPR5 0x00000124 220 #define DDRSS_DDRPHY_DTPR6 0x00000128 221 #define DDRSS_DDRPHY_RDIMMGCR0 0x00000140 222 #define DDRSS_DDRPHY_RDIMMGCR1 0x00000144 223 #define DDRSS_DDRPHY_RDIMMGCR2 0x00000148 224 #define DDRSS_DDRPHY_RDIMMCR0 0x00000150 225 #define DDRSS_DDRPHY_RDIMMCR1 0x00000154 226 #define DDRSS_DDRPHY_RDIMMCR2 0x00000158 227 #define DDRSS_DDRPHY_RDIMMCR3 0x0000015C 228 #define DDRSS_DDRPHY_RDIMMCR4 0x00000160 229 #define DDRSS_DDRPHY_SCHCR0 0x00000168 230 #define DDRSS_DDRPHY_SCHCR1 0x0000016C 231 #define DDRSS_DDRPHY_MR0 0x00000180 232 #define DDRSS_DDRPHY_MR1 0x00000184 233 #define DDRSS_DDRPHY_MR2 0x00000188 234 #define DDRSS_DDRPHY_MR3 0x0000018C 235 #define DDRSS_DDRPHY_MR4 0x00000190 236 #define DDRSS_DDRPHY_MR5 0x00000194 237 #define DDRSS_DDRPHY_MR6 0x00000198 238 #define DDRSS_DDRPHY_MR7 0x0000019C 239 #define DDRSS_DDRPHY_MR11 0x000001AC 240 #define DDRSS_DDRPHY_MR12 0x000001B0 241 #define DDRSS_DDRPHY_MR13 0x000001B4 242 #define DDRSS_DDRPHY_MR14 0x000001B8 243 #define DDRSS_DDRPHY_MR22 0x000001D8 244 #define DDRSS_DDRPHY_DTCR0 0x00000200 245 #define DDRSS_DDRPHY_DTCR1 0x00000204 246 #define DDRSS_DDRPHY_DTAR0 0x00000208 247 #define DDRSS_DDRPHY_DTAR1 0x0000020C 248 #define DDRSS_DDRPHY_DTAR2 0x00000210 249 #define DDRSS_DDRPHY_DTDR0 0x00000218 250 #define DDRSS_DDRPHY_DTDR1 0x0000021C 251 #define DDRSS_DDRPHY_DTEDR0 0x00000230 252 #define DDRSS_DDRPHY_DTEDR1 0x00000234 253 #define DDRSS_DDRPHY_DTEDR2 0x00000238 254 #define DDRSS_DDRPHY_VTDR 0x0000023C 255 #define DDRSS_DDRPHY_CATR0 0x00000240 256 #define DDRSS_DDRPHY_CATR1 0x00000244 257 #define DDRSS_DDRPHY_PGCR8 0x00000248 258 #define DDRSS_DDRPHY_DQSDR0 0x00000250 259 #define DDRSS_DDRPHY_DQSDR1 0x00000254 260 #define DDRSS_DDRPHY_DQSDR2 0x00000258 261 #define DDRSS_DDRPHY_DCUAR 0x00000300 262 #define DDRSS_DDRPHY_DCUDR 0x00000304 263 #define DDRSS_DDRPHY_DCURR 0x00000308 264 #define DDRSS_DDRPHY_DCULR 0x0000030C 265 #define DDRSS_DDRPHY_DCUGCR 0x00000310 266 #define DDRSS_DDRPHY_DCUTPR 0x00000314 267 #define DDRSS_DDRPHY_DCUSR0 0x00000318 268 #define DDRSS_DDRPHY_DCUSR1 0x0000031C 269 #define DDRSS_DDRPHY_BISTRR 0x00000400 270 #define DDRSS_DDRPHY_BISTWCR 0x00000404 271 #define DDRSS_DDRPHY_BISTMSKR0 0x00000408 272 #define DDRSS_DDRPHY_BISTMSKR1 0x0000040C 273 #define DDRSS_DDRPHY_BISTMSKR2 0x00000410 274 #define DDRSS_DDRPHY_BISTLSR 0x00000414 275 #define DDRSS_DDRPHY_BISTAR0 0x00000418 276 #define DDRSS_DDRPHY_BISTAR1 0x0000041C 277 #define DDRSS_DDRPHY_BISTAR2 0x00000420 278 #define DDRSS_DDRPHY_BISTAR3 0x00000424 279 #define DDRSS_DDRPHY_BISTAR4 0x00000428 280 #define DDRSS_DDRPHY_BISTUDPR 0x0000042C 281 #define DDRSS_DDRPHY_BISTGSR 0x00000430 282 #define DDRSS_DDRPHY_BISTWER0 0x00000434 283 #define DDRSS_DDRPHY_BISTWER1 0x00000438 284 #define DDRSS_DDRPHY_BISTBER0 0x0000043C 285 #define DDRSS_DDRPHY_BISTBER1 0x00000440 286 #define DDRSS_DDRPHY_BISTBER2 0x00000444 287 #define DDRSS_DDRPHY_BISTBER3 0x00000448 288 #define DDRSS_DDRPHY_BISTBER4 0x0000044C 289 #define DDRSS_DDRPHY_BISTWCSR 0x00000450 290 #define DDRSS_DDRPHY_BISTFWR0 0x00000454 291 #define DDRSS_DDRPHY_BISTFWR1 0x00000458 292 #define DDRSS_DDRPHY_BISTFWR2 0x0000045C 293 #define DDRSS_DDRPHY_BISTBER5 0x00000460 294 #define DDRSS_DDRPHY_RANKIDR 0x000004DC 295 #define DDRSS_DDRPHY_RIOCR0 0x000004E0 296 #define DDRSS_DDRPHY_RIOCR1 0x000004E4 297 #define DDRSS_DDRPHY_RIOCR2 0x000004E8 298 #define DDRSS_DDRPHY_RIOCR3 0x000004EC 299 #define DDRSS_DDRPHY_RIOCR4 0x000004F0 300 #define DDRSS_DDRPHY_RIOCR5 0x000004F4 301 #define DDRSS_DDRPHY_ACIOCR0 0x00000500 302 #define DDRSS_DDRPHY_ACIOCR1 0x00000504 303 #define DDRSS_DDRPHY_ACIOCR2 0x00000508 304 #define DDRSS_DDRPHY_ACIOCR3 0x0000050C 305 #define DDRSS_DDRPHY_ACIOCR4 0x00000510 306 #define DDRSS_DDRPHY_ACIOCR5 0x00000514 307 #define DDRSS_DDRPHY_IOVCR0 0x00000520 308 #define DDRSS_DDRPHY_IOVCR1 0x00000524 309 #define DDRSS_DDRPHY_VTCR0 0x00000528 310 #define DDRSS_DDRPHY_VTCR1 0x0000052C 311 #define DDRSS_DDRPHY_ACBDLR0 0x00000540 312 #define DDRSS_DDRPHY_ACBDLR1 0x00000544 313 #define DDRSS_DDRPHY_ACBDLR2 0x00000548 314 #define DDRSS_DDRPHY_ACBDLR3 0x0000054C 315 #define DDRSS_DDRPHY_ACBDLR4 0x00000550 316 #define DDRSS_DDRPHY_ACBDLR5 0x00000554 317 #define DDRSS_DDRPHY_ACBDLR6 0x00000558 318 #define DDRSS_DDRPHY_ACBDLR7 0x0000055C 319 #define DDRSS_DDRPHY_ACBDLR8 0x00000560 320 #define DDRSS_DDRPHY_ACBDLR9 0x00000564 321 #define DDRSS_DDRPHY_ACBDLR10 0x00000568 322 #define DDRSS_DDRPHY_ACBDLR11 0x0000056C 323 #define DDRSS_DDRPHY_ACBDLR12 0x00000570 324 #define DDRSS_DDRPHY_ACBDLR13 0x00000574 325 #define DDRSS_DDRPHY_ACBDLR14 0x00000578 326 #define DDRSS_DDRPHY_ACBDLR15 0x0000057C 327 #define DDRSS_DDRPHY_ACBDLR16 0x00000580 328 #define DDRSS_DDRPHY_ACLCDLR 0x00000584 329 #define DDRSS_DDRPHY_ACMDLR0 0x000005A0 330 #define DDRSS_DDRPHY_ACMDLR1 0x000005A4 331 #define DDRSS_DDRPHY_ZQCR 0x00000680 332 #define DDRSS_DDRPHY_ZQ0PR0 0x00000684 333 #define DDRSS_DDRPHY_ZQ0PR1 0x00000688 334 #define DDRSS_DDRPHY_ZQ0DR0 0x0000068C 335 #define DDRSS_DDRPHY_ZQ0DR1 0x00000690 336 #define DDRSS_DDRPHY_ZQ0OR0 0x00000694 337 #define DDRSS_DDRPHY_ZQ0OR1 0x00000698 338 #define DDRSS_DDRPHY_ZQ0SR 0x0000069C 339 #define DDRSS_DDRPHY_ZQ1PR0 0x000006A4 340 #define DDRSS_DDRPHY_ZQ1PR1 0x000006A8 341 #define DDRSS_DDRPHY_ZQ1DR0 0x000006AC 342 #define DDRSS_DDRPHY_ZQ1DR1 0x000006B0 343 #define DDRSS_DDRPHY_ZQ1OR0 0x000006B4 344 #define DDRSS_DDRPHY_ZQ1OR1 0x000006B8 345 #define DDRSS_DDRPHY_ZQ1SR 0x000006BC 346 #define DDRSS_DDRPHY_ZQ2PR0 0x000006C4 347 #define DDRSS_DDRPHY_ZQ2PR1 0x000006C8 348 #define DDRSS_DDRPHY_ZQ2DR0 0x000006CC 349 #define DDRSS_DDRPHY_ZQ2DR1 0x000006D0 350 #define DDRSS_DDRPHY_ZQ2OR0 0x000006D4 351 #define DDRSS_DDRPHY_ZQ2OR1 0x000006D8 352 #define DDRSS_DDRPHY_ZQ2SR 0x000006DC 353 #define DDRSS_DDRPHY_ZQ3PR0 0x000006E4 354 #define DDRSS_DDRPHY_ZQ3PR1 0x000006E8 355 #define DDRSS_DDRPHY_ZQ3DR0 0x000006EC 356 #define DDRSS_DDRPHY_ZQ3DR1 0x000006F0 357 #define DDRSS_DDRPHY_ZQ3OR0 0x000006F4 358 #define DDRSS_DDRPHY_ZQ3OR1 0x000006F8 359 #define DDRSS_DDRPHY_ZQ3SR 0x000006FC 360 #define DDRSS_DDRPHY_DX0GCR0 0x00000700 361 #define DDRSS_DDRPHY_DX0GCR1 0x00000704 362 #define DDRSS_DDRPHY_DX0GCR2 0x00000708 363 #define DDRSS_DDRPHY_DX0GCR3 0x0000070C 364 #define DDRSS_DDRPHY_DX0GCR4 0x00000710 365 #define DDRSS_DDRPHY_DX0GCR5 0x00000714 366 #define DDRSS_DDRPHY_DX0GCR6 0x00000718 367 #define DDRSS_DDRPHY_DX0GCR7 0x0000071C 368 #define DDRSS_DDRPHY_DX0GCR8 0x00000720 369 #define DDRSS_DDRPHY_DX0GCR9 0x00000724 370 #define DDRSS_DDRPHY_DX0DQMAP0 0x00000728 371 #define DDRSS_DDRPHY_DX0DQMAP1 0x0000072C 372 #define DDRSS_DDRPHY_DX0BDLR0 0x00000740 373 #define DDRSS_DDRPHY_DX0BDLR1 0x00000744 374 #define DDRSS_DDRPHY_DX0BDLR2 0x00000748 375 #define DDRSS_DDRPHY_DX0BDLR3 0x00000750 376 #define DDRSS_DDRPHY_DX0BDLR4 0x00000754 377 #define DDRSS_DDRPHY_DX0BDLR5 0x00000758 378 #define DDRSS_DDRPHY_DX0BDLR6 0x00000760 379 #define DDRSS_DDRPHY_DX0BDLR7 0x00000764 380 #define DDRSS_DDRPHY_DX0BDLR8 0x00000768 381 #define DDRSS_DDRPHY_DX0BDLR9 0x0000076C 382 #define DDRSS_DDRPHY_DX0LCDLR0 0x00000780 383 #define DDRSS_DDRPHY_DX0LCDLR1 0x00000784 384 #define DDRSS_DDRPHY_DX0LCDLR2 0x00000788 385 #define DDRSS_DDRPHY_DX0LCDLR3 0x0000078C 386 #define DDRSS_DDRPHY_DX0LCDLR4 0x00000790 387 #define DDRSS_DDRPHY_DX0LCDLR5 0x00000794 388 #define DDRSS_DDRPHY_DX0MDLR0 0x000007A0 389 #define DDRSS_DDRPHY_DX0MDLR1 0x000007A4 390 #define DDRSS_DDRPHY_DX0GTR0 0x000007C0 391 #define DDRSS_DDRPHY_DX0RSR0 0x000007D0 392 #define DDRSS_DDRPHY_DX0RSR1 0x000007D4 393 #define DDRSS_DDRPHY_DX0RSR2 0x000007D8 394 #define DDRSS_DDRPHY_DX0RSR3 0x000007DC 395 #define DDRSS_DDRPHY_DX0GSR0 0x000007E0 396 #define DDRSS_DDRPHY_DX0GSR1 0x000007E4 397 #define DDRSS_DDRPHY_DX0GSR2 0x000007E8 398 #define DDRSS_DDRPHY_DX0GSR3 0x000007EC 399 #define DDRSS_DDRPHY_DX0GSR4 0x000007F0 400 #define DDRSS_DDRPHY_DX0GSR5 0x000007F4 401 #define DDRSS_DDRPHY_DX0GSR6 0x000007F8 402 #define DDRSS_DDRPHY_DX1GCR0 0x00000800 403 #define DDRSS_DDRPHY_DX1GCR1 0x00000804 404 #define DDRSS_DDRPHY_DX1GCR2 0x00000808 405 #define DDRSS_DDRPHY_DX1GCR3 0x0000080C 406 #define DDRSS_DDRPHY_DX1GCR4 0x00000810 407 #define DDRSS_DDRPHY_DX1GCR5 0x00000814 408 #define DDRSS_DDRPHY_DX1GCR6 0x00000818 409 #define DDRSS_DDRPHY_DX1GCR7 0x0000081C 410 #define DDRSS_DDRPHY_DX1GCR8 0x00000820 411 #define DDRSS_DDRPHY_DX1GCR9 0x00000824 412 #define DDRSS_DDRPHY_DX1DQMAP0 0x00000828 413 #define DDRSS_DDRPHY_DX1DQMAP1 0x0000082C 414 #define DDRSS_DDRPHY_DX1BDLR0 0x00000840 415 #define DDRSS_DDRPHY_DX1BDLR1 0x00000844 416 #define DDRSS_DDRPHY_DX1BDLR2 0x00000848 417 #define DDRSS_DDRPHY_DX1BDLR3 0x00000850 418 #define DDRSS_DDRPHY_DX1BDLR4 0x00000854 419 #define DDRSS_DDRPHY_DX1BDLR5 0x00000858 420 #define DDRSS_DDRPHY_DX1BDLR6 0x00000860 421 #define DDRSS_DDRPHY_DX1BDLR7 0x00000864 422 #define DDRSS_DDRPHY_DX1BDLR8 0x00000868 423 #define DDRSS_DDRPHY_DX1BDLR9 0x0000086C 424 #define DDRSS_DDRPHY_DX1LCDLR0 0x00000880 425 #define DDRSS_DDRPHY_DX1LCDLR1 0x00000884 426 #define DDRSS_DDRPHY_DX1LCDLR2 0x00000888 427 #define DDRSS_DDRPHY_DX1LCDLR3 0x0000088C 428 #define DDRSS_DDRPHY_DX1LCDLR4 0x00000890 429 #define DDRSS_DDRPHY_DX1LCDLR5 0x00000894 430 #define DDRSS_DDRPHY_DX1MDLR0 0x000008A0 431 #define DDRSS_DDRPHY_DX1MDLR1 0x000008A4 432 #define DDRSS_DDRPHY_DX1GTR0 0x000008C0 433 #define DDRSS_DDRPHY_DX1RSR0 0x000008D0 434 #define DDRSS_DDRPHY_DX1RSR1 0x000008D4 435 #define DDRSS_DDRPHY_DX1RSR2 0x000008D8 436 #define DDRSS_DDRPHY_DX1RSR3 0x000008DC 437 #define DDRSS_DDRPHY_DX1GSR0 0x000008E0 438 #define DDRSS_DDRPHY_DX1GSR1 0x000008E4 439 #define DDRSS_DDRPHY_DX1GSR2 0x000008E8 440 #define DDRSS_DDRPHY_DX1GSR3 0x000008EC 441 #define DDRSS_DDRPHY_DX1GSR4 0x000008F0 442 #define DDRSS_DDRPHY_DX1GSR5 0x000008F4 443 #define DDRSS_DDRPHY_DX1GSR6 0x000008F8 444 #define DDRSS_DDRPHY_DX2GCR0 0x00000900 445 #define DDRSS_DDRPHY_DX2GCR1 0x00000904 446 #define DDRSS_DDRPHY_DX2GCR2 0x00000908 447 #define DDRSS_DDRPHY_DX2GCR3 0x0000090C 448 #define DDRSS_DDRPHY_DX2GCR4 0x00000910 449 #define DDRSS_DDRPHY_DX2GCR5 0x00000914 450 #define DDRSS_DDRPHY_DX2GCR6 0x00000918 451 #define DDRSS_DDRPHY_DX2GCR7 0x0000091C 452 #define DDRSS_DDRPHY_DX2GCR8 0x00000920 453 #define DDRSS_DDRPHY_DX2GCR9 0x00000924 454 #define DDRSS_DDRPHY_DX2DQMAP0 0x00000928 455 #define DDRSS_DDRPHY_DX2DQMAP1 0x0000092C 456 #define DDRSS_DDRPHY_DX2BDLR0 0x00000940 457 #define DDRSS_DDRPHY_DX2BDLR1 0x00000944 458 #define DDRSS_DDRPHY_DX2BDLR2 0x00000948 459 #define DDRSS_DDRPHY_DX2BDLR3 0x00000950 460 #define DDRSS_DDRPHY_DX2BDLR4 0x00000954 461 #define DDRSS_DDRPHY_DX2BDLR5 0x00000958 462 #define DDRSS_DDRPHY_DX2BDLR6 0x00000960 463 #define DDRSS_DDRPHY_DX2BDLR7 0x00000964 464 #define DDRSS_DDRPHY_DX2BDLR8 0x00000968 465 #define DDRSS_DDRPHY_DX2BDLR9 0x0000096C 466 #define DDRSS_DDRPHY_DX2LCDLR0 0x00000980 467 #define DDRSS_DDRPHY_DX2LCDLR1 0x00000984 468 #define DDRSS_DDRPHY_DX2LCDLR2 0x00000988 469 #define DDRSS_DDRPHY_DX2LCDLR3 0x0000098C 470 #define DDRSS_DDRPHY_DX2LCDLR4 0x00000990 471 #define DDRSS_DDRPHY_DX2LCDLR5 0x00000994 472 #define DDRSS_DDRPHY_DX2MDLR0 0x000009A0 473 #define DDRSS_DDRPHY_DX2MDLR1 0x000009A4 474 #define DDRSS_DDRPHY_DX2GTR0 0x000009C0 475 #define DDRSS_DDRPHY_DX2RSR0 0x000009D0 476 #define DDRSS_DDRPHY_DX2RSR1 0x000009D4 477 #define DDRSS_DDRPHY_DX2RSR2 0x000009D8 478 #define DDRSS_DDRPHY_DX2RSR3 0x000009DC 479 #define DDRSS_DDRPHY_DX2GSR0 0x000009E0 480 #define DDRSS_DDRPHY_DX2GSR1 0x000009E4 481 #define DDRSS_DDRPHY_DX2GSR2 0x000009E8 482 #define DDRSS_DDRPHY_DX2GSR3 0x000009EC 483 #define DDRSS_DDRPHY_DX2GSR4 0x000009F0 484 #define DDRSS_DDRPHY_DX2GSR5 0x000009F4 485 #define DDRSS_DDRPHY_DX2GSR6 0x000009F8 486 #define DDRSS_DDRPHY_DX3GCR0 0x00000A00 487 #define DDRSS_DDRPHY_DX3GCR1 0x00000A04 488 #define DDRSS_DDRPHY_DX3GCR2 0x00000A08 489 #define DDRSS_DDRPHY_DX3GCR3 0x00000A0C 490 #define DDRSS_DDRPHY_DX3GCR4 0x00000A10 491 #define DDRSS_DDRPHY_DX3GCR5 0x00000A14 492 #define DDRSS_DDRPHY_DX3GCR6 0x00000A18 493 #define DDRSS_DDRPHY_DX3GCR7 0x00000A1C 494 #define DDRSS_DDRPHY_DX3GCR8 0x00000A20 495 #define DDRSS_DDRPHY_DX3GCR9 0x00000A24 496 #define DDRSS_DDRPHY_DX3DQMAP0 0x00000A28 497 #define DDRSS_DDRPHY_DX3DQMAP1 0x00000A2C 498 #define DDRSS_DDRPHY_DX3BDLR0 0x00000A40 499 #define DDRSS_DDRPHY_DX3BDLR1 0x00000A44 500 #define DDRSS_DDRPHY_DX3BDLR2 0x00000A48 501 #define DDRSS_DDRPHY_DX3BDLR3 0x00000A50 502 #define DDRSS_DDRPHY_DX3BDLR4 0x00000A54 503 #define DDRSS_DDRPHY_DX3BDLR5 0x00000A58 504 #define DDRSS_DDRPHY_DX3BDLR6 0x00000A60 505 #define DDRSS_DDRPHY_DX3BDLR7 0x00000A64 506 #define DDRSS_DDRPHY_DX3BDLR8 0x00000A68 507 #define DDRSS_DDRPHY_DX3BDLR9 0x00000A6C 508 #define DDRSS_DDRPHY_DX3LCDLR0 0x00000A80 509 #define DDRSS_DDRPHY_DX3LCDLR1 0x00000A84 510 #define DDRSS_DDRPHY_DX3LCDLR2 0x00000A88 511 #define DDRSS_DDRPHY_DX3LCDLR3 0x00000A8C 512 #define DDRSS_DDRPHY_DX3LCDLR4 0x00000A90 513 #define DDRSS_DDRPHY_DX3LCDLR5 0x00000A94 514 #define DDRSS_DDRPHY_DX3MDLR0 0x00000AA0 515 #define DDRSS_DDRPHY_DX3MDLR1 0x00000AA4 516 #define DDRSS_DDRPHY_DX3GTR0 0x00000AC0 517 #define DDRSS_DDRPHY_DX3RSR0 0x00000AD0 518 #define DDRSS_DDRPHY_DX3RSR1 0x00000AD4 519 #define DDRSS_DDRPHY_DX3RSR2 0x00000AD8 520 #define DDRSS_DDRPHY_DX3RSR3 0x00000ADC 521 #define DDRSS_DDRPHY_DX3GSR0 0x00000AE0 522 #define DDRSS_DDRPHY_DX3GSR1 0x00000AE4 523 #define DDRSS_DDRPHY_DX3GSR2 0x00000AE8 524 #define DDRSS_DDRPHY_DX3GSR3 0x00000AEC 525 #define DDRSS_DDRPHY_DX3GSR4 0x00000AF0 526 #define DDRSS_DDRPHY_DX3GSR5 0x00000AF4 527 #define DDRSS_DDRPHY_DX3GSR6 0x00000AF8 528 #define DDRSS_DDRPHY_DX4GCR0 0x00000B00 529 #define DDRSS_DDRPHY_DX4GCR1 0x00000B04 530 #define DDRSS_DDRPHY_DX4GCR2 0x00000B08 531 #define DDRSS_DDRPHY_DX4GCR3 0x00000B0C 532 #define DDRSS_DDRPHY_DX4GCR4 0x00000B10 533 #define DDRSS_DDRPHY_DX4GCR5 0x00000B14 534 #define DDRSS_DDRPHY_DX4GCR6 0x00000B18 535 #define DDRSS_DDRPHY_DX4GCR7 0x00000B1C 536 #define DDRSS_DDRPHY_DX4GCR8 0x00000B20 537 #define DDRSS_DDRPHY_DX4GCR9 0x00000B24 538 #define DDRSS_DDRPHY_DX4DQMAP0 0x00000B28 539 #define DDRSS_DDRPHY_DX4DQMAP1 0x00000B2C 540 #define DDRSS_DDRPHY_DX4BDLR0 0x00000B40 541 #define DDRSS_DDRPHY_DX4BDLR1 0x00000B44 542 #define DDRSS_DDRPHY_DX4BDLR2 0x00000B48 543 #define DDRSS_DDRPHY_DX4BDLR3 0x00000B50 544 #define DDRSS_DDRPHY_DX4BDLR4 0x00000B54 545 #define DDRSS_DDRPHY_DX4BDLR5 0x00000B58 546 #define DDRSS_DDRPHY_DX4BDLR6 0x00000B60 547 #define DDRSS_DDRPHY_DX4BDLR7 0x00000B64 548 #define DDRSS_DDRPHY_DX4BDLR8 0x00000B68 549 #define DDRSS_DDRPHY_DX4BDLR9 0x00000B6C 550 #define DDRSS_DDRPHY_DX4LCDLR0 0x00000B80 551 #define DDRSS_DDRPHY_DX4LCDLR1 0x00000B84 552 #define DDRSS_DDRPHY_DX4LCDLR2 0x00000B88 553 #define DDRSS_DDRPHY_DX4LCDLR3 0x00000B8C 554 #define DDRSS_DDRPHY_DX4LCDLR4 0x00000B90 555 #define DDRSS_DDRPHY_DX4LCDLR5 0x00000B94 556 #define DDRSS_DDRPHY_DX4MDLR0 0x00000BA0 557 #define DDRSS_DDRPHY_DX4MDLR1 0x00000BA4 558 #define DDRSS_DDRPHY_DX4GTR0 0x00000BC0 559 #define DDRSS_DDRPHY_DX4RSR0 0x00000BD0 560 #define DDRSS_DDRPHY_DX4RSR1 0x00000BD4 561 #define DDRSS_DDRPHY_DX4RSR2 0x00000BD8 562 #define DDRSS_DDRPHY_DX4RSR3 0x00000BDC 563 #define DDRSS_DDRPHY_DX4GSR0 0x00000BE0 564 #define DDRSS_DDRPHY_DX4GSR1 0x00000BE4 565 #define DDRSS_DDRPHY_DX4GSR2 0x00000BE8 566 #define DDRSS_DDRPHY_DX4GSR3 0x00000BEC 567 #define DDRSS_DDRPHY_DX4GSR4 0x00000BF0 568 #define DDRSS_DDRPHY_DX4GSR5 0x00000BF4 569 #define DDRSS_DDRPHY_DX4GSR6 0x00000BF8 570 #define DDRSS_DDRPHY_DX5GCR0 0x00000C00 571 #define DDRSS_DDRPHY_DX5GCR1 0x00000C04 572 #define DDRSS_DDRPHY_DX5GCR2 0x00000C08 573 #define DDRSS_DDRPHY_DX5GCR3 0x00000C0C 574 #define DDRSS_DDRPHY_DX5GCR4 0x00000C10 575 #define DDRSS_DDRPHY_DX5GCR5 0x00000C14 576 #define DDRSS_DDRPHY_DX5GCR6 0x00000C18 577 #define DDRSS_DDRPHY_DX5GCR7 0x00000C1C 578 #define DDRSS_DDRPHY_DX5GCR8 0x00000C20 579 #define DDRSS_DDRPHY_DX5GCR9 0x00000C24 580 #define DDRSS_DDRPHY_DX5DQMAP0 0x00000C28 581 #define DDRSS_DDRPHY_DX5DQMAP1 0x00000C2C 582 #define DDRSS_DDRPHY_DX5BDLR0 0x00000C40 583 #define DDRSS_DDRPHY_DX5BDLR1 0x00000C44 584 #define DDRSS_DDRPHY_DX5BDLR2 0x00000C48 585 #define DDRSS_DDRPHY_DX5BDLR3 0x00000C50 586 #define DDRSS_DDRPHY_DX5BDLR4 0x00000C54 587 #define DDRSS_DDRPHY_DX5BDLR5 0x00000C58 588 #define DDRSS_DDRPHY_DX5BDLR6 0x00000C60 589 #define DDRSS_DDRPHY_DX5BDLR7 0x00000C64 590 #define DDRSS_DDRPHY_DX5BDLR8 0x00000C68 591 #define DDRSS_DDRPHY_DX5BDLR9 0x00000C6C 592 #define DDRSS_DDRPHY_DX5LCDLR0 0x00000C80 593 #define DDRSS_DDRPHY_DX5LCDLR1 0x00000C84 594 #define DDRSS_DDRPHY_DX5LCDLR2 0x00000C88 595 #define DDRSS_DDRPHY_DX5LCDLR3 0x00000C8C 596 #define DDRSS_DDRPHY_DX5LCDLR4 0x00000C90 597 #define DDRSS_DDRPHY_DX5LCDLR5 0x00000C94 598 #define DDRSS_DDRPHY_DX5MDLR0 0x00000CA0 599 #define DDRSS_DDRPHY_DX5MDLR1 0x00000CA4 600 #define DDRSS_DDRPHY_DX5GTR0 0x00000CC0 601 #define DDRSS_DDRPHY_DX5RSR0 0x00000CD0 602 #define DDRSS_DDRPHY_DX5RSR1 0x00000CD4 603 #define DDRSS_DDRPHY_DX5RSR2 0x00000CD8 604 #define DDRSS_DDRPHY_DX5RSR3 0x00000CDC 605 #define DDRSS_DDRPHY_DX5GSR0 0x00000CE0 606 #define DDRSS_DDRPHY_DX5GSR1 0x00000CE4 607 #define DDRSS_DDRPHY_DX5GSR2 0x00000CE8 608 #define DDRSS_DDRPHY_DX5GSR3 0x00000CEC 609 #define DDRSS_DDRPHY_DX5GSR4 0x00000CF0 610 #define DDRSS_DDRPHY_DX5GSR5 0x00000CF4 611 #define DDRSS_DDRPHY_DX5GSR6 0x00000CF8 612 #define DDRSS_DDRPHY_DX6GCR0 0x00000D00 613 #define DDRSS_DDRPHY_DX6GCR1 0x00000D04 614 #define DDRSS_DDRPHY_DX6GCR2 0x00000D08 615 #define DDRSS_DDRPHY_DX6GCR3 0x00000D0C 616 #define DDRSS_DDRPHY_DX6GCR4 0x00000D10 617 #define DDRSS_DDRPHY_DX6GCR5 0x00000D14 618 #define DDRSS_DDRPHY_DX6GCR6 0x00000D18 619 #define DDRSS_DDRPHY_DX6GCR7 0x00000D1C 620 #define DDRSS_DDRPHY_DX6GCR8 0x00000D20 621 #define DDRSS_DDRPHY_DX6GCR9 0x00000D24 622 #define DDRSS_DDRPHY_DX6DQMAP0 0x00000D28 623 #define DDRSS_DDRPHY_DX6DQMAP1 0x00000D2C 624 #define DDRSS_DDRPHY_DX6BDLR0 0x00000D40 625 #define DDRSS_DDRPHY_DX6BDLR1 0x00000D44 626 #define DDRSS_DDRPHY_DX6BDLR2 0x00000D48 627 #define DDRSS_DDRPHY_DX6BDLR3 0x00000D50 628 #define DDRSS_DDRPHY_DX6BDLR4 0x00000D54 629 #define DDRSS_DDRPHY_DX6BDLR5 0x00000D58 630 #define DDRSS_DDRPHY_DX6BDLR6 0x00000D60 631 #define DDRSS_DDRPHY_DX6BDLR7 0x00000D64 632 #define DDRSS_DDRPHY_DX6BDLR8 0x00000D68 633 #define DDRSS_DDRPHY_DX6BDLR9 0x00000D6C 634 #define DDRSS_DDRPHY_DX6LCDLR0 0x00000D80 635 #define DDRSS_DDRPHY_DX6LCDLR1 0x00000D84 636 #define DDRSS_DDRPHY_DX6LCDLR2 0x00000D88 637 #define DDRSS_DDRPHY_DX6LCDLR3 0x00000D8C 638 #define DDRSS_DDRPHY_DX6LCDLR4 0x00000D90 639 #define DDRSS_DDRPHY_DX6LCDLR5 0x00000D94 640 #define DDRSS_DDRPHY_DX6MDLR0 0x00000DA0 641 #define DDRSS_DDRPHY_DX6MDLR1 0x00000DA4 642 #define DDRSS_DDRPHY_DX6GTR0 0x00000DC0 643 #define DDRSS_DDRPHY_DX6RSR0 0x00000DD0 644 #define DDRSS_DDRPHY_DX6RSR1 0x00000DD4 645 #define DDRSS_DDRPHY_DX6RSR2 0x00000DD8 646 #define DDRSS_DDRPHY_DX6RSR3 0x00000DDC 647 #define DDRSS_DDRPHY_DX6GSR0 0x00000DE0 648 #define DDRSS_DDRPHY_DX6GSR1 0x00000DE4 649 #define DDRSS_DDRPHY_DX6GSR2 0x00000DE8 650 #define DDRSS_DDRPHY_DX6GSR3 0x00000DEC 651 #define DDRSS_DDRPHY_DX6GSR4 0x00000DF0 652 #define DDRSS_DDRPHY_DX6GSR5 0x00000DF4 653 #define DDRSS_DDRPHY_DX6GSR6 0x00000DF8 654 #define DDRSS_DDRPHY_DX7GCR0 0x00000E00 655 #define DDRSS_DDRPHY_DX7GCR1 0x00000E04 656 #define DDRSS_DDRPHY_DX7GCR2 0x00000E08 657 #define DDRSS_DDRPHY_DX7GCR3 0x00000E0C 658 #define DDRSS_DDRPHY_DX7GCR4 0x00000E10 659 #define DDRSS_DDRPHY_DX7GCR5 0x00000E14 660 #define DDRSS_DDRPHY_DX7GCR6 0x00000E18 661 #define DDRSS_DDRPHY_DX7GCR7 0x00000E1C 662 #define DDRSS_DDRPHY_DX7GCR8 0x00000E20 663 #define DDRSS_DDRPHY_DX7GCR9 0x00000E24 664 #define DDRSS_DDRPHY_DX7DQMAP0 0x00000E28 665 #define DDRSS_DDRPHY_DX7DQMAP1 0x00000E2C 666 #define DDRSS_DDRPHY_DX7BDLR0 0x00000E40 667 #define DDRSS_DDRPHY_DX7BDLR1 0x00000E44 668 #define DDRSS_DDRPHY_DX7BDLR2 0x00000E48 669 #define DDRSS_DDRPHY_DX7BDLR3 0x00000E50 670 #define DDRSS_DDRPHY_DX7BDLR4 0x00000E54 671 #define DDRSS_DDRPHY_DX7BDLR5 0x00000E58 672 #define DDRSS_DDRPHY_DX7BDLR6 0x00000E60 673 #define DDRSS_DDRPHY_DX7BDLR7 0x00000E64 674 #define DDRSS_DDRPHY_DX7BDLR8 0x00000E68 675 #define DDRSS_DDRPHY_DX7BDLR9 0x00000E6C 676 #define DDRSS_DDRPHY_DX7LCDLR0 0x00000E80 677 #define DDRSS_DDRPHY_DX7LCDLR1 0x00000E84 678 #define DDRSS_DDRPHY_DX7LCDLR2 0x00000E88 679 #define DDRSS_DDRPHY_DX7LCDLR3 0x00000E8C 680 #define DDRSS_DDRPHY_DX7LCDLR4 0x00000E90 681 #define DDRSS_DDRPHY_DX7LCDLR5 0x00000E94 682 #define DDRSS_DDRPHY_DX7MDLR0 0x00000EA0 683 #define DDRSS_DDRPHY_DX7MDLR1 0x00000EA4 684 #define DDRSS_DDRPHY_DX7GTR0 0x00000EC0 685 #define DDRSS_DDRPHY_DX7RSR0 0x00000ED0 686 #define DDRSS_DDRPHY_DX7RSR1 0x00000ED4 687 #define DDRSS_DDRPHY_DX7RSR2 0x00000ED8 688 #define DDRSS_DDRPHY_DX7RSR3 0x00000EDC 689 #define DDRSS_DDRPHY_DX7GSR0 0x00000EE0 690 #define DDRSS_DDRPHY_DX7GSR1 0x00000EE4 691 #define DDRSS_DDRPHY_DX7GSR2 0x00000EE8 692 #define DDRSS_DDRPHY_DX7GSR3 0x00000EEC 693 #define DDRSS_DDRPHY_DX7GSR4 0x00000EF0 694 #define DDRSS_DDRPHY_DX7GSR5 0x00000EF4 695 #define DDRSS_DDRPHY_DX7GSR6 0x00000EF8 696 #define DDRSS_DDRPHY_DX8GCR0 0x00000F00 697 #define DDRSS_DDRPHY_DX8GCR1 0x00000F04 698 #define DDRSS_DDRPHY_DX8GCR2 0x00000F08 699 #define DDRSS_DDRPHY_DX8GCR3 0x00000F0C 700 #define DDRSS_DDRPHY_DX8GCR4 0x00000F10 701 #define DDRSS_DDRPHY_DX8GCR5 0x00000F14 702 #define DDRSS_DDRPHY_DX8GCR6 0x00000F18 703 #define DDRSS_DDRPHY_DX8GCR7 0x00000F1C 704 #define DDRSS_DDRPHY_DX8GCR8 0x00000F20 705 #define DDRSS_DDRPHY_DX8GCR9 0x00000F24 706 #define DDRSS_DDRPHY_DX8DQMAP0 0x00000F28 707 #define DDRSS_DDRPHY_DX8DQMAP1 0x00000F2C 708 #define DDRSS_DDRPHY_DX8BDLR0 0x00000F40 709 #define DDRSS_DDRPHY_DX8BDLR1 0x00000F44 710 #define DDRSS_DDRPHY_DX8BDLR2 0x00000F48 711 #define DDRSS_DDRPHY_DX8BDLR3 0x00000F50 712 #define DDRSS_DDRPHY_DX8BDLR4 0x00000F54 713 #define DDRSS_DDRPHY_DX8BDLR5 0x00000F58 714 #define DDRSS_DDRPHY_DX8BDLR6 0x00000F60 715 #define DDRSS_DDRPHY_DX8BDLR7 0x00000F64 716 #define DDRSS_DDRPHY_DX8BDLR8 0x00000F68 717 #define DDRSS_DDRPHY_DX8BDLR9 0x00000F6C 718 #define DDRSS_DDRPHY_DX8LCDLR0 0x00000F80 719 #define DDRSS_DDRPHY_DX8LCDLR1 0x00000F84 720 #define DDRSS_DDRPHY_DX8LCDLR2 0x00000F88 721 #define DDRSS_DDRPHY_DX8LCDLR3 0x00000F8C 722 #define DDRSS_DDRPHY_DX8LCDLR4 0x00000F90 723 #define DDRSS_DDRPHY_DX8LCDLR5 0x00000F94 724 #define DDRSS_DDRPHY_DX8MDLR0 0x00000FA0 725 #define DDRSS_DDRPHY_DX8MDLR1 0x00000FA4 726 #define DDRSS_DDRPHY_DX8GTR0 0x00000FC0 727 #define DDRSS_DDRPHY_DX8RSR0 0x00000FD0 728 #define DDRSS_DDRPHY_DX8RSR1 0x00000FD4 729 #define DDRSS_DDRPHY_DX8RSR2 0x00000FD8 730 #define DDRSS_DDRPHY_DX8RSR3 0x00000FDC 731 #define DDRSS_DDRPHY_DX8GSR0 0x00000FE0 732 #define DDRSS_DDRPHY_DX8GSR1 0x00000FE4 733 #define DDRSS_DDRPHY_DX8GSR2 0x00000FE8 734 #define DDRSS_DDRPHY_DX8GSR3 0x00000FEC 735 #define DDRSS_DDRPHY_DX8GSR4 0x00000FF0 736 #define DDRSS_DDRPHY_DX8GSR5 0x00000FF4 737 #define DDRSS_DDRPHY_DX8GSR6 0x00000FF8 738 #define DDRSS_DDRPHY_DX8SL0OSC 0x00001400 739 #define DDRSS_DDRPHY_DX8SL0PLLCR0 0x00001404 740 #define DDRSS_DDRPHY_DX8SL0PLLCR1 0x00001408 741 #define DDRSS_DDRPHY_DX8SL0PLLCR2 0x0000140C 742 #define DDRSS_DDRPHY_DX8SL0PLLCR3 0x00001410 743 #define DDRSS_DDRPHY_DX8SL0PLLCR4 0x00001414 744 #define DDRSS_DDRPHY_DX8SL0PLLCR5 0x00001418 745 #define DDRSS_DDRPHY_DX8SL0DQSCTL 0x0000141C 746 #define DDRSS_DDRPHY_DX8SL0TRNCTL 0x00001420 747 #define DDRSS_DDRPHY_DX8SL0DDLCTL 0x00001424 748 #define DDRSS_DDRPHY_DX8SL0DXCTL1 0x00001428 749 #define DDRSS_DDRPHY_DX8SL0DXCTL2 0x0000142C 750 #define DDRSS_DDRPHY_DX8SL0IOCR 0x00001430 751 #define DDRSS_DDRPHY_DX4SL0IOCR 0x00001434 752 #define DDRSS_DDRPHY_DX8SL1OSC 0x00001440 753 #define DDRSS_DDRPHY_DX8SL1PLLCR0 0x00001444 754 #define DDRSS_DDRPHY_DX8SL1PLLCR1 0x00001448 755 #define DDRSS_DDRPHY_DX8SL1PLLCR2 0x0000144C 756 #define DDRSS_DDRPHY_DX8SL1PLLCR3 0x00001450 757 #define DDRSS_DDRPHY_DX8SL1PLLCR4 0x00001454 758 #define DDRSS_DDRPHY_DX8SL1PLLCR5 0x00001458 759 #define DDRSS_DDRPHY_DX8SL1DQSCTL 0x0000145C 760 #define DDRSS_DDRPHY_DX8SL1TRNCTL 0x00001460 761 #define DDRSS_DDRPHY_DX8SL1DDLCTL 0x00001464 762 #define DDRSS_DDRPHY_DX8SL1DXCTL1 0x00001468 763 #define DDRSS_DDRPHY_DX8SL1DXCTL2 0x0000146C 764 #define DDRSS_DDRPHY_DX8SL1IOCR 0x00001470 765 #define DDRSS_DDRPHY_DX4SL1IOCR 0x00001474 766 #define DDRSS_DDRPHY_DX8SL2OSC 0x00001480 767 #define DDRSS_DDRPHY_DX8SL2PLLCR0 0x00001484 768 #define DDRSS_DDRPHY_DX8SL2PLLCR1 0x00001488 769 #define DDRSS_DDRPHY_DX8SL2PLLCR2 0x0000148C 770 #define DDRSS_DDRPHY_DX8SL2PLLCR3 0x00001490 771 #define DDRSS_DDRPHY_DX8SL2PLLCR4 0x00001494 772 #define DDRSS_DDRPHY_DX8SL2PLLCR5 0x00001498 773 #define DDRSS_DDRPHY_DX8SL2DQSCTL 0x0000149C 774 #define DDRSS_DDRPHY_DX8SL2TRNCTL 0x000014A0 775 #define DDRSS_DDRPHY_DX8SL2DDLCTL 0x000014A4 776 #define DDRSS_DDRPHY_DX8SL2DXCTL1 0x000014A8 777 #define DDRSS_DDRPHY_DX8SL2DXCTL2 0x000014AC 778 #define DDRSS_DDRPHY_DX8SL2IOCR 0x000014B0 779 #define DDRSS_DDRPHY_DX4SL2IOCR 0x000014B4 780 #define DDRSS_DDRPHY_DX8SL3OSC 0x000014C0 781 #define DDRSS_DDRPHY_DX8SL3PLLCR0 0x000014C4 782 #define DDRSS_DDRPHY_DX8SL3PLLCR1 0x000014C8 783 #define DDRSS_DDRPHY_DX8SL3PLLCR2 0x000014CC 784 #define DDRSS_DDRPHY_DX8SL3PLLCR3 0x000014D0 785 #define DDRSS_DDRPHY_DX8SL3PLLCR4 0x000014D4 786 #define DDRSS_DDRPHY_DX8SL3PLLCR5 0x000014D8 787 #define DDRSS_DDRPHY_DX8SL3DQSCTL 0x000014DC 788 #define DDRSS_DDRPHY_DX8SL3TRNCTL 0x000014E0 789 #define DDRSS_DDRPHY_DX8SL3DDLCTL 0x000014E4 790 #define DDRSS_DDRPHY_DX8SL3DXCTL1 0x000014E8 791 #define DDRSS_DDRPHY_DX8SL3DXCTL2 0x000014EC 792 #define DDRSS_DDRPHY_DX8SL3IOCR 0x000014F0 793 #define DDRSS_DDRPHY_DX4SL3IOCR 0x000014F4 794 #define DDRSS_DDRPHY_DX8SL4OSC 0x00001500 795 #define DDRSS_DDRPHY_DX8SL4PLLCR0 0x00001504 796 #define DDRSS_DDRPHY_DX8SL4PLLCR1 0x00001508 797 #define DDRSS_DDRPHY_DX8SL4PLLCR2 0x0000150C 798 #define DDRSS_DDRPHY_DX8SL4PLLCR3 0x00001510 799 #define DDRSS_DDRPHY_DX8SL4PLLCR4 0x00001514 800 #define DDRSS_DDRPHY_DX8SL4PLLCR5 0x00001518 801 #define DDRSS_DDRPHY_DX8SL4DQSCTL 0x0000151C 802 #define DDRSS_DDRPHY_DX8SL4TRNCTL 0x00001520 803 #define DDRSS_DDRPHY_DX8SL4DDLCTL 0x00001524 804 #define DDRSS_DDRPHY_DX8SL4DXCTL1 0x00001528 805 #define DDRSS_DDRPHY_DX8SL4DXCTL2 0x0000152C 806 #define DDRSS_DDRPHY_DX8SL4IOCR 0x00001530 807 #define DDRSS_DDRPHY_DX4SL4IOCR 0x00001534 808 #define DDRSS_DDRPHY_DX8SL5OSC 0x00001540 809 #define DDRSS_DDRPHY_DX8SL5PLLCR0 0x00001544 810 #define DDRSS_DDRPHY_DX8SL5PLLCR1 0x00001548 811 #define DDRSS_DDRPHY_DX8SL5PLLCR2 0x0000154C 812 #define DDRSS_DDRPHY_DX8SL5PLLCR3 0x00001550 813 #define DDRSS_DDRPHY_DX8SL5PLLCR4 0x00001554 814 #define DDRSS_DDRPHY_DX8SL5PLLCR5 0x00001558 815 #define DDRSS_DDRPHY_DX8SL5DQSCTL 0x0000155C 816 #define DDRSS_DDRPHY_DX8SL5TRNCTL 0x00001560 817 #define DDRSS_DDRPHY_DX8SL5DDLCTL 0x00001564 818 #define DDRSS_DDRPHY_DX8SL5DXCTL1 0x00001568 819 #define DDRSS_DDRPHY_DX8SL5DXCTL2 0x0000156C 820 #define DDRSS_DDRPHY_DX8SL5IOCR 0x00001570 821 #define DDRSS_DDRPHY_DX4SL5IOCR 0x00001574 822 #define DDRSS_DDRPHY_DX8SL6OSC 0x00001580 823 #define DDRSS_DDRPHY_DX8SL6PLLCR0 0x00001584 824 #define DDRSS_DDRPHY_DX8SL6PLLCR1 0x00001588 825 #define DDRSS_DDRPHY_DX8SL6PLLCR2 0x0000158C 826 #define DDRSS_DDRPHY_DX8SL6PLLCR3 0x00001590 827 #define DDRSS_DDRPHY_DX8SL6PLLCR4 0x00001594 828 #define DDRSS_DDRPHY_DX8SL6PLLCR5 0x00001598 829 #define DDRSS_DDRPHY_DX8SL6DQSCTL 0x0000159C 830 #define DDRSS_DDRPHY_DX8SL6TRNCTL 0x000015A0 831 #define DDRSS_DDRPHY_DX8SL6DDLCTL 0x000015A4 832 #define DDRSS_DDRPHY_DX8SL6DXCTL1 0x000015A8 833 #define DDRSS_DDRPHY_DX8SL6DXCTL2 0x000015AC 834 #define DDRSS_DDRPHY_DX8SL6IOCR 0x000015B0 835 #define DDRSS_DDRPHY_DX4SL6IOCR 0x000015B4 836 #define DDRSS_DDRPHY_DX8SL7OSC 0x000015C0 837 #define DDRSS_DDRPHY_DX8SL7PLLCR0 0x000015C4 838 #define DDRSS_DDRPHY_DX8SL7PLLCR1 0x000015C8 839 #define DDRSS_DDRPHY_DX8SL7PLLCR2 0x000015CC 840 #define DDRSS_DDRPHY_DX8SL7PLLCR3 0x000015D0 841 #define DDRSS_DDRPHY_DX8SL7PLLCR4 0x000015D4 842 #define DDRSS_DDRPHY_DX8SL7PLLCR5 0x000015D8 843 #define DDRSS_DDRPHY_DX8SL7DQSCTL 0x000015DC 844 #define DDRSS_DDRPHY_DX8SL7TRNCTL 0x000015E0 845 #define DDRSS_DDRPHY_DX8SL7DDLCTL 0x000015E4 846 #define DDRSS_DDRPHY_DX8SL7DXCTL1 0x000015E8 847 #define DDRSS_DDRPHY_DX8SL7DXCTL2 0x000015EC 848 #define DDRSS_DDRPHY_DX8SL7IOCR 0x000015F0 849 #define DDRSS_DDRPHY_DX4SL7IOCR 0x000015F4 850 #define DDRSS_DDRPHY_DX8SL8OSC 0x00001600 851 #define DDRSS_DDRPHY_DX8SL8PLLCR0 0x00001604 852 #define DDRSS_DDRPHY_DX8SL8PLLCR1 0x00001608 853 #define DDRSS_DDRPHY_DX8SL8PLLCR2 0x0000160C 854 #define DDRSS_DDRPHY_DX8SL8PLLCR3 0x00001610 855 #define DDRSS_DDRPHY_DX8SL8PLLCR4 0x00001614 856 #define DDRSS_DDRPHY_DX8SL8PLLCR5 0x00001618 857 #define DDRSS_DDRPHY_DX8SL8DQSCTL 0x0000161C 858 #define DDRSS_DDRPHY_DX8SL8TRNCTL 0x00001620 859 #define DDRSS_DDRPHY_DX8SL8DDLCTL 0x00001624 860 #define DDRSS_DDRPHY_DX8SL8DXCTL1 0x00001628 861 #define DDRSS_DDRPHY_DX8SL8DXCTL2 0x0000162C 862 #define DDRSS_DDRPHY_DX8SL8IOCR 0x00001630 863 #define DDRSS_DDRPHY_DX4SL8IOCR 0x00001634 864 #define DDRSS_DDRPHY_DX8SLBOSC 0x000017C0 865 #define DDRSS_DDRPHY_DX8SLBPLLCR0 0x000017C4 866 #define DDRSS_DDRPHY_DX8SLBPLLCR1 0x000017C8 867 #define DDRSS_DDRPHY_DX8SLBPLLCR2 0x000017CC 868 #define DDRSS_DDRPHY_DX8SLBPLLCR3 0x000017D0 869 #define DDRSS_DDRPHY_DX8SLBPLLCR4 0x000017D4 870 #define DDRSS_DDRPHY_DX8SLBPLLCR5 0x000017D8 871 #define DDRSS_DDRPHY_DX8SLBDQSCTL 0x000017DC 872 #define DDRSS_DDRPHY_DX8SLBTRNCTL 0x000017E0 873 #define DDRSS_DDRPHY_DX8SLBDDLCTL 0x000017E4 874 #define DDRSS_DDRPHY_DX8SLBDXCTL1 0x000017E8 875 #define DDRSS_DDRPHY_DX8SLBDXCTL2 0x000017EC 876 #define DDRSS_DDRPHY_DX8SLBIOCR 0x000017F0 877 #define DDRSS_DDRPHY_DX4SLBIOCR 0x000017F4 878 879 #define PIR_INIT_SHIFT 0 880 #define PIR_INIT_MASK BIT(PIR_INIT_SHIFT) 881 #define PIR_ZCAL_SHIFT 1 882 #define PIR_ZCAL_MASK BIT(PIR_ZCAL_SHIFT) 883 #define PIR_CA_SHIFT 2 884 #define PIR_CA_MASK BIT(PIR_CA_SHIFT) 885 #define PIR_PLLINIT_SHIFT 4 886 #define PIR_PLLINIT_MASK BIT(PIR_PLLINIT_SHIFT) 887 #define PIR_DCAL_SHIFT 5 888 #define PIR_DCAL_MASK BIT(PIR_DCAL_SHIFT) 889 #define PIR_PHYRST_SHIFT 6 890 #define PIR_PHYRST_MASK BIT(PIR_PHYRST_SHIFT) 891 #define PIR_DRAMRST_SHIFT 7 892 #define PIR_DRAMRST_MASK BIT(PIR_DRAMRST_SHIFT) 893 #define PIR_DRAMINIT_SHIFT 8 894 #define PIR_DRAMINIT_MASK BIT(PIR_DRAMINIT_SHIFT) 895 #define PIR_WL_SHIFT 9 896 #define PIR_WL_MASK BIT(PIR_WL_SHIFT) 897 #define PIR_QSGATE_SHIFT 10 898 #define PIR_QSGATE_MASK BIT(PIR_QSGATE_SHIFT) 899 #define PIR_WLADJ_SHIFT 11 900 #define PIR_WLADJ_MASK BIT(PIR_WLADJ_SHIFT) 901 #define PIR_RDDSKW_SHIFT 12 902 #define PIR_RDDSKW_MASK BIT(PIR_RDDSKW_SHIFT) 903 #define PIR_WRDSKW_SHIFT 13 904 #define PIR_WRDSKW_MASK BIT(PIR_WRDSKW_SHIFT) 905 #define PIR_RDEYE_SHIFT 14 906 #define PIR_RDEYE_MASK BIT(PIR_RDEYE_SHIFT) 907 #define PIR_WREYE_SHIFT 15 908 #define PIR_WREYE_MASK BIT(PIR_WREYE_SHIFT) 909 #define PIR_SRD_SHIFT 16 910 #define PIR_SRD_MASK BIT(PIR_SRD_SHIFT) 911 #define PIR_VREF_SHIFT 17 912 #define PIR_VREF_MASK BIT(PIR_VREF_SHIFT) 913 #define PIR_CTLDINIT_SHIFT 18 914 #define PIR_CTLDINIT_MASK BIT(PIR_CTLDINIT_SHIFT) 915 #define PIR_RDIMMINIT_SHIFT 19 916 #define PIR_RDIMMINIT_MASK BIT(PIR_RDIMMINIT_SHIFT) 917 #define PIR_DQS2DQ_SHIFT 20 918 #define PIR_DQS2DQ_MASK BIT(PIR_DQS2DQ_SHIFT) 919 #define PIR_DCALPSE_SHIFT 29 920 #define PIR_DCALPSE_MASK BIT(PIR_DCALPSE_SHIFT) 921 #define PIR_ZCALBYP_SHIFT 30 922 #define PIR_ZCALBYP_MASK BIT(PIR_ZCALBYP_SHIFT) 923 924 #define PIR_PHY_INIT (PIR_ZCAL_MASK | PIR_PLLINIT_MASK | \ 925 PIR_DCAL_MASK | PIR_PHYRST_MASK) 926 #define PIR_DRAM_INIT (PIR_DRAMRST_MASK | PIR_DRAMINIT_MASK) 927 #define PIR_DATA_TR_INIT (PIR_WL_MASK | PIR_QSGATE_MASK | \ 928 PIR_WLADJ_MASK | PIR_RDDSKW_MASK | \ 929 PIR_WRDSKW_MASK | PIR_RDEYE_MASK \ 930 PIR_WREYE_MASK) 931 932 #define PGSR0_IDONE_SHIFT 0 933 #define PGSR0_IDONE_MASK BIT(PGSR0_IDONE_SHIFT) 934 #define PGSR0_PLDONE_SHIFT 1 935 #define PGSR0_PLDONE_MASK BIT(PGSR0_PLDONE_SHIFT) 936 #define PGSR0_DCDONE_SHIFT 2 937 #define PGSR0_DCDONE_MASK BIT(PGSR0_DCDONE_SHIFT) 938 #define PGSR0_ZCDONE_SHIFT 3 939 #define PGSR0_ZCDONE_MASK BIT(PGSR0_ZCDONE_SHIFT) 940 #define PGSR0_DIDONE_SHIFT 4 941 #define PGSR0_DIDONE_MASK BIT(PGSR0_DIDONE_SHIFT) 942 #define PGSR0_WLDONE_SHIFT 5 943 #define PGSR0_WLDONE_MASK BIT(PGSR0_WLDONE_SHIFT) 944 #define PGSR0_QSGDONE_SHIFT 6 945 #define PGSR0_QSGDONE_MASK BIT(PGSR0_QSGDONE_SHIFT) 946 #define PGSR0_WLADONE_SHIFT 7 947 #define PGSR0_WLADONE_MASK BIT(PGSR0_WLADONE_SHIFT) 948 #define PGSR0_RDDONE_SHIFT 8 949 #define PGSR0_RDDONE_MASK BIT(PGSR0_RDDONE_SHIFT) 950 #define PGSR0_WDDONE_SHIFT 9 951 #define PGSR0_WDDONE_MASK BIT(PGSR0_WDDONE_SHIFT) 952 #define PGSR0_REDONE_SHIFT 10 953 #define PGSR0_REDONE_MASK BIT(PGSR0_REDONE_SHIFT) 954 #define PGSR0_WEDONE_SHIFT 11 955 #define PGSR0_WEDONE_MASK BIT(PGSR0_WEDONE_SHIFT) 956 #define PGSR0_CADONE_SHIFT 12 957 #define PGSR0_CADONE_MASK BIT(PGSR0_CADONE_SHIFT) 958 #define PGSR0_SRDDONE_SHIFT 13 959 #define PGSR0_SRDDONE_MASK BIT(PGSR0_SRDDONE_SHIFT) 960 #define PGSR0_VDONE_SHIFT 14 961 #define PGSR0_VDONE_MASK BIT(PGSR0_VDONE_SHIFT) 962 #define PGSR0_DQS2DQDONE_SHIFT 15 963 #define PGSR0_DQS2DQDONE_MASK BIT(PGSR0_DQS2DQDONE_SHIFT) 964 #define PGSR0_DQS2DQERR_SHIFT 18 965 #define PGSR0_DQS2DQERR_MASK BIT(PGSR0_DQS2DQERR_SHIFT) 966 #define PGSR0_VERR_SHIFT 19 967 #define PGSR0_VERR_MASK BIT(PGSR0_VERR_SHIFT) 968 #define PGSR0_ZCERR_SHIFT 20 969 #define PGSR0_ZCERR_MASK BIT(PGSR0_ZCERR_SHIFT) 970 #define PGSR0_WLERR_SHIFT 21 971 #define PGSR0_WLERR_MASK BIT(PGSR0_WLERR_SHIFT) 972 #define PGSR0_QSGERR_SHIFT 22 973 #define PGSR0_QSGERR_MASK BIT(PGSR0_QSGERR_SHIFT) 974 #define PGSR0_WLAERR_SHIFT 23 975 #define PGSR0_WLAERR_MASK BIT(PGSR0_WLAERR_SHIFT) 976 #define PGSR0_RDERR_SHIFT 24 977 #define PGSR0_RDERR_MASK BIT(PGSR0_RDERR_SHIFT) 978 #define PGSR0_WDERR_SHIFT 25 979 #define PGSR0_WDERR_MASK BIT(PGSR0_WDERR_SHIFT) 980 #define PGSR0_REERR_SHIFT 26 981 #define PGSR0_REERR_MASK BIT(PGSR0_REERR_SHIFT) 982 #define PGSR0_WEERR_SHIFT 27 983 #define PGSR0_WEERR_MASK BIT(PGSR0_WEERR_SHIFT) 984 #define PGSR0_CAERR_SHIFT 28 985 #define PGSR0_CAERR_MASK BIT(PGSR0_CAERR_SHIFT) 986 #define PGSR0_CAWRN_SHIFT 29 987 #define PGSR0_CAWRN_MASK BIT(PGSR0_CAWRN_SHIFT) 988 #define PGSR0_SRDERR_SHIFT 30 989 #define PGSR0_SRDERR_MASK BIT(PGSR0_SRDERR_SHIFT) 990 #define PGSR0_APLOCK_SHIFT 31 991 #define PGSR0_APLOCK_MASK BIT(PGSR0_APLOCK_SHIFT) 992 993 #define PGSR0_PHY_INIT_MASK (PGSR0_IDONE_MASK | PGSR0_PLDONE_MASK |\ 994 PGSR0_DCDONE_MASK | PGSR0_ZCDONE_MASK |\ 995 PGSR0_APLOCK_MASK) 996 #define PGSR0_DRAM_INIT_MASK (PGSR0_PHY_INIT_MASK | \ 997 PGSR0_DIDONE_MASK) 998 #define PGSR0_DATA_TR_INIT_MASK (PGSR0_DRAM_INIT_MASK) 999 1000 struct ddrss_ss_reg_params { 1001 u32 ddrss_v2h_ctl_reg; 1002 }; 1003 1004 struct ddrss_ddrctl_reg_params { 1005 u32 ddrctl_dfimisc; 1006 u32 ddrctl_dfitmg0; 1007 u32 ddrctl_dfitmg1; 1008 u32 ddrctl_dfitmg2; 1009 u32 ddrctl_init0; 1010 u32 ddrctl_init1; 1011 u32 ddrctl_init3; 1012 u32 ddrctl_init4; 1013 u32 ddrctl_init5; 1014 u32 ddrctl_init6; 1015 u32 ddrctl_init7; 1016 u32 ddrctl_mstr; 1017 u32 ddrctl_odtcfg; 1018 u32 ddrctl_odtmap; 1019 u32 ddrctl_rankctl; 1020 u32 ddrctl_rfshctl0; 1021 u32 ddrctl_rfshtmg; 1022 u32 ddrctl_zqctl0; 1023 u32 ddrctl_zqctl1; 1024 }; 1025 1026 struct ddrss_ddrctl_crc_params { 1027 u32 ddrctl_crcparctl0; 1028 u32 ddrctl_crcparctl1; 1029 u32 ddrctl_crcparctl2; 1030 }; 1031 1032 struct ddrss_ddrctl_ecc_params { 1033 u32 ddrctl_ecccfg0; 1034 }; 1035 1036 struct ddrss_ddrctl_map_params { 1037 u32 ddrctl_addrmap0; 1038 u32 ddrctl_addrmap1; 1039 u32 ddrctl_addrmap2; 1040 u32 ddrctl_addrmap3; 1041 u32 ddrctl_addrmap4; 1042 u32 ddrctl_addrmap5; 1043 u32 ddrctl_addrmap6; 1044 u32 ddrctl_addrmap7; 1045 u32 ddrctl_addrmap8; 1046 u32 ddrctl_addrmap9; 1047 u32 ddrctl_addrmap10; 1048 u32 ddrctl_addrmap11; 1049 u32 ddrctl_dqmap0; 1050 u32 ddrctl_dqmap1; 1051 u32 ddrctl_dqmap4; 1052 u32 ddrctl_dqmap5; 1053 }; 1054 1055 struct ddrss_ddrctl_pwr_params { 1056 u32 ddrctl_pwrctl; 1057 }; 1058 1059 struct ddrss_ddrctl_timing_params { 1060 u32 ddrctl_dramtmg0; 1061 u32 ddrctl_dramtmg1; 1062 u32 ddrctl_dramtmg2; 1063 u32 ddrctl_dramtmg3; 1064 u32 ddrctl_dramtmg4; 1065 u32 ddrctl_dramtmg5; 1066 u32 ddrctl_dramtmg6; 1067 u32 ddrctl_dramtmg7; 1068 u32 ddrctl_dramtmg8; 1069 u32 ddrctl_dramtmg9; 1070 u32 ddrctl_dramtmg11; 1071 u32 ddrctl_dramtmg12; 1072 u32 ddrctl_dramtmg13; 1073 u32 ddrctl_dramtmg14; 1074 u32 ddrctl_dramtmg15; 1075 u32 ddrctl_dramtmg17; 1076 }; 1077 1078 struct ddrss_ddrphy_cfg_params { 1079 u32 ddrphy_dcr; 1080 u32 ddrphy_dsgcr; 1081 u32 ddrphy_dx0gcr0; 1082 u32 ddrphy_dx0gcr1; 1083 u32 ddrphy_dx0gcr2; 1084 u32 ddrphy_dx0gcr3; 1085 u32 ddrphy_dx0gcr4; 1086 u32 ddrphy_dx0gcr5; 1087 u32 ddrphy_dx0gtr0; 1088 u32 ddrphy_dx1gcr0; 1089 u32 ddrphy_dx1gcr1; 1090 u32 ddrphy_dx1gcr2; 1091 u32 ddrphy_dx1gcr3; 1092 u32 ddrphy_dx1gcr4; 1093 u32 ddrphy_dx1gcr5; 1094 u32 ddrphy_dx1gtr0; 1095 u32 ddrphy_dx2gcr0; 1096 u32 ddrphy_dx2gcr1; 1097 u32 ddrphy_dx2gcr2; 1098 u32 ddrphy_dx2gcr3; 1099 u32 ddrphy_dx2gcr4; 1100 u32 ddrphy_dx2gcr5; 1101 u32 ddrphy_dx2gtr0; 1102 u32 ddrphy_dx3gcr0; 1103 u32 ddrphy_dx3gcr1; 1104 u32 ddrphy_dx3gcr2; 1105 u32 ddrphy_dx3gcr3; 1106 u32 ddrphy_dx3gcr4; 1107 u32 ddrphy_dx3gcr5; 1108 u32 ddrphy_dx3gtr0; 1109 u32 ddrphy_dx4gcr0; 1110 u32 ddrphy_dx4gcr1; 1111 u32 ddrphy_dx4gcr2; 1112 u32 ddrphy_dx4gcr3; 1113 u32 ddrphy_dx4gcr4; 1114 u32 ddrphy_dx4gcr5; 1115 u32 ddrphy_dx4gtr0; 1116 u32 ddrphy_dx8sl0dxctl2; 1117 u32 ddrphy_dx8sl0iocr; 1118 u32 ddrphy_dx8sl0pllcr0; 1119 u32 ddrphy_dx8sl0dqsctl; 1120 u32 ddrphy_dx8sl1dxctl2; 1121 u32 ddrphy_dx8sl1iocr; 1122 u32 ddrphy_dx8sl1pllcr0; 1123 u32 ddrphy_dx8sl1dqsctl; 1124 u32 ddrphy_dx8sl2dxctl2; 1125 u32 ddrphy_dx8sl2iocr; 1126 u32 ddrphy_dx8sl2pllcr0; 1127 u32 ddrphy_dx8sl2dqsctl; 1128 u32 ddrphy_dxccr; 1129 u32 ddrphy_odtcr; 1130 u32 ddrphy_pgcr0; 1131 u32 ddrphy_pgcr1; 1132 u32 ddrphy_pgcr2; 1133 u32 ddrphy_pgcr3; 1134 u32 ddrphy_pgcr5; 1135 u32 ddrphy_pgcr6; 1136 }; 1137 1138 struct ddrss_ddrphy_ctrl_params { 1139 u32 ddrphy_dtcr0; 1140 u32 ddrphy_dtcr1; 1141 u32 ddrphy_mr0; 1142 u32 ddrphy_mr1; 1143 u32 ddrphy_mr2; 1144 u32 ddrphy_mr3; 1145 u32 ddrphy_mr4; 1146 u32 ddrphy_mr5; 1147 u32 ddrphy_mr6; 1148 u32 ddrphy_mr11; 1149 u32 ddrphy_mr12; 1150 u32 ddrphy_mr13; 1151 u32 ddrphy_mr14; 1152 u32 ddrphy_mr22; 1153 u32 ddrphy_pllcr0; 1154 u32 ddrphy_vtcr0; 1155 }; 1156 1157 struct ddrss_ddrphy_ioctl_params { 1158 u32 ddrphy_aciocr0; 1159 u32 ddrphy_aciocr3; 1160 u32 ddrphy_aciocr5; 1161 u32 ddrphy_iovcr0; 1162 }; 1163 1164 struct ddrss_ddrphy_timing_params { 1165 u32 ddrphy_dtpr0; 1166 u32 ddrphy_dtpr1; 1167 u32 ddrphy_dtpr2; 1168 u32 ddrphy_dtpr3; 1169 u32 ddrphy_dtpr4; 1170 u32 ddrphy_dtpr5; 1171 u32 ddrphy_dtpr6; 1172 u32 ddrphy_ptr2; 1173 u32 ddrphy_ptr3; 1174 u32 ddrphy_ptr4; 1175 u32 ddrphy_ptr5; 1176 u32 ddrphy_ptr6; 1177 }; 1178 1179 struct ddrss_ddrphy_zq_params { 1180 u32 ddrphy_zq0pr0; 1181 u32 ddrphy_zq1pr0; 1182 u32 ddrphy_zqcr; 1183 }; 1184 1185 struct ddrss_params { 1186 struct ddrss_ss_reg_params ss_reg; 1187 struct ddrss_ddrctl_reg_params ctl_reg; 1188 struct ddrss_ddrctl_crc_params ctl_crc; 1189 struct ddrss_ddrctl_ecc_params ctl_ecc; 1190 struct ddrss_ddrctl_map_params ctl_map; 1191 struct ddrss_ddrctl_pwr_params ctl_pwr; 1192 struct ddrss_ddrctl_timing_params ctl_timing; 1193 struct ddrss_ddrphy_cfg_params phy_cfg; 1194 struct ddrss_ddrphy_ctrl_params phy_ctrl; 1195 struct ddrss_ddrphy_ioctl_params phy_ioctl; 1196 struct ddrss_ddrphy_timing_params phy_timing; 1197 struct ddrss_ddrphy_zq_params phy_zq; 1198 }; 1199 1200 #endif /* __K3_AM654_DDRSS_H */ 1201