1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_BIOS_PARSER_TYPES_H__ 27 28 #define __DAL_BIOS_PARSER_TYPES_H__ 29 30 #include "dm_services.h" 31 #include "include/signal_types.h" 32 #include "include/grph_object_ctrl_defs.h" 33 #include "include/gpio_types.h" 34 #include "include/link_service_types.h" 35 36 /* TODO: include signal_types.h and remove this enum */ 37 enum as_signal_type { 38 AS_SIGNAL_TYPE_NONE = 0L, /* no signal */ 39 AS_SIGNAL_TYPE_DVI, 40 AS_SIGNAL_TYPE_HDMI, 41 AS_SIGNAL_TYPE_LVDS, 42 AS_SIGNAL_TYPE_DISPLAY_PORT, 43 AS_SIGNAL_TYPE_GPU_PLL, 44 AS_SIGNAL_TYPE_XGMI, 45 AS_SIGNAL_TYPE_UNKNOWN 46 }; 47 48 enum bp_result { 49 BP_RESULT_OK = 0, /* There was no error */ 50 BP_RESULT_BADINPUT, /*Bad input parameter */ 51 BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */ 52 BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */ 53 BP_RESULT_NORECORD, /* Record can't be found */ 54 BP_RESULT_FAILURE 55 }; 56 57 enum bp_encoder_control_action { 58 /* direct VBIOS translation! Just to simplify the translation */ 59 ENCODER_CONTROL_DISABLE = 0, 60 ENCODER_CONTROL_ENABLE, 61 ENCODER_CONTROL_SETUP, 62 ENCODER_CONTROL_INIT 63 }; 64 65 enum bp_transmitter_control_action { 66 /* direct VBIOS translation! Just to simplify the translation */ 67 TRANSMITTER_CONTROL_DISABLE = 0, 68 TRANSMITTER_CONTROL_ENABLE, 69 TRANSMITTER_CONTROL_BACKLIGHT_OFF, 70 TRANSMITTER_CONTROL_BACKLIGHT_ON, 71 TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS, 72 TRANSMITTER_CONTROL_LCD_SETF_TEST_START, 73 TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP, 74 TRANSMITTER_CONTROL_INIT, 75 TRANSMITTER_CONTROL_DEACTIVATE, 76 TRANSMITTER_CONTROL_ACTIAVATE, 77 TRANSMITTER_CONTROL_SETUP, 78 TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS, 79 /* ATOM_TRANSMITTER_ACTION_POWER_ON. This action is for eDP only 80 * (power up the panel) 81 */ 82 TRANSMITTER_CONTROL_POWER_ON, 83 /* ATOM_TRANSMITTER_ACTION_POWER_OFF. This action is for eDP only 84 * (power down the panel) 85 */ 86 TRANSMITTER_CONTROL_POWER_OFF 87 }; 88 89 enum bp_external_encoder_control_action { 90 EXTERNAL_ENCODER_CONTROL_DISABLE = 0, 91 EXTERNAL_ENCODER_CONTROL_ENABLE = 1, 92 EXTERNAL_ENCODER_CONTROL_INIT = 0x7, 93 EXTERNAL_ENCODER_CONTROL_SETUP = 0xf, 94 EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10, 95 EXTERNAL_ENCODER_CONTROL_BLANK = 0x11, 96 }; 97 98 enum bp_pipe_control_action { 99 ASIC_PIPE_DISABLE = 0, 100 ASIC_PIPE_ENABLE, 101 ASIC_PIPE_INIT 102 }; 103 104 enum bp_lvtma_control_action { 105 LVTMA_CONTROL_LCD_BLOFF = 2, 106 LVTMA_CONTROL_LCD_BLON = 3, 107 LVTMA_CONTROL_POWER_ON = 12, 108 LVTMA_CONTROL_POWER_OFF = 13 109 }; 110 111 struct bp_encoder_control { 112 enum bp_encoder_control_action action; 113 enum engine_id engine_id; 114 enum transmitter transmitter; 115 enum signal_type signal; 116 enum dc_lane_count lanes_number; 117 enum dc_color_depth color_depth; 118 bool enable_dp_audio; 119 uint32_t pixel_clock; /* khz */ 120 }; 121 122 struct bp_external_encoder_control { 123 enum bp_external_encoder_control_action action; 124 enum engine_id engine_id; 125 enum dc_link_rate link_rate; 126 enum dc_lane_count lanes_number; 127 enum signal_type signal; 128 enum dc_color_depth color_depth; 129 bool coherent; 130 struct graphics_object_id encoder_id; 131 struct graphics_object_id connector_obj_id; 132 uint32_t pixel_clock; /* in KHz */ 133 }; 134 135 struct bp_crtc_source_select { 136 enum engine_id engine_id; 137 enum controller_id controller_id; 138 /* from GPU Tx aka asic_signal */ 139 enum signal_type signal; 140 /* sink_signal may differ from asicSignal if Translator encoder */ 141 enum signal_type sink_signal; 142 enum display_output_bit_depth display_output_bit_depth; 143 bool enable_dp_audio; 144 }; 145 146 struct bp_transmitter_control { 147 enum bp_transmitter_control_action action; 148 enum engine_id engine_id; 149 enum transmitter transmitter; /* PhyId */ 150 enum dc_lane_count lanes_number; 151 enum clock_source_id pll_id; /* needed for DCE 4.0 */ 152 enum signal_type signal; 153 enum dc_color_depth color_depth; /* not used for DCE6.0 */ 154 enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */ 155 #if defined(CONFIG_DRM_AMD_DC_DCN) 156 enum tx_ffe_id txffe_sel; /* used for DCN3 */ 157 enum engine_id hpo_engine_id; /* used for DCN3 */ 158 #endif 159 struct graphics_object_id connector_obj_id; 160 /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should 161 * be pixel clock * deep_color_ratio (in KHz) 162 */ 163 uint32_t pixel_clock; 164 uint32_t lane_select; 165 uint32_t lane_settings; 166 bool coherent; 167 bool multi_path; 168 bool single_pll_mode; 169 }; 170 171 struct bp_hw_crtc_timing_parameters { 172 enum controller_id controller_id; 173 /* horizontal part */ 174 uint32_t h_total; 175 uint32_t h_addressable; 176 uint32_t h_overscan_left; 177 uint32_t h_overscan_right; 178 uint32_t h_sync_start; 179 uint32_t h_sync_width; 180 181 /* vertical part */ 182 uint32_t v_total; 183 uint32_t v_addressable; 184 uint32_t v_overscan_top; 185 uint32_t v_overscan_bottom; 186 uint32_t v_sync_start; 187 uint32_t v_sync_width; 188 189 struct timing_flags { 190 uint32_t INTERLACE:1; 191 uint32_t PIXEL_REPETITION:4; 192 uint32_t HSYNC_POSITIVE_POLARITY:1; 193 uint32_t VSYNC_POSITIVE_POLARITY:1; 194 uint32_t HORZ_COUNT_BY_TWO:1; 195 } flags; 196 }; 197 198 struct bp_adjust_pixel_clock_parameters { 199 /* Input: Signal Type - to be converted to Encoder mode */ 200 enum signal_type signal_type; 201 /* Input: Encoder object id */ 202 struct graphics_object_id encoder_object_id; 203 /* Input: Pixel Clock (requested Pixel clock based on Video timing 204 * standard used) in KHz 205 */ 206 uint32_t pixel_clock; 207 /* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */ 208 uint32_t adjusted_pixel_clock; 209 /* Output: If non-zero, this refDiv value should be used to calculate 210 * other ppll params */ 211 uint32_t reference_divider; 212 /* Output: If non-zero, this postDiv value should be used to calculate 213 * other ppll params */ 214 uint32_t pixel_clock_post_divider; 215 /* Input: Enable spread spectrum */ 216 bool ss_enable; 217 }; 218 219 struct bp_pixel_clock_parameters { 220 enum controller_id controller_id; /* (Which CRTC uses this PLL) */ 221 enum clock_source_id pll_id; /* Clock Source Id */ 222 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */ 223 enum signal_type signal_type; 224 /* Adjusted Pixel Clock (after VBIOS exec table) 225 * that becomes Target Pixel Clock (100 Hz units) */ 226 uint32_t target_pixel_clock_100hz; 227 /* Calculated Reference divider of Display PLL */ 228 uint32_t reference_divider; 229 /* Calculated Feedback divider of Display PLL */ 230 uint32_t feedback_divider; 231 /* Calculated Fractional Feedback divider of Display PLL */ 232 uint32_t fractional_feedback_divider; 233 /* Calculated Pixel Clock Post divider of Display PLL */ 234 uint32_t pixel_clock_post_divider; 235 struct graphics_object_id encoder_object_id; /* Encoder object id */ 236 /* VBIOS returns a fixed display clock when DFS-bypass feature 237 * is enabled (KHz) */ 238 uint32_t dfs_bypass_display_clock; 239 /* color depth to support HDMI deep color */ 240 enum transmitter_color_depth color_depth; 241 242 struct program_pixel_clock_flags { 243 uint32_t FORCE_PROGRAMMING_OF_PLL:1; 244 /* Use Engine Clock as source for Display Clock when 245 * programming PLL */ 246 uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1; 247 /* Use external reference clock (refDivSrc for PLL) */ 248 uint32_t SET_EXTERNAL_REF_DIV_SRC:1; 249 /* Use DFS bypass for Display clock. */ 250 uint32_t SET_DISPCLK_DFS_BYPASS:1; 251 /* Force program PHY PLL only */ 252 uint32_t PROGRAM_PHY_PLL_ONLY:1; 253 /* Support for YUV420 */ 254 uint32_t SUPPORT_YUV_420:1; 255 /* Use XTALIN reference clock source */ 256 uint32_t SET_XTALIN_REF_SRC:1; 257 /* Use GENLK reference clock source */ 258 uint32_t SET_GENLOCK_REF_DIV_SRC:1; 259 } flags; 260 }; 261 262 enum bp_dce_clock_type { 263 DCECLOCK_TYPE_DISPLAY_CLOCK = 0, 264 DCECLOCK_TYPE_DPREFCLK = 1 265 }; 266 267 /* DCE Clock Parameters structure for SetDceClock Exec command table */ 268 struct bp_set_dce_clock_parameters { 269 enum clock_source_id pll_id; /* Clock Source Id */ 270 /* Display clock or DPREFCLK value */ 271 uint32_t target_clock_frequency; 272 /* Clock to set: =0: DISPCLK =1: DPREFCLK =2: PIXCLK */ 273 enum bp_dce_clock_type clock_type; 274 275 struct set_dce_clock_flags { 276 uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1; 277 /* Use XTALIN reference clock source */ 278 uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1; 279 /* Use PCIE reference clock source */ 280 uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1; 281 /* Use GENLK reference clock source */ 282 uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1; 283 } flags; 284 }; 285 286 struct spread_spectrum_flags { 287 /* 1 = Center Spread; 0 = down spread */ 288 uint32_t CENTER_SPREAD:1; 289 /* 1 = external; 0 = internal */ 290 uint32_t EXTERNAL_SS:1; 291 /* 1 = delta-sigma type parameter; 0 = ver1 */ 292 uint32_t DS_TYPE:1; 293 }; 294 295 struct bp_spread_spectrum_parameters { 296 enum clock_source_id pll_id; 297 uint32_t percentage; 298 uint32_t ds_frac_amount; 299 300 union { 301 struct { 302 uint32_t step; 303 uint32_t delay; 304 uint32_t range; /* In Hz unit */ 305 } ver1; 306 struct { 307 uint32_t feedback_amount; 308 uint32_t nfrac_amount; 309 uint32_t ds_frac_size; 310 } ds; 311 }; 312 313 struct spread_spectrum_flags flags; 314 }; 315 316 struct bp_disp_connector_caps_info { 317 uint32_t INTERNAL_DISPLAY : 1; 318 uint32_t INTERNAL_DISPLAY_BL : 1; 319 }; 320 321 struct bp_encoder_cap_info { 322 uint32_t DP_HBR2_CAP:1; 323 uint32_t DP_HBR2_EN:1; 324 uint32_t DP_HBR3_EN:1; 325 uint32_t HDMI_6GB_EN:1; 326 uint32_t IS_DP2_CAPABLE:1; 327 uint32_t DP_UHBR10_EN:1; 328 uint32_t DP_UHBR13_5_EN:1; 329 uint32_t DP_UHBR20_EN:1; 330 uint32_t DP_IS_USB_C:1; 331 uint32_t RESERVED:27; 332 }; 333 334 struct bp_soc_bb_info { 335 uint32_t dram_clock_change_latency_100ns; 336 uint32_t dram_sr_exit_latency_100ns; 337 uint32_t dram_sr_enter_exit_latency_100ns; 338 }; 339 340 #endif /*__DAL_BIOS_PARSER_TYPES_H__ */ 341