1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_LINK_SERVICE_TYPES_H__ 27 #define __DAL_LINK_SERVICE_TYPES_H__ 28 29 #include "grph_object_id.h" 30 #include "dal_types.h" 31 #include "irq_types.h" 32 33 /*struct mst_mgr_callback_object;*/ 34 struct ddc; 35 struct irq_manager; 36 37 enum { 38 MAX_CONTROLLER_NUM = 6 39 }; 40 41 enum dp_power_state { 42 DP_POWER_STATE_D0 = 1, 43 DP_POWER_STATE_D3 44 }; 45 46 enum edp_revision { 47 /* eDP version 1.1 or lower */ 48 EDP_REVISION_11 = 0x00, 49 /* eDP version 1.2 */ 50 EDP_REVISION_12 = 0x01, 51 /* eDP version 1.3 */ 52 EDP_REVISION_13 = 0x02 53 }; 54 55 enum { 56 LINK_RATE_REF_FREQ_IN_KHZ = 27000, /*27MHz*/ 57 BITS_PER_DP_BYTE = 10, 58 DATA_EFFICIENCY_8b_10b_x10000 = 8000, /* 80% data efficiency */ 59 DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100 = 97, /* 97% data efficiency when FEC is enabled */ 60 DATA_EFFICIENCY_128b_132b_x10000 = 9646, /* 96.71% data efficiency x 99.75% downspread factor */ 61 }; 62 63 enum link_training_result { 64 LINK_TRAINING_SUCCESS, 65 LINK_TRAINING_CR_FAIL_LANE0, 66 LINK_TRAINING_CR_FAIL_LANE1, 67 LINK_TRAINING_CR_FAIL_LANE23, 68 /* CR DONE bit is cleared during EQ step */ 69 LINK_TRAINING_EQ_FAIL_CR, 70 /* other failure during EQ step */ 71 LINK_TRAINING_EQ_FAIL_EQ, 72 LINK_TRAINING_LQA_FAIL, 73 /* one of the CR,EQ or symbol lock is dropped */ 74 LINK_TRAINING_LINK_LOSS, 75 /* Abort link training (because sink unplugged) */ 76 LINK_TRAINING_ABORT, 77 #if defined(CONFIG_DRM_AMD_DC_DCN) 78 DP_128b_132b_LT_FAILED, 79 DP_128b_132b_MAX_LOOP_COUNT_REACHED, 80 DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT, 81 DP_128b_132b_CDS_DONE_TIMEOUT, 82 #endif 83 }; 84 85 enum lttpr_mode { 86 LTTPR_MODE_NON_LTTPR, 87 LTTPR_MODE_TRANSPARENT, 88 LTTPR_MODE_NON_TRANSPARENT, 89 }; 90 91 struct link_training_settings { 92 struct dc_link_settings link_settings; 93 94 /* TODO: turn lane settings below into mandatory fields 95 * as initial lane configuration 96 */ 97 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; 98 enum dc_voltage_swing *voltage_swing; 99 enum dc_pre_emphasis *pre_emphasis; 100 enum dc_post_cursor2 *post_cursor2; 101 bool should_set_fec_ready; 102 #if defined(CONFIG_DRM_AMD_DC_DCN) 103 /* TODO - factor lane_settings out because it changes during LT */ 104 union dc_dp_ffe_preset *ffe_preset; 105 #endif 106 107 uint16_t cr_pattern_time; 108 uint16_t eq_pattern_time; 109 uint16_t cds_pattern_time; 110 enum dc_dp_training_pattern pattern_for_cr; 111 enum dc_dp_training_pattern pattern_for_eq; 112 #if defined(CONFIG_DRM_AMD_DC_DCN) 113 enum dc_dp_training_pattern pattern_for_cds; 114 115 uint32_t eq_wait_time_limit; 116 uint8_t eq_loop_count_limit; 117 uint32_t cds_wait_time_limit; 118 #endif 119 120 bool enhanced_framing; 121 enum lttpr_mode lttpr_mode; 122 123 /* disallow different lanes to have different lane settings */ 124 bool disallow_per_lane_settings; 125 /* dpcd lane settings will always use the same hw lane settings 126 * even if it doesn't match requested lane adjust */ 127 bool always_match_dpcd_with_hw_lane_settings; 128 129 /***************************************************************** 130 * training states - parameters that can change in link training 131 *****************************************************************/ 132 /* TODO: Move hw_lane_settings and dpcd_lane_settings 133 * along with lane adjust, lane align, offset and all 134 * other training states into a new structure called 135 * training states, so link_training_settings becomes 136 * a constant input pre-decided prior to link training. 137 * 138 * The goal is to strictly decouple link training settings 139 * decision making process from link training states to 140 * prevent it from messy code practice of changing training 141 * decision on the fly. 142 */ 143 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX]; 144 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]; 145 }; 146 147 /*TODO: Move this enum test harness*/ 148 /* Test patterns*/ 149 enum dp_test_pattern { 150 /* Input data is pass through Scrambler 151 * and 8b10b Encoder straight to output*/ 152 DP_TEST_PATTERN_VIDEO_MODE = 0, 153 154 /* phy test patterns*/ 155 DP_TEST_PATTERN_PHY_PATTERN_BEGIN, 156 DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN, 157 DP_TEST_PATTERN_SYMBOL_ERROR, 158 DP_TEST_PATTERN_PRBS7, 159 DP_TEST_PATTERN_80BIT_CUSTOM, 160 DP_TEST_PATTERN_CP2520_1, 161 DP_TEST_PATTERN_CP2520_2, 162 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2, 163 DP_TEST_PATTERN_CP2520_3, 164 #if defined(CONFIG_DRM_AMD_DC_DCN) 165 DP_TEST_PATTERN_128b_132b_TPS1, 166 DP_TEST_PATTERN_128b_132b_TPS2, 167 DP_TEST_PATTERN_PRBS9, 168 DP_TEST_PATTERN_PRBS11, 169 DP_TEST_PATTERN_PRBS15, 170 DP_TEST_PATTERN_PRBS23, 171 DP_TEST_PATTERN_PRBS31, 172 DP_TEST_PATTERN_264BIT_CUSTOM, 173 DP_TEST_PATTERN_SQUARE_PULSE, 174 #endif 175 176 /* Link Training Patterns */ 177 DP_TEST_PATTERN_TRAINING_PATTERN1, 178 DP_TEST_PATTERN_TRAINING_PATTERN2, 179 DP_TEST_PATTERN_TRAINING_PATTERN3, 180 DP_TEST_PATTERN_TRAINING_PATTERN4, 181 #if defined(CONFIG_DRM_AMD_DC_DCN) 182 DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE, 183 DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE, 184 DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE, 185 #else 186 DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4, 187 #endif 188 189 /* link test patterns*/ 190 DP_TEST_PATTERN_COLOR_SQUARES, 191 DP_TEST_PATTERN_COLOR_SQUARES_CEA, 192 DP_TEST_PATTERN_VERTICAL_BARS, 193 DP_TEST_PATTERN_HORIZONTAL_BARS, 194 DP_TEST_PATTERN_COLOR_RAMP, 195 196 /* audio test patterns*/ 197 DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED, 198 DP_TEST_PATTERN_AUDIO_SAWTOOTH, 199 200 DP_TEST_PATTERN_UNSUPPORTED 201 }; 202 203 enum dp_test_pattern_color_space { 204 DP_TEST_PATTERN_COLOR_SPACE_RGB, 205 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601, 206 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709, 207 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED 208 }; 209 210 enum dp_panel_mode { 211 /* not required */ 212 DP_PANEL_MODE_DEFAULT, 213 /* standard mode for eDP */ 214 DP_PANEL_MODE_EDP, 215 /* external chips specific settings */ 216 DP_PANEL_MODE_SPECIAL 217 }; 218 219 enum dpcd_source_sequence { 220 DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG = 1, /*done in apply_single_controller_ctx_to_hw */ 221 DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR, /*done in core_link_enable_stream */ 222 DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME, /*done in core_link_enable_stream/dcn20_enable_stream */ 223 DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE, /*done in perform_link_training_with_retries/dcn20_enable_stream */ 224 DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY, /*done in dp_enable_link_phy */ 225 DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN, /*done in dp_set_hw_test_pattern */ 226 DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM, /*done in dce110_enable_audio_stream */ 227 DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM, /*done in enc1_stream_encoder_dp_unblank */ 228 DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM, /*done in enc1_stream_encoder_dp_blank */ 229 DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET, /*done in enc1_stream_encoder_dp_blank */ 230 DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM, /*done in dce110_disable_audio_stream */ 231 DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY, /*done in dp_disable_link_phy */ 232 DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE, /*done in dce110_disable_stream */ 233 }; 234 235 /* DPCD_ADDR_TRAINING_LANEx_SET registers value */ 236 union dpcd_training_lane_set { 237 struct { 238 #if defined(LITTLEENDIAN_CPU) 239 uint8_t VOLTAGE_SWING_SET:2; 240 uint8_t MAX_SWING_REACHED:1; 241 uint8_t PRE_EMPHASIS_SET:2; 242 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 243 /* following is reserved in DP 1.1 */ 244 uint8_t POST_CURSOR2_SET:2; 245 #elif defined(BIGENDIAN_CPU) 246 uint8_t POST_CURSOR2_SET:2; 247 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 248 uint8_t PRE_EMPHASIS_SET:2; 249 uint8_t MAX_SWING_REACHED:1; 250 uint8_t VOLTAGE_SWING_SET:2; 251 #else 252 #error ARCH not defined! 253 #endif 254 } bits; 255 256 uint8_t raw; 257 }; 258 259 260 /* DP MST stream allocation (payload bandwidth number) */ 261 struct dp_mst_stream_allocation { 262 uint8_t vcp_id; 263 /* number of slots required for the DP stream in 264 * transport packet */ 265 uint8_t slot_count; 266 }; 267 268 /* DP MST stream allocation table */ 269 struct dp_mst_stream_allocation_table { 270 /* number of DP video streams */ 271 int stream_count; 272 /* array of stream allocations */ 273 struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 274 }; 275 276 #endif /*__DAL_LINK_SERVICE_TYPES_H__*/ 277