1 /*
2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef STM32MP1_DEF_H
8 #define STM32MP1_DEF_H
9
10 #include <common/tbbr/tbbr_img_def.h>
11 #include <drivers/st/stm32mp1_rcc.h>
12 #include <dt-bindings/clock/stm32mp1-clks.h>
13 #include <dt-bindings/reset/stm32mp1-resets.h>
14 #include <lib/utils_def.h>
15 #include <lib/xlat_tables/xlat_tables_defs.h>
16
17 #ifndef __ASSEMBLER__
18 #include <drivers/st/bsec.h>
19 #include <drivers/st/stm32mp1_clk.h>
20
21 #include <boot_api.h>
22 #include <stm32mp_auth.h>
23 #include <stm32mp_common.h>
24 #include <stm32mp_dt.h>
25 #include <stm32mp_shres_helpers.h>
26 #include <stm32mp1_dbgmcu.h>
27 #include <stm32mp1_private.h>
28 #include <stm32mp1_shared_resources.h>
29 #endif
30
31 /*******************************************************************************
32 * CHIP ID
33 ******************************************************************************/
34 #define STM32MP1_CHIP_ID U(0x500)
35
36 #define STM32MP157C_PART_NB U(0x05000000)
37 #define STM32MP157A_PART_NB U(0x05000001)
38 #define STM32MP153C_PART_NB U(0x05000024)
39 #define STM32MP153A_PART_NB U(0x05000025)
40 #define STM32MP151C_PART_NB U(0x0500002E)
41 #define STM32MP151A_PART_NB U(0x0500002F)
42 #define STM32MP157F_PART_NB U(0x05000080)
43 #define STM32MP157D_PART_NB U(0x05000081)
44 #define STM32MP153F_PART_NB U(0x050000A4)
45 #define STM32MP153D_PART_NB U(0x050000A5)
46 #define STM32MP151F_PART_NB U(0x050000AE)
47 #define STM32MP151D_PART_NB U(0x050000AF)
48
49 #define STM32MP1_REV_B U(0x2000)
50 #define STM32MP1_REV_Z U(0x2001)
51
52 /*******************************************************************************
53 * PACKAGE ID
54 ******************************************************************************/
55 #define PKG_AA_LFBGA448 U(4)
56 #define PKG_AB_LFBGA354 U(3)
57 #define PKG_AC_TFBGA361 U(2)
58 #define PKG_AD_TFBGA257 U(1)
59
60 /*******************************************************************************
61 * STM32MP1 memory map related constants
62 ******************************************************************************/
63 #define STM32MP_ROM_BASE U(0x00000000)
64 #define STM32MP_ROM_SIZE U(0x00020000)
65
66 #define STM32MP_SYSRAM_BASE U(0x2FFC0000)
67 #define STM32MP_SYSRAM_SIZE U(0x00040000)
68
69 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
70 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
71 STM32MP_SYSRAM_SIZE - \
72 STM32MP_NS_SYSRAM_SIZE)
73
74 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE
75 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE
76
77 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
78 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \
79 STM32MP_NS_SYSRAM_SIZE)
80
81 /* DDR configuration */
82 #define STM32MP_DDR_BASE U(0xC0000000)
83 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
84 #ifdef AARCH32_SP_OPTEE
85 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
86 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
87 #else
88 #define STM32MP_DDR_S_SIZE U(0)
89 #define STM32MP_DDR_SHMEM_SIZE U(0)
90 #endif
91
92 /* DDR power initializations */
93 #ifndef __ASSEMBLER__
94 enum ddr_type {
95 STM32MP_DDR3,
96 STM32MP_LPDDR2,
97 STM32MP_LPDDR3
98 };
99 #endif
100
101 /* Section used inside TF binaries */
102 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
103 /* 256 Octets reserved for header */
104 #define STM32MP_HEADER_SIZE U(0x00000100)
105
106 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
107 STM32MP_PARAM_LOAD_SIZE + \
108 STM32MP_HEADER_SIZE)
109
110 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
111 (STM32MP_PARAM_LOAD_SIZE + \
112 STM32MP_HEADER_SIZE))
113
114 #ifdef AARCH32_SP_OPTEE
115 #define STM32MP_BL32_SIZE U(0)
116
117 #define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE
118
119 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \
120 STM32MP_OPTEE_BASE)
121 #else
122 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */
123 #endif
124
125 #define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \
126 STM32MP_SEC_SYSRAM_SIZE - \
127 STM32MP_BL32_SIZE)
128
129 #define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */
130
131 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
132 STM32MP_BL2_SIZE)
133
134 /* BL2 and BL32/sp_min require 4 tables */
135 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
136
137 /*
138 * MAX_MMAP_REGIONS is usually:
139 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
140 */
141 #if defined(IMAGE_BL2)
142 #define MAX_MMAP_REGIONS 11
143 #endif
144 #if defined(IMAGE_BL32)
145 #define MAX_MMAP_REGIONS 6
146 #endif
147
148 /* DTB initialization value */
149 #define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
150
151 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
152 STM32MP_DTB_SIZE)
153
154 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
155
156 /* Define maximum page size for NAND devices */
157 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
158
159 /*******************************************************************************
160 * STM32MP1 RAW partition offset for MTD devices
161 ******************************************************************************/
162 #define STM32MP_NOR_BL33_OFFSET U(0x00080000)
163 #ifdef AARCH32_SP_OPTEE
164 #define STM32MP_NOR_TEEH_OFFSET U(0x00280000)
165 #define STM32MP_NOR_TEED_OFFSET U(0x002C0000)
166 #define STM32MP_NOR_TEEX_OFFSET U(0x00300000)
167 #endif
168
169 #define STM32MP_NAND_BL33_OFFSET U(0x00200000)
170 #ifdef AARCH32_SP_OPTEE
171 #define STM32MP_NAND_TEEH_OFFSET U(0x00600000)
172 #define STM32MP_NAND_TEED_OFFSET U(0x00680000)
173 #define STM32MP_NAND_TEEX_OFFSET U(0x00700000)
174 #endif
175
176 /*******************************************************************************
177 * STM32MP1 device/io map related constants (used for MMU)
178 ******************************************************************************/
179 #define STM32MP1_DEVICE1_BASE U(0x40000000)
180 #define STM32MP1_DEVICE1_SIZE U(0x40000000)
181
182 #define STM32MP1_DEVICE2_BASE U(0x80000000)
183 #define STM32MP1_DEVICE2_SIZE U(0x40000000)
184
185 /*******************************************************************************
186 * STM32MP1 RCC
187 ******************************************************************************/
188 #define RCC_BASE U(0x50000000)
189
190 /*******************************************************************************
191 * STM32MP1 PWR
192 ******************************************************************************/
193 #define PWR_BASE U(0x50001000)
194
195 /*******************************************************************************
196 * STM32MP1 GPIO
197 ******************************************************************************/
198 #define GPIOA_BASE U(0x50002000)
199 #define GPIOB_BASE U(0x50003000)
200 #define GPIOC_BASE U(0x50004000)
201 #define GPIOD_BASE U(0x50005000)
202 #define GPIOE_BASE U(0x50006000)
203 #define GPIOF_BASE U(0x50007000)
204 #define GPIOG_BASE U(0x50008000)
205 #define GPIOH_BASE U(0x50009000)
206 #define GPIOI_BASE U(0x5000A000)
207 #define GPIOJ_BASE U(0x5000B000)
208 #define GPIOK_BASE U(0x5000C000)
209 #define GPIOZ_BASE U(0x54004000)
210 #define GPIO_BANK_OFFSET U(0x1000)
211
212 /* Bank IDs used in GPIO driver API */
213 #define GPIO_BANK_A U(0)
214 #define GPIO_BANK_B U(1)
215 #define GPIO_BANK_C U(2)
216 #define GPIO_BANK_D U(3)
217 #define GPIO_BANK_E U(4)
218 #define GPIO_BANK_F U(5)
219 #define GPIO_BANK_G U(6)
220 #define GPIO_BANK_H U(7)
221 #define GPIO_BANK_I U(8)
222 #define GPIO_BANK_J U(9)
223 #define GPIO_BANK_K U(10)
224 #define GPIO_BANK_Z U(25)
225
226 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8
227
228 /*******************************************************************************
229 * STM32MP1 UART
230 ******************************************************************************/
231 #define USART1_BASE U(0x5C000000)
232 #define USART2_BASE U(0x4000E000)
233 #define USART3_BASE U(0x4000F000)
234 #define UART4_BASE U(0x40010000)
235 #define UART5_BASE U(0x40011000)
236 #define USART6_BASE U(0x44003000)
237 #define UART7_BASE U(0x40018000)
238 #define UART8_BASE U(0x40019000)
239 #define STM32MP_UART_BAUDRATE U(115200)
240
241 /* For UART crash console */
242 #define STM32MP_DEBUG_USART_BASE UART4_BASE
243 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
244 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000
245 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
246 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
247 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
248 #define DEBUG_UART_TX_GPIO_PORT 11
249 #define DEBUG_UART_TX_GPIO_ALTERNATE 6
250 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
251 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
252 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
253 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
254
255 /*******************************************************************************
256 * STM32MP1 ETZPC
257 ******************************************************************************/
258 #define STM32MP1_ETZPC_BASE U(0x5C007000)
259
260 /* ETZPC TZMA IDs */
261 #define STM32MP1_ETZPC_TZMA_ROM U(0)
262 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
263
264 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
265
266 /* ETZPC DECPROT IDs */
267 #define STM32MP1_ETZPC_STGENC_ID 0
268 #define STM32MP1_ETZPC_BKPSRAM_ID 1
269 #define STM32MP1_ETZPC_IWDG1_ID 2
270 #define STM32MP1_ETZPC_USART1_ID 3
271 #define STM32MP1_ETZPC_SPI6_ID 4
272 #define STM32MP1_ETZPC_I2C4_ID 5
273 #define STM32MP1_ETZPC_RNG1_ID 7
274 #define STM32MP1_ETZPC_HASH1_ID 8
275 #define STM32MP1_ETZPC_CRYP1_ID 9
276 #define STM32MP1_ETZPC_DDRCTRL_ID 10
277 #define STM32MP1_ETZPC_DDRPHYC_ID 11
278 #define STM32MP1_ETZPC_I2C6_ID 12
279 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13
280
281 #define STM32MP1_ETZPC_TIM2_ID 16
282 #define STM32MP1_ETZPC_TIM3_ID 17
283 #define STM32MP1_ETZPC_TIM4_ID 18
284 #define STM32MP1_ETZPC_TIM5_ID 19
285 #define STM32MP1_ETZPC_TIM6_ID 20
286 #define STM32MP1_ETZPC_TIM7_ID 21
287 #define STM32MP1_ETZPC_TIM12_ID 22
288 #define STM32MP1_ETZPC_TIM13_ID 23
289 #define STM32MP1_ETZPC_TIM14_ID 24
290 #define STM32MP1_ETZPC_LPTIM1_ID 25
291 #define STM32MP1_ETZPC_WWDG1_ID 26
292 #define STM32MP1_ETZPC_SPI2_ID 27
293 #define STM32MP1_ETZPC_SPI3_ID 28
294 #define STM32MP1_ETZPC_SPDIFRX_ID 29
295 #define STM32MP1_ETZPC_USART2_ID 30
296 #define STM32MP1_ETZPC_USART3_ID 31
297 #define STM32MP1_ETZPC_UART4_ID 32
298 #define STM32MP1_ETZPC_UART5_ID 33
299 #define STM32MP1_ETZPC_I2C1_ID 34
300 #define STM32MP1_ETZPC_I2C2_ID 35
301 #define STM32MP1_ETZPC_I2C3_ID 36
302 #define STM32MP1_ETZPC_I2C5_ID 37
303 #define STM32MP1_ETZPC_CEC_ID 38
304 #define STM32MP1_ETZPC_DAC_ID 39
305 #define STM32MP1_ETZPC_UART7_ID 40
306 #define STM32MP1_ETZPC_UART8_ID 41
307 #define STM32MP1_ETZPC_MDIOS_ID 44
308 #define STM32MP1_ETZPC_TIM1_ID 48
309 #define STM32MP1_ETZPC_TIM8_ID 49
310 #define STM32MP1_ETZPC_USART6_ID 51
311 #define STM32MP1_ETZPC_SPI1_ID 52
312 #define STM32MP1_ETZPC_SPI4_ID 53
313 #define STM32MP1_ETZPC_TIM15_ID 54
314 #define STM32MP1_ETZPC_TIM16_ID 55
315 #define STM32MP1_ETZPC_TIM17_ID 56
316 #define STM32MP1_ETZPC_SPI5_ID 57
317 #define STM32MP1_ETZPC_SAI1_ID 58
318 #define STM32MP1_ETZPC_SAI2_ID 59
319 #define STM32MP1_ETZPC_SAI3_ID 60
320 #define STM32MP1_ETZPC_DFSDM_ID 61
321 #define STM32MP1_ETZPC_TT_FDCAN_ID 62
322 #define STM32MP1_ETZPC_LPTIM2_ID 64
323 #define STM32MP1_ETZPC_LPTIM3_ID 65
324 #define STM32MP1_ETZPC_LPTIM4_ID 66
325 #define STM32MP1_ETZPC_LPTIM5_ID 67
326 #define STM32MP1_ETZPC_SAI4_ID 68
327 #define STM32MP1_ETZPC_VREFBUF_ID 69
328 #define STM32MP1_ETZPC_DCMI_ID 70
329 #define STM32MP1_ETZPC_CRC2_ID 71
330 #define STM32MP1_ETZPC_ADC_ID 72
331 #define STM32MP1_ETZPC_HASH2_ID 73
332 #define STM32MP1_ETZPC_RNG2_ID 74
333 #define STM32MP1_ETZPC_CRYP2_ID 75
334 #define STM32MP1_ETZPC_SRAM1_ID 80
335 #define STM32MP1_ETZPC_SRAM2_ID 81
336 #define STM32MP1_ETZPC_SRAM3_ID 82
337 #define STM32MP1_ETZPC_SRAM4_ID 83
338 #define STM32MP1_ETZPC_RETRAM_ID 84
339 #define STM32MP1_ETZPC_OTG_ID 85
340 #define STM32MP1_ETZPC_SDMMC3_ID 86
341 #define STM32MP1_ETZPC_DLYBSD3_ID 87
342 #define STM32MP1_ETZPC_DMA1_ID 88
343 #define STM32MP1_ETZPC_DMA2_ID 89
344 #define STM32MP1_ETZPC_DMAMUX_ID 90
345 #define STM32MP1_ETZPC_FMC_ID 91
346 #define STM32MP1_ETZPC_QSPI_ID 92
347 #define STM32MP1_ETZPC_DLYBQ_ID 93
348 #define STM32MP1_ETZPC_ETH_ID 94
349 #define STM32MP1_ETZPC_RSV_ID 95
350
351 #define STM32MP_ETZPC_MAX_ID 96
352
353 /*******************************************************************************
354 * STM32MP1 TZC (TZ400)
355 ******************************************************************************/
356 #define STM32MP1_TZC_BASE U(0x5C006000)
357
358 #define STM32MP1_TZC_A7_ID U(0)
359 #define STM32MP1_TZC_M4_ID U(1)
360 #define STM32MP1_TZC_LCD_ID U(3)
361 #define STM32MP1_TZC_GPU_ID U(4)
362 #define STM32MP1_TZC_MDMA_ID U(5)
363 #define STM32MP1_TZC_DMA_ID U(6)
364 #define STM32MP1_TZC_USB_HOST_ID U(7)
365 #define STM32MP1_TZC_USB_OTG_ID U(8)
366 #define STM32MP1_TZC_SDMMC_ID U(9)
367 #define STM32MP1_TZC_ETH_ID U(10)
368 #define STM32MP1_TZC_DAP_ID U(15)
369
370 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \
371 TZC_400_REGION_ATTR_FILTER_BIT(1))
372
373 /*******************************************************************************
374 * STM32MP1 SDMMC
375 ******************************************************************************/
376 #define STM32MP_SDMMC1_BASE U(0x58005000)
377 #define STM32MP_SDMMC2_BASE U(0x58007000)
378 #define STM32MP_SDMMC3_BASE U(0x48004000)
379
380 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
381 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
382 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
383 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
384 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
385
386 /*******************************************************************************
387 * STM32MP1 BSEC / OTP
388 ******************************************************************************/
389 #define STM32MP1_OTP_MAX_ID 0x5FU
390 #define STM32MP1_UPPER_OTP_START 0x20U
391
392 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
393
394 /* OTP offsets */
395 #define DATA0_OTP U(0)
396 #define PART_NUMBER_OTP U(1)
397 #define NAND_OTP U(9)
398 #define PACKAGE_OTP U(16)
399 #define HW2_OTP U(18)
400
401 /* OTP mask */
402 /* DATA0 */
403 #define DATA0_OTP_SECURED BIT(6)
404
405 /* PART NUMBER */
406 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
407 #define PART_NUMBER_OTP_PART_SHIFT 0
408
409 /* PACKAGE */
410 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
411 #define PACKAGE_OTP_PKG_SHIFT 27
412
413 /* IWDG OTP */
414 #define HW2_OTP_IWDG_HW_POS U(3)
415 #define HW2_OTP_IWDG_FZ_STOP_POS U(5)
416 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
417
418 /* HW2 OTP */
419 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
420
421 /* NAND OTP */
422 /* NAND parameter storage flag */
423 #define NAND_PARAM_STORED_IN_OTP BIT(31)
424
425 /* NAND page size in bytes */
426 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
427 #define NAND_PAGE_SIZE_SHIFT 29
428 #define NAND_PAGE_SIZE_2K U(0)
429 #define NAND_PAGE_SIZE_4K U(1)
430 #define NAND_PAGE_SIZE_8K U(2)
431
432 /* NAND block size in pages */
433 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
434 #define NAND_BLOCK_SIZE_SHIFT 27
435 #define NAND_BLOCK_SIZE_64_PAGES U(0)
436 #define NAND_BLOCK_SIZE_128_PAGES U(1)
437 #define NAND_BLOCK_SIZE_256_PAGES U(2)
438
439 /* NAND number of block (in unit of 256 blocs) */
440 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
441 #define NAND_BLOCK_NB_SHIFT 19
442 #define NAND_BLOCK_NB_UNIT U(256)
443
444 /* NAND bus width in bits */
445 #define NAND_WIDTH_MASK BIT(18)
446 #define NAND_WIDTH_SHIFT 18
447
448 /* NAND number of ECC bits per 512 bytes */
449 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
450 #define NAND_ECC_BIT_NB_SHIFT 15
451 #define NAND_ECC_BIT_NB_UNSET U(0)
452 #define NAND_ECC_BIT_NB_1_BITS U(1)
453 #define NAND_ECC_BIT_NB_4_BITS U(2)
454 #define NAND_ECC_BIT_NB_8_BITS U(3)
455 #define NAND_ECC_ON_DIE U(4)
456
457 /* NAND number of planes */
458 #define NAND_PLANE_BIT_NB_MASK BIT(14)
459
460 /*******************************************************************************
461 * STM32MP1 TAMP
462 ******************************************************************************/
463 #define TAMP_BASE U(0x5C00A000)
464 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
465
466 #if !(defined(__LINKER__) || defined(__ASSEMBLER__))
tamp_bkpr(uint32_t idx)467 static inline uint32_t tamp_bkpr(uint32_t idx)
468 {
469 return TAMP_BKP_REGISTER_BASE + (idx << 2);
470 }
471 #endif
472
473 /*******************************************************************************
474 * STM32MP1 DDRCTRL
475 ******************************************************************************/
476 #define DDRCTRL_BASE U(0x5A003000)
477
478 /*******************************************************************************
479 * STM32MP1 DDRPHYC
480 ******************************************************************************/
481 #define DDRPHYC_BASE U(0x5A004000)
482
483 /*******************************************************************************
484 * STM32MP1 IWDG
485 ******************************************************************************/
486 #define IWDG_MAX_INSTANCE U(2)
487 #define IWDG1_INST U(0)
488 #define IWDG2_INST U(1)
489
490 #define IWDG1_BASE U(0x5C003000)
491 #define IWDG2_BASE U(0x5A002000)
492
493 /*******************************************************************************
494 * Miscellaneous STM32MP1 peripherals base address
495 ******************************************************************************/
496 #define BSEC_BASE U(0x5C005000)
497 #define CRYP1_BASE U(0x54001000)
498 #define DBGMCU_BASE U(0x50081000)
499 #define HASH1_BASE U(0x54002000)
500 #define I2C4_BASE U(0x5C002000)
501 #define I2C6_BASE U(0x5c009000)
502 #define RNG1_BASE U(0x54003000)
503 #define RTC_BASE U(0x5c004000)
504 #define SPI6_BASE U(0x5c001000)
505 #define STGEN_BASE U(0x5c008000)
506 #define SYSCFG_BASE U(0x50020000)
507
508 /*******************************************************************************
509 * Device Tree defines
510 ******************************************************************************/
511 #define DT_BSEC_COMPAT "st,stm32mp15-bsec"
512 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
513 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
514 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
515
516 #endif /* STM32MP1_DEF_H */
517