1 /* 2 * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef EMMC_STD_H 8 #define EMMC_STD_H 9 10 #include "emmc_hal.h" 11 12 #ifndef FALSE 13 #define FALSE 0U 14 #endif 15 #ifndef TRUE 16 #define TRUE 1U 17 #endif 18 19 /* 64bit registers */ 20 #define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v)) 21 #define GETR_64(r) (*(volatile uint64_t *)(r)) 22 23 /* 32bit registers */ 24 #define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v)) 25 #define GETR_32(r) (*(volatile uint32_t *)(r)) 26 27 /* 16bit registers */ 28 #define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v)) 29 #define GETR_16(r) (*(volatile uint16_t *)(r)) 30 31 /* 8bit registers */ 32 #define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v)) 33 #define GETR_8(r) (*(volatile uint8_t *)(r)) 34 35 /* CSD register Macros */ 36 #define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y))) 37 38 #define EMMC_CID_MID() (EMMC_GET_CID(127, 120)) 39 #define EMMC_CID_CBX() (EMMC_GET_CID(113, 112)) 40 #define EMMC_CID_OID() (EMMC_GET_CID(111, 104)) 41 #define EMMC_CID_PNM1() (EMMC_GET_CID(103, 88)) 42 #define EMMC_CID_PNM2() (EMMC_GET_CID(87, 56)) 43 #define EMMC_CID_PRV() (EMMC_GET_CID(55, 48)) 44 #define EMMC_CID_PSN() (EMMC_GET_CID(47, 16)) 45 #define EMMC_CID_MDT() (EMMC_GET_CID(15, 8)) 46 #define EMMC_CID_CRC() (EMMC_GET_CID(7, 1)) 47 48 /* CSD register Macros */ 49 #define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y))) 50 51 #define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127, 126)) 52 #define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125, 122)) 53 #define EMMC_CSD_TAAC() (EMMC_GET_CSD(119, 112)) 54 #define EMMC_CSD_NSAC() (EMMC_GET_CSD(111, 104)) 55 #define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103, 96)) 56 #define EMMC_CSD_CCC() (EMMC_GET_CSD(95, 84)) 57 #define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83, 80)) 58 #define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79, 79)) 59 #define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78, 78)) 60 #define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77, 77)) 61 #define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76, 76)) 62 #define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73, 62)) 63 #define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61, 59)) 64 #define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58, 56)) 65 #define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55, 53)) 66 #define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52, 50)) 67 #define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49, 47)) 68 #define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46, 42)) 69 #define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41, 37)) 70 #define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36, 32)) 71 #define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31, 31)) 72 #define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30, 29)) 73 #define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28, 26)) 74 #define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25, 22)) 75 #define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21, 21)) 76 #define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16, 16)) 77 #define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15, 15)) 78 #define EMMC_CSD_COPY() (EMMC_GET_CSD(14, 14)) 79 #define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13, 13)) 80 #define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12, 12)) 81 #define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11, 10)) 82 #define EMMC_CSD_ECC() (EMMC_GET_CSD(9, 8)) 83 #define EMMC_CSD_CRC() (EMMC_GET_CSD(7, 1)) 84 85 /* sector access */ 86 #define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003 87 #define EMMC_SECTOR_SIZE_SHIFT 9U /* 512 = 2^9 */ 88 #define EMMC_SECTOR_SIZE 512 89 #define EMMC_BLOCK_LENGTH 512 90 #define EMMC_BLOCK_LENGTH_DW 128 91 #define EMMC_BUF_SIZE_SHIFT 3U /* 8byte = 2^3 */ 92 93 /* eMMC specification clock */ 94 #define EMMC_CLOCK_SPEC_400K 400000UL /* initialize clock 400KHz */ 95 #define EMMC_CLOCK_SPEC_20M 20000000UL /* normal speed 20MHz */ 96 #define EMMC_CLOCK_SPEC_26M 26000000UL /* high speed 26MHz */ 97 #define EMMC_CLOCK_SPEC_52M 52000000UL /* high speed 52MHz */ 98 #define EMMC_CLOCK_SPEC_100M 100000000UL /* high speed 100MHz */ 99 100 /* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */ 101 typedef enum { 102 EMMC_ERR = 0, /* unknown error */ 103 EMMC_SUCCESS, /* OK */ 104 EMMC_ERR_FROM_DMAC, /* DMAC allocation error */ 105 EMMC_ERR_FROM_DMAC_TRANSFER, /* DMAC transfer error */ 106 EMMC_ERR_CARD_STATUS_BIT, /* card status error */ 107 EMMC_ERR_CMD_TIMEOUT, /* command timeout error */ 108 EMMC_ERR_DATA_TIMEOUT, /* data timeout error */ 109 EMMC_ERR_CMD_CRC, /* command CRC error */ 110 EMMC_ERR_DATA_CRC, /* data CRC error */ 111 EMMC_ERR_PARAM, /* parameter error */ 112 EMMC_ERR_RESPONSE, /* response error */ 113 EMMC_ERR_RESPONSE_BUSY, /* response busy error */ 114 EMMC_ERR_TRANSFER, /* data transfer error */ 115 EMMC_ERR_READ_SECTOR, /* read sector error */ 116 EMMC_ERR_WRITE_SECTOR, /* write sector error */ 117 EMMC_ERR_STATE, /* state error */ 118 EMMC_ERR_TIMEOUT, /* timeout error */ 119 EMMC_ERR_ILLEGAL_CARD, /* illegal card */ 120 EMMC_ERR_CARD_BUSY, /* Busy state */ 121 EMMC_ERR_CARD_STATE, /* card state error */ 122 EMMC_ERR_SET_TRACE, /* trace information error */ 123 EMMC_ERR_FROM_TIMER, /* Timer error */ 124 EMMC_ERR_FORCE_TERMINATE, /* Force terminate */ 125 EMMC_ERR_CARD_POWER, /* card power fail */ 126 EMMC_ERR_ERASE_SECTOR, /* erase sector error */ 127 EMMC_ERR_INFO2 /* exec cmd error info2 */ 128 } EMMC_ERROR_CODE; 129 130 /* Function number */ 131 #define EMMC_FUNCNO_NONE 0U 132 #define EMMC_FUNCNO_DRIVER_INIT 1U 133 #define EMMC_FUNCNO_CARD_POWER_ON 2U 134 #define EMMC_FUNCNO_MOUNT 3U 135 #define EMMC_FUNCNO_CARD_INIT 4U 136 #define EMMC_FUNCNO_HIGH_SPEED 5U 137 #define EMMC_FUNCNO_BUS_WIDTH 6U 138 #define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U 139 #define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U 140 #define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U 141 #define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U 142 #define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U 143 #define EMMC_FUNCNO_SET_CLOCK 12U 144 #define EMMC_FUNCNO_EXEC_CMD 13U 145 #define EMMC_FUNCNO_READ_SECTOR 14U 146 #define EMMC_FUNCNO_WRITE_SECTOR 15U 147 #define EMMC_FUNCNO_ERASE_SECTOR 16U 148 #define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U 149 /* 150 * Response 151 * R1 152 * Type 'E' bit and bit14(must be 0). ignore bit22 153 */ 154 #define EMMC_R1_ERROR_MASK 0xFDBFE080U 155 /* Ignore bit23 (Not check CRC error) */ 156 #define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) 157 #define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */ 158 #define EMMC_R1_READY 0x00000100U /* bit8 */ 159 #define EMMC_R1_STATE_SHIFT 9 160 161 /* R4 */ 162 #define EMMC_R4_RCA_MASK 0xFFFF0000UL 163 #define EMMC_R4_STATUS 0x00008000UL 164 165 /* CSD */ 166 #define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */ 167 #define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0 168 #define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */ 169 #define EMMC_TRANSPEED_MULT_SHIFT 3 170 171 /* OCR */ 172 #define EMMC_HOST_OCR_VALUE 0x40FF8080 173 #define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */ 174 #define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */ 175 #define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L 176 #define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L 177 178 /* EXT_CSD */ 179 #define EMMC_EXT_CSD_S_CMD_SET 504 180 #define EMMC_EXT_CSD_INI_TIMEOUT_AP 241 181 #define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239 182 #define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238 183 #define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235 184 #define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234 185 #define EMMC_EXT_CSD_TRIM_MULT 232 186 #define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231 187 #define EMMC_EXT_CSD_SEC_ERASE_MULT 229 188 #define EMMC_EXT_CSD_BOOT_INFO 228 189 #define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226 190 #define EMMC_EXT_CSD_ACC_SIZE 225 191 #define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224 192 #define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223 193 #define EMMC_EXT_CSD_PEL_WR_SEC_C 222 194 #define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221 195 #define EMMC_EXT_CSD_S_C_VCC 220 196 #define EMMC_EXT_CSD_S_C_VCCQ 219 197 #define EMMC_EXT_CSD_S_A_TIMEOUT 217 198 #define EMMC_EXT_CSD_SEC_COUNT 215 199 #define EMMC_EXT_CSD_MIN_PERF_W_8_52 210 200 #define EMMC_EXT_CSD_MIN_PERF_R_8_52 209 201 #define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208 202 #define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207 203 #define EMMC_EXT_CSD_MIN_PERF_W_4_26 206 204 #define EMMC_EXT_CSD_MIN_PERF_R_4_26 205 205 #define EMMC_EXT_CSD_PWR_CL_26_360 203 206 #define EMMC_EXT_CSD_PWR_CL_52_360 202 207 #define EMMC_EXT_CSD_PWR_CL_26_195 201 208 #define EMMC_EXT_CSD_PWR_CL_52_195 200 209 #define EMMC_EXT_CSD_CARD_TYPE 196 210 #define EMMC_EXT_CSD_CSD_STRUCTURE 194 211 #define EMMC_EXT_CSD_EXT_CSD_REV 192 212 #define EMMC_EXT_CSD_CMD_SET 191 213 #define EMMC_EXT_CSD_CMD_SET_REV 189 214 #define EMMC_EXT_CSD_POWER_CLASS 187 215 #define EMMC_EXT_CSD_HS_TIMING 185 216 #define EMMC_EXT_CSD_BUS_WIDTH 183 217 #define EMMC_EXT_CSD_ERASED_MEM_CONT 181 218 #define EMMC_EXT_CSD_PARTITION_CONFIG 179 219 #define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178 220 #define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177 221 #define EMMC_EXT_CSD_ERASE_GROUP_DEF 175 222 #define EMMC_EXT_CSD_BOOT_WP 173 223 #define EMMC_EXT_CSD_USER_WP 171 224 #define EMMC_EXT_CSD_FW_CONFIG 169 225 #define EMMC_EXT_CSD_RPMB_SIZE_MULT 168 226 #define EMMC_EXT_CSD_RST_n_FUNCTION 162 227 #define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160 228 #define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159 229 #define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156 230 #define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155 231 #define EMMC_EXT_CSD_GP_SIZE_MULT 154 232 #define EMMC_EXT_CSD_ENH_SIZE_MULT 142 233 #define EMMC_EXT_CSD_ENH_START_ADDR 139 234 #define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134 235 236 #define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01 237 #define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02 238 #define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04 239 #define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08 240 #define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e 241 242 /* SWITCH (CMD6) argument */ 243 #define EXTCSD_ACCESS_BYTE (BIT25 | BIT24) 244 #define EXTCSD_SET_BITS BIT24 245 246 #define HS_TIMING_ADD (185 << 16) /* H'b9 */ 247 #define HS_TIMING_1 (1 << 8) 248 #define HS_TIMING_HS200 (2 << 8) 249 #define HS_TIMING_HS400 (3 << 8) 250 251 #define BUS_WIDTH_ADD (183 << 16) /* H'b7 */ 252 #define BUS_WIDTH_1 (0 << 8) 253 #define BUS_WIDTH_4 (1 << 8) 254 #define BUS_WIDTH_8 (2 << 8) 255 #define BUS_WIDTH_4DDR (5 << 8) 256 #define BUS_WIDTH_8DDR (6 << 8) 257 258 #define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE | HS_TIMING_ADD |\ 259 HS_TIMING_1) /* H'03b90100 */ 260 #define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE |\ 261 HS_TIMING_ADD) /* H'03b90000 */ 262 263 #define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ 264 BUS_WIDTH_1) /* H'03b70000 */ 265 #define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ 266 BUS_WIDTH_4) /* H'03b70100 */ 267 #define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ 268 BUS_WIDTH_8) /* H'03b70200 */ 269 #define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ 270 BUS_WIDTH_4DDR) /* H'03b70500 */ 271 #define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ 272 BUS_WIDTH_8DDR) /* H'03b70600 */ 273 /* Partition config = 0x00 */ 274 #define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL 275 276 #define TIMING_HIGH_SPEED 1UL 277 #define EMMC_BOOT_PARTITION_EN_MASK 0x38U 278 #define EMMC_BOOT_PARTITION_EN_SHIFT 3U 279 280 /* Bus width */ 281 #define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT 282 #define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT 283 #define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT 284 285 /* for st_mmc_base */ 286 #define EMMC_MAX_RESPONSE_LENGTH 17 287 #define EMMC_MAX_CID_LENGTH 16 288 #define EMMC_MAX_CSD_LENGTH 16 289 #define EMMC_MAX_EXT_CSD_LENGTH 512U 290 #define EMMC_RES_REG_ALIGNED 4U 291 #define EMMC_BUF_REG_ALIGNED 8U 292 293 /* TAAC mask */ 294 #define TAAC_TIME_UNIT_MASK (0x07) 295 #define TAAC_MULTIPLIER_FACTOR_MASK (0x0F) 296 297 /* Partition id */ 298 typedef enum { 299 PARTITION_ID_USER = 0x0, /* User Area */ 300 PARTITION_ID_BOOT_1 = 0x1, /* boot partition 1 */ 301 PARTITION_ID_BOOT_2 = 0x2, /* boot partition 2 */ 302 PARTITION_ID_RPMB = 0x3, /* Replay Protected Memory Block */ 303 PARTITION_ID_GP_1 = 0x4, /* General Purpose partition 1 */ 304 PARTITION_ID_GP_2 = 0x5, /* General Purpose partition 2 */ 305 PARTITION_ID_GP_3 = 0x6, /* General Purpose partition 3 */ 306 PARTITION_ID_GP_4 = 0x7, /* General Purpose partition 4 */ 307 PARTITION_ID_MASK = 0x7 /* [2:0] */ 308 } EMMC_PARTITION_ID; 309 310 /* card state in R1 response [12:9] */ 311 typedef enum { 312 EMMC_R1_STATE_IDLE = 0, 313 EMMC_R1_STATE_READY, 314 EMMC_R1_STATE_IDENT, 315 EMMC_R1_STATE_STBY, 316 EMMC_R1_STATE_TRAN, 317 EMMC_R1_STATE_DATA, 318 EMMC_R1_STATE_RCV, 319 EMMC_R1_STATE_PRG, 320 EMMC_R1_STATE_DIS, 321 EMMC_R1_STATE_BTST, 322 EMMC_R1_STATE_SLEP 323 } EMMC_R1_STATE; 324 325 typedef enum { 326 ESTATE_BEGIN = 0, 327 ESTATE_ISSUE_CMD, 328 ESTATE_NON_RESP_CMD, 329 ESTATE_RCV_RESP, 330 ESTATE_RCV_RESPONSE_BUSY, 331 ESTATE_CHECK_RESPONSE_COMPLETE, 332 ESTATE_DATA_TRANSFER, 333 ESTATE_DATA_TRANSFER_COMPLETE, 334 ESTATE_ACCESS_END, 335 ESTATE_TRANSFER_ERROR, 336 ESTATE_ERROR, 337 ESTATE_END 338 } EMMC_INT_STATE; 339 340 /* eMMC boot driver error information */ 341 typedef struct { 342 uint16_t num; /* error no */ 343 uint16_t code; /* error code */ 344 345 volatile uint32_t info1; /* SD_INFO1. (hw dependent) */ 346 volatile uint32_t info2; /* SD_INFO2. (hw dependent) */ 347 volatile uint32_t status1; /* SD_ERR_STS1. (hw dependent) */ 348 volatile uint32_t status2; /* SD_ERR_STS2. (hw dependent) */ 349 volatile uint32_t dm_info1; /* DM_CM_INFO1. (hw dependent) */ 350 volatile uint32_t dm_info2; /* DM_CM_INFO2. (hw dependent) */ 351 } st_error_info; 352 353 /* Command information */ 354 typedef struct { 355 HAL_MEMCARD_COMMAND cmd; /* Command information */ 356 uint32_t arg; /* argument */ 357 HAL_MEMCARD_OPERATION dir; /* direction */ 358 uint32_t hw; /* SD_CMD register value. */ 359 } st_command_info; 360 361 /* MMC driver base */ 362 typedef struct { 363 st_error_info error_info; /* error information */ 364 st_command_info cmd_info; /* command information */ 365 366 /* for data transfer */ 367 uint32_t *buff_address_virtual; /* Dest or Src buff */ 368 uint32_t *buff_address_physical; /* Dest or Src buff */ 369 HAL_MEMCARD_DATA_WIDTH bus_width; /* bus width */ 370 371 uint32_t trans_size; /* transfer size for this command */ 372 uint32_t remain_size; /* remain size for this command */ 373 uint32_t response_length; /* response length for this command */ 374 uint32_t sector_size; /* sector_size */ 375 376 /* clock */ 377 uint32_t base_clock; /* MMC host controller clock */ 378 /* 379 * Max freq (Card Spec)[Hz]. It changes dynamically by CSD and 380 * EXT_CSD. 381 */ 382 uint32_t max_freq; 383 /* request freq [Hz] (400K, 26MHz, 52MHz, etc) */ 384 uint32_t request_freq; 385 /* current MMC clock[Hz] (the closest frequency supported by HW) */ 386 uint32_t current_freq; 387 388 /* state flag */ 389 /* presence status of the memory card */ 390 HAL_MEMCARD_PRESENCE_STATUS card_present; 391 392 uint32_t card_power_enable; 393 uint32_t clock_enable; 394 /* True : initialize complete. */ 395 uint32_t initialize; 396 /* True : sector access, FALSE : byte access */ 397 uint32_t access_mode; 398 /* True : mount complete. */ 399 uint32_t mount; 400 /* True : selected card. */ 401 uint32_t selected; 402 /* 0: DMA, 1:PIO */ 403 HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; 404 405 /* loaded ISSW image No. ISSW have copy image. */ 406 uint32_t image_num; 407 /* card state */ 408 EMMC_R1_STATE current_state; 409 /* True : during command processing */ 410 volatile uint32_t during_cmd_processing; 411 /* True : during transfer */ 412 volatile uint32_t during_transfer; 413 /* True : during transfer (DMA) */ 414 volatile uint32_t during_dma_transfer; 415 /* True : occurred DMAC error */ 416 volatile uint32_t dma_error_flag; 417 /* force terminate flag */ 418 volatile uint32_t force_terminate; 419 /* state machine blocking flag : True or False */ 420 volatile uint32_t state_machine_blocking; 421 /* True : get partition access processing */ 422 volatile uint32_t get_partition_access_flag; 423 424 EMMC_PARTITION_ID boot_partition_en; /* Boot partition */ 425 EMMC_PARTITION_ID partition_access; /* Current access partition */ 426 427 /* timeout */ 428 uint32_t hs_timing; 429 430 /* read and write data timeout */ 431 uint32_t data_timeout; 432 433 /* retry */ 434 uint32_t retries_after_fail; 435 436 /* interrupt */ 437 volatile uint32_t int_event1; /* interrupt SD_INFO1 Event */ 438 volatile uint32_t int_event2; /* interrupt SD_INFO2 Event */ 439 volatile uint32_t dm_event1; /* interrupt DM_CM_INFO1 Event */ 440 volatile uint32_t dm_event2; /* interrupt DM_CM_INFO2 Event */ 441 442 /* response */ 443 uint32_t *response; /* buffer ptr for executing command. */ 444 uint32_t r1_card_status; /* R1 response data */ 445 uint32_t r3_ocr; /* R3 response data */ 446 uint32_t r4_resp; /* R4 response data */ 447 uint32_t r5_resp; /* R5 response data */ 448 449 /* True : clock mode is low. (MMC clock = Max26MHz) */ 450 uint32_t low_clock_mode_enable; 451 452 uint32_t reserved2; 453 uint32_t reserved3; 454 uint32_t reserved4; 455 456 /* CSD registers (4byte align) */ 457 uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /* CSD */ 458 __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); 459 /* CID registers (4byte align) */ 460 uint8_t cid_data[EMMC_MAX_CID_LENGTH] /* CID */ 461 __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); 462 /* EXT CSD registers (8byte align) */ 463 uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /* EXT_CSD */ 464 __attribute__ ((aligned(EMMC_BUF_REG_ALIGNED))); 465 /* Response registers (4byte align) */ 466 uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /* other response */ 467 __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); 468 } st_mmc_base; 469 470 typedef int (*func) (void); 471 472 uint32_t emmc_get_csd_time(void); 473 474 #define MMC_DEBUG 475 #endif /* EMMC_STD_H */ 476