1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 - ARM Ltd
4  * Author: Marc Zyngier <marc.zyngier@arm.com>
5  */
6 
7 #ifndef __ASM_ESR_H
8 #define __ASM_ESR_H
9 
10 #include <asm/memory.h>
11 #include <asm/sysreg.h>
12 
13 #define ESR_ELx_EC_UNKNOWN	(0x00)
14 #define ESR_ELx_EC_WFx		(0x01)
15 /* Unallocated EC: 0x02 */
16 #define ESR_ELx_EC_CP15_32	(0x03)
17 #define ESR_ELx_EC_CP15_64	(0x04)
18 #define ESR_ELx_EC_CP14_MR	(0x05)
19 #define ESR_ELx_EC_CP14_LS	(0x06)
20 #define ESR_ELx_EC_FP_ASIMD	(0x07)
21 #define ESR_ELx_EC_CP10_ID	(0x08)	/* EL2 only */
22 #define ESR_ELx_EC_PAC		(0x09)	/* EL2 and above */
23 /* Unallocated EC: 0x0A - 0x0B */
24 #define ESR_ELx_EC_CP14_64	(0x0C)
25 #define ESR_ELx_EC_BTI		(0x0D)
26 #define ESR_ELx_EC_ILL		(0x0E)
27 /* Unallocated EC: 0x0F - 0x10 */
28 #define ESR_ELx_EC_SVC32	(0x11)
29 #define ESR_ELx_EC_HVC32	(0x12)	/* EL2 only */
30 #define ESR_ELx_EC_SMC32	(0x13)	/* EL2 and above */
31 /* Unallocated EC: 0x14 */
32 #define ESR_ELx_EC_SVC64	(0x15)
33 #define ESR_ELx_EC_HVC64	(0x16)	/* EL2 and above */
34 #define ESR_ELx_EC_SMC64	(0x17)	/* EL2 and above */
35 #define ESR_ELx_EC_SYS64	(0x18)
36 #define ESR_ELx_EC_SVE		(0x19)
37 #define ESR_ELx_EC_ERET		(0x1a)	/* EL2 only */
38 /* Unallocated EC: 0x1B */
39 #define ESR_ELx_EC_FPAC		(0x1C)	/* EL1 and above */
40 /* Unallocated EC: 0x1D - 0x1E */
41 #define ESR_ELx_EC_IMP_DEF	(0x1f)	/* EL3 only */
42 #define ESR_ELx_EC_IABT_LOW	(0x20)
43 #define ESR_ELx_EC_IABT_CUR	(0x21)
44 #define ESR_ELx_EC_PC_ALIGN	(0x22)
45 /* Unallocated EC: 0x23 */
46 #define ESR_ELx_EC_DABT_LOW	(0x24)
47 #define ESR_ELx_EC_DABT_CUR	(0x25)
48 #define ESR_ELx_EC_SP_ALIGN	(0x26)
49 /* Unallocated EC: 0x27 */
50 #define ESR_ELx_EC_FP_EXC32	(0x28)
51 /* Unallocated EC: 0x29 - 0x2B */
52 #define ESR_ELx_EC_FP_EXC64	(0x2C)
53 /* Unallocated EC: 0x2D - 0x2E */
54 #define ESR_ELx_EC_SERROR	(0x2F)
55 #define ESR_ELx_EC_BREAKPT_LOW	(0x30)
56 #define ESR_ELx_EC_BREAKPT_CUR	(0x31)
57 #define ESR_ELx_EC_SOFTSTP_LOW	(0x32)
58 #define ESR_ELx_EC_SOFTSTP_CUR	(0x33)
59 #define ESR_ELx_EC_WATCHPT_LOW	(0x34)
60 #define ESR_ELx_EC_WATCHPT_CUR	(0x35)
61 /* Unallocated EC: 0x36 - 0x37 */
62 #define ESR_ELx_EC_BKPT32	(0x38)
63 /* Unallocated EC: 0x39 */
64 #define ESR_ELx_EC_VECTOR32	(0x3A)	/* EL2 only */
65 /* Unallocated EC: 0x3B */
66 #define ESR_ELx_EC_BRK64	(0x3C)
67 /* Unallocated EC: 0x3D - 0x3F */
68 #define ESR_ELx_EC_MAX		(0x3F)
69 
70 #define ESR_ELx_EC_SHIFT	(26)
71 #define ESR_ELx_EC_WIDTH	(6)
72 #define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
73 #define ESR_ELx_EC(esr)		(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
74 
75 #define ESR_ELx_IL_SHIFT	(25)
76 #define ESR_ELx_IL		(UL(1) << ESR_ELx_IL_SHIFT)
77 #define ESR_ELx_ISS_MASK	(ESR_ELx_IL - 1)
78 
79 /* ISS field definitions shared by different classes */
80 #define ESR_ELx_WNR_SHIFT	(6)
81 #define ESR_ELx_WNR		(UL(1) << ESR_ELx_WNR_SHIFT)
82 
83 /* Asynchronous Error Type */
84 #define ESR_ELx_IDS_SHIFT	(24)
85 #define ESR_ELx_IDS		(UL(1) << ESR_ELx_IDS_SHIFT)
86 #define ESR_ELx_AET_SHIFT	(10)
87 #define ESR_ELx_AET		(UL(0x7) << ESR_ELx_AET_SHIFT)
88 
89 #define ESR_ELx_AET_UC		(UL(0) << ESR_ELx_AET_SHIFT)
90 #define ESR_ELx_AET_UEU		(UL(1) << ESR_ELx_AET_SHIFT)
91 #define ESR_ELx_AET_UEO		(UL(2) << ESR_ELx_AET_SHIFT)
92 #define ESR_ELx_AET_UER		(UL(3) << ESR_ELx_AET_SHIFT)
93 #define ESR_ELx_AET_CE		(UL(6) << ESR_ELx_AET_SHIFT)
94 
95 /* Shared ISS field definitions for Data/Instruction aborts */
96 #define ESR_ELx_SET_SHIFT	(11)
97 #define ESR_ELx_SET_MASK	(UL(3) << ESR_ELx_SET_SHIFT)
98 #define ESR_ELx_FnV_SHIFT	(10)
99 #define ESR_ELx_FnV		(UL(1) << ESR_ELx_FnV_SHIFT)
100 #define ESR_ELx_EA_SHIFT	(9)
101 #define ESR_ELx_EA		(UL(1) << ESR_ELx_EA_SHIFT)
102 #define ESR_ELx_S1PTW_SHIFT	(7)
103 #define ESR_ELx_S1PTW		(UL(1) << ESR_ELx_S1PTW_SHIFT)
104 
105 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
106 #define ESR_ELx_FSC		(0x3F)
107 #define ESR_ELx_FSC_TYPE	(0x3C)
108 #define ESR_ELx_FSC_LEVEL	(0x03)
109 #define ESR_ELx_FSC_EXTABT	(0x10)
110 #define ESR_ELx_FSC_MTE		(0x11)
111 #define ESR_ELx_FSC_SERROR	(0x11)
112 #define ESR_ELx_FSC_ACCESS	(0x08)
113 #define ESR_ELx_FSC_FAULT	(0x04)
114 #define ESR_ELx_FSC_PERM	(0x0C)
115 
116 /* ISS field definitions for Data Aborts */
117 #define ESR_ELx_ISV_SHIFT	(24)
118 #define ESR_ELx_ISV		(UL(1) << ESR_ELx_ISV_SHIFT)
119 #define ESR_ELx_SAS_SHIFT	(22)
120 #define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)
121 #define ESR_ELx_SSE_SHIFT	(21)
122 #define ESR_ELx_SSE		(UL(1) << ESR_ELx_SSE_SHIFT)
123 #define ESR_ELx_SRT_SHIFT	(16)
124 #define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)
125 #define ESR_ELx_SF_SHIFT	(15)
126 #define ESR_ELx_SF 		(UL(1) << ESR_ELx_SF_SHIFT)
127 #define ESR_ELx_AR_SHIFT	(14)
128 #define ESR_ELx_AR 		(UL(1) << ESR_ELx_AR_SHIFT)
129 #define ESR_ELx_CM_SHIFT	(8)
130 #define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
131 
132 /* ISS field definitions for exceptions taken in to Hyp */
133 #define ESR_ELx_CV		(UL(1) << 24)
134 #define ESR_ELx_COND_SHIFT	(20)
135 #define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
136 #define ESR_ELx_WFx_ISS_TI	(UL(1) << 0)
137 #define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)
138 #define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
139 #define ESR_ELx_xVC_IMM_MASK	((1UL << 16) - 1)
140 
141 #define DISR_EL1_IDS		(UL(1) << 24)
142 /*
143  * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
144  * different things in the future...
145  */
146 #define DISR_EL1_ESR_MASK	(ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
147 
148 /* ESR value templates for specific events */
149 #define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)
150 #define ESR_ELx_WFx_WFI_VAL	((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) |	\
151 				 ESR_ELx_WFx_ISS_WFI)
152 
153 /* BRK instruction trap from AArch64 state */
154 #define ESR_ELx_BRK64_ISS_COMMENT_MASK	0xffff
155 
156 /* ISS field definitions for System instruction traps */
157 #define ESR_ELx_SYS64_ISS_RES0_SHIFT	22
158 #define ESR_ELx_SYS64_ISS_RES0_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
159 #define ESR_ELx_SYS64_ISS_DIR_MASK	0x1
160 #define ESR_ELx_SYS64_ISS_DIR_READ	0x1
161 #define ESR_ELx_SYS64_ISS_DIR_WRITE	0x0
162 
163 #define ESR_ELx_SYS64_ISS_RT_SHIFT	5
164 #define ESR_ELx_SYS64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
165 #define ESR_ELx_SYS64_ISS_CRM_SHIFT	1
166 #define ESR_ELx_SYS64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
167 #define ESR_ELx_SYS64_ISS_CRN_SHIFT	10
168 #define ESR_ELx_SYS64_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
169 #define ESR_ELx_SYS64_ISS_OP1_SHIFT	14
170 #define ESR_ELx_SYS64_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
171 #define ESR_ELx_SYS64_ISS_OP2_SHIFT	17
172 #define ESR_ELx_SYS64_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
173 #define ESR_ELx_SYS64_ISS_OP0_SHIFT	20
174 #define ESR_ELx_SYS64_ISS_OP0_MASK	(UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
175 #define ESR_ELx_SYS64_ISS_SYS_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
176 					 ESR_ELx_SYS64_ISS_OP1_MASK | \
177 					 ESR_ELx_SYS64_ISS_OP2_MASK | \
178 					 ESR_ELx_SYS64_ISS_CRN_MASK | \
179 					 ESR_ELx_SYS64_ISS_CRM_MASK)
180 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
181 					(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
182 					 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
183 					 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
184 					 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
185 					 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
186 
187 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \
188 					 ESR_ELx_SYS64_ISS_DIR_MASK)
189 #define ESR_ELx_SYS64_ISS_RT(esr) \
190 	(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
191 /*
192  * User space cache operations have the following sysreg encoding
193  * in System instructions.
194  * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
195  */
196 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC	14
197 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP	13
198 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP	12
199 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU	11
200 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC	10
201 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU	5
202 
203 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
204 						 ESR_ELx_SYS64_ISS_OP1_MASK | \
205 						 ESR_ELx_SYS64_ISS_OP2_MASK | \
206 						 ESR_ELx_SYS64_ISS_CRN_MASK | \
207 						 ESR_ELx_SYS64_ISS_DIR_MASK)
208 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
209 				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
210 				 ESR_ELx_SYS64_ISS_DIR_WRITE)
211 /*
212  * User space MRS operations which are supported for emulation
213  * have the following sysreg encoding in System instructions.
214  * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
215  */
216 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
217 						 ESR_ELx_SYS64_ISS_OP1_MASK | \
218 						 ESR_ELx_SYS64_ISS_CRN_MASK | \
219 						 ESR_ELx_SYS64_ISS_DIR_MASK)
220 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
221 				(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
222 				 ESR_ELx_SYS64_ISS_DIR_READ)
223 
224 #define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
225 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ	(ESR_ELx_SYS64_ISS_SYS_CTR | \
226 					 ESR_ELx_SYS64_ISS_DIR_READ)
227 
228 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
229 					 ESR_ELx_SYS64_ISS_DIR_READ)
230 
231 #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
232 					 ESR_ELx_SYS64_ISS_DIR_READ)
233 
234 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
235 					 ESR_ELx_SYS64_ISS_DIR_READ)
236 
237 #define esr_sys64_to_sysreg(e)					\
238 	sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >>		\
239 		 ESR_ELx_SYS64_ISS_OP0_SHIFT),			\
240 		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
241 		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
242 		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
243 		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
244 		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
245 		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
246 		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
247 		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
248 
249 #define esr_cp15_to_sysreg(e)					\
250 	sys_reg(3,						\
251 		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
252 		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
253 		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
254 		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
255 		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
256 		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
257 		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
258 		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
259 
260 /*
261  * ISS field definitions for floating-point exception traps
262  * (FP_EXC_32/FP_EXC_64).
263  *
264  * (The FPEXC_* constants are used instead for common bits.)
265  */
266 
267 #define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)
268 
269 /*
270  * ISS field definitions for CP15 accesses
271  */
272 #define ESR_ELx_CP15_32_ISS_DIR_MASK	0x1
273 #define ESR_ELx_CP15_32_ISS_DIR_READ	0x1
274 #define ESR_ELx_CP15_32_ISS_DIR_WRITE	0x0
275 
276 #define ESR_ELx_CP15_32_ISS_RT_SHIFT	5
277 #define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
278 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1
279 #define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
280 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT	10
281 #define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
282 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT	14
283 #define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
284 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT	17
285 #define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
286 
287 #define ESR_ELx_CP15_32_ISS_SYS_MASK	(ESR_ELx_CP15_32_ISS_OP1_MASK | \
288 					 ESR_ELx_CP15_32_ISS_OP2_MASK | \
289 					 ESR_ELx_CP15_32_ISS_CRN_MASK | \
290 					 ESR_ELx_CP15_32_ISS_CRM_MASK | \
291 					 ESR_ELx_CP15_32_ISS_DIR_MASK)
292 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
293 					(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
294 					 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
295 					 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
296 					 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
297 
298 #define ESR_ELx_CP15_64_ISS_DIR_MASK	0x1
299 #define ESR_ELx_CP15_64_ISS_DIR_READ	0x1
300 #define ESR_ELx_CP15_64_ISS_DIR_WRITE	0x0
301 
302 #define ESR_ELx_CP15_64_ISS_RT_SHIFT	5
303 #define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
304 
305 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT	10
306 #define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
307 
308 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT	16
309 #define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
310 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1
311 #define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
312 
313 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
314 					(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
315 					 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
316 
317 #define ESR_ELx_CP15_64_ISS_SYS_MASK	(ESR_ELx_CP15_64_ISS_OP1_MASK |	\
318 					 ESR_ELx_CP15_64_ISS_CRM_MASK | \
319 					 ESR_ELx_CP15_64_ISS_DIR_MASK)
320 
321 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
322 					 ESR_ELx_CP15_64_ISS_DIR_READ)
323 
324 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
325 					 ESR_ELx_CP15_64_ISS_DIR_READ)
326 
327 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ	(ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
328 					 ESR_ELx_CP15_32_ISS_DIR_READ)
329 
330 #ifndef __ASSEMBLY__
331 #include <asm/types.h>
332 
esr_is_data_abort(u32 esr)333 static inline bool esr_is_data_abort(u32 esr)
334 {
335 	const u32 ec = ESR_ELx_EC(esr);
336 
337 	return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
338 }
339 
340 const char *esr_get_class_string(u32 esr);
341 #endif /* __ASSEMBLY */
342 
343 #endif /* __ASM_ESR_H */
344