1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
4  * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
5  * Copyright (C) 1999 SuSE GmbH
6  * Copyright (C) 2021 Helge Deller <deller@gmx.de>
7  */
8 
9 #ifndef _PARISC_ASSEMBLY_H
10 #define _PARISC_ASSEMBLY_H
11 
12 #ifdef CONFIG_64BIT
13 #define RP_OFFSET	16
14 #define FRAME_SIZE	128
15 #define CALLEE_REG_FRAME_SIZE	144
16 #define REG_SZ		8
17 #define ASM_ULONG_INSN	.dword
18 #else	/* CONFIG_64BIT */
19 #define RP_OFFSET	20
20 #define FRAME_SIZE	64
21 #define CALLEE_REG_FRAME_SIZE	128
22 #define REG_SZ		4
23 #define ASM_ULONG_INSN	.word
24 #endif
25 
26 /* Frame alignment for 32- and 64-bit */
27 #define FRAME_ALIGN     64
28 
29 #define CALLEE_FLOAT_FRAME_SIZE	80
30 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
31 
32 #ifdef CONFIG_PA20
33 #define LDCW		ldcw,co
34 #define BL		b,l
35 # ifdef CONFIG_64BIT
36 #  define PA_ASM_LEVEL	2.0w
37 # else
38 #  define PA_ASM_LEVEL	2.0
39 # endif
40 #else
41 #define LDCW		ldcw
42 #define BL		bl
43 #define PA_ASM_LEVEL	1.1
44 #endif
45 
46 /* Privilege level field in the rightmost two bits of the IA queues */
47 #define PRIV_USER	3
48 #define PRIV_KERNEL	0
49 
50 #ifdef __ASSEMBLY__
51 
52 #ifdef CONFIG_64BIT
53 #define LDREG	ldd
54 #define STREG	std
55 #define LDREGX  ldd,s
56 #define LDREGM	ldd,mb
57 #define STREGM	std,ma
58 #define SHRREG	shrd
59 #define SHLREG	shld
60 #define ANDCM   andcm,*
61 #define	COND(x)	* ## x
62 #else	/* CONFIG_64BIT */
63 #define LDREG	ldw
64 #define STREG	stw
65 #define LDREGX  ldwx,s
66 #define LDREGM	ldwm
67 #define STREGM	stwm
68 #define SHRREG	shr
69 #define SHLREG	shlw
70 #define ANDCM   andcm
71 #define COND(x)	x
72 #endif
73 
74 #ifdef CONFIG_64BIT
75 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
76  * work around that for now... */
77 	.level 2.0w
78 #endif
79 
80 #include <asm/asm-offsets.h>
81 #include <asm/page.h>
82 #include <asm/types.h>
83 
84 #include <asm/asmregs.h>
85 #include <asm/psw.h>
86 
87 	sp	=	30
88 	gp	=	27
89 	ipsw	=	22
90 
91 	/*
92 	 * We provide two versions of each macro to convert from physical
93 	 * to virtual and vice versa. The "_r1" versions take one argument
94 	 * register, but trashes r1 to do the conversion. The other
95 	 * version takes two arguments: a src and destination register.
96 	 * However, the source and destination registers can not be
97 	 * the same register.
98 	 */
99 
100 	.macro  tophys  grvirt, grphys
101 	ldil    L%(__PAGE_OFFSET), \grphys
102 	sub     \grvirt, \grphys, \grphys
103 	.endm
104 
105 	.macro  tovirt  grphys, grvirt
106 	ldil    L%(__PAGE_OFFSET), \grvirt
107 	add     \grphys, \grvirt, \grvirt
108 	.endm
109 
110 	.macro  tophys_r1  gr
111 	ldil    L%(__PAGE_OFFSET), %r1
112 	sub     \gr, %r1, \gr
113 	.endm
114 
115 	.macro  tovirt_r1  gr
116 	ldil    L%(__PAGE_OFFSET), %r1
117 	add     \gr, %r1, \gr
118 	.endm
119 
120 	.macro delay value
121 	ldil	L%\value, 1
122 	ldo	R%\value(1), 1
123 	addib,UV,n -1,1,.
124 	addib,NUV,n -1,1,.+8
125 	nop
126 	.endm
127 
128 	.macro	debug value
129 	.endm
130 
131 	.macro shlw r, sa, t
132 	zdep	\r, 31-(\sa), 32-(\sa), \t
133 	.endm
134 
135 	/* And the PA 2.0W shift left */
136 	.macro shld r, sa, t
137 	depd,z	\r, 63-(\sa), 64-(\sa), \t
138 	.endm
139 
140 	/* Shift Right - note the r and t can NOT be the same! */
141 	.macro shr r, sa, t
142 	extru \r, 31-(\sa), 32-(\sa), \t
143 	.endm
144 
145 	/* pa20w version of shift right */
146 	.macro shrd r, sa, t
147 	extrd,u \r, 63-(\sa), 64-(\sa), \t
148 	.endm
149 
150 	/* Extract unsigned for 32- and 64-bit
151 	 * The extru instruction leaves the most significant 32 bits of the
152 	 * target register in an undefined state on PA 2.0 systems. */
153 	.macro extru_safe r, p, len, t
154 #ifdef CONFIG_64BIT
155 	extrd,u	\r, 32+(\p), \len, \t
156 #else
157 	extru	\r, \p, \len, \t
158 #endif
159 	.endm
160 
161 	/* load 32-bit 'value' into 'reg' compensating for the ldil
162 	 * sign-extension when running in wide mode.
163 	 * WARNING!! neither 'value' nor 'reg' can be expressions
164 	 * containing '.'!!!! */
165 	.macro	load32 value, reg
166 	ldil	L%\value, \reg
167 	ldo	R%\value(\reg), \reg
168 	.endm
169 
170 	.macro loadgp
171 #ifdef CONFIG_64BIT
172 	ldil		L%__gp, %r27
173 	ldo		R%__gp(%r27), %r27
174 #else
175 	ldil		L%$global$, %r27
176 	ldo		R%$global$(%r27), %r27
177 #endif
178 	.endm
179 
180 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
181 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
182 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
183 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
184 
185 	.macro	save_general	regs
186 	STREG %r1, PT_GR1 (\regs)
187 	STREG %r2, PT_GR2 (\regs)
188 	STREG %r3, PT_GR3 (\regs)
189 	STREG %r4, PT_GR4 (\regs)
190 	STREG %r5, PT_GR5 (\regs)
191 	STREG %r6, PT_GR6 (\regs)
192 	STREG %r7, PT_GR7 (\regs)
193 	STREG %r8, PT_GR8 (\regs)
194 	STREG %r9, PT_GR9 (\regs)
195 	STREG %r10, PT_GR10(\regs)
196 	STREG %r11, PT_GR11(\regs)
197 	STREG %r12, PT_GR12(\regs)
198 	STREG %r13, PT_GR13(\regs)
199 	STREG %r14, PT_GR14(\regs)
200 	STREG %r15, PT_GR15(\regs)
201 	STREG %r16, PT_GR16(\regs)
202 	STREG %r17, PT_GR17(\regs)
203 	STREG %r18, PT_GR18(\regs)
204 	STREG %r19, PT_GR19(\regs)
205 	STREG %r20, PT_GR20(\regs)
206 	STREG %r21, PT_GR21(\regs)
207 	STREG %r22, PT_GR22(\regs)
208 	STREG %r23, PT_GR23(\regs)
209 	STREG %r24, PT_GR24(\regs)
210 	STREG %r25, PT_GR25(\regs)
211 	/* r26 is saved in get_stack and used to preserve a value across virt_map */
212 	STREG %r27, PT_GR27(\regs)
213 	STREG %r28, PT_GR28(\regs)
214 	/* r29 is saved in get_stack and used to point to saved registers */
215 	/* r30 stack pointer saved in get_stack */
216 	STREG %r31, PT_GR31(\regs)
217 	.endm
218 
219 	.macro	rest_general	regs
220 	/* r1 used as a temp in rest_stack and is restored there */
221 	LDREG PT_GR2 (\regs), %r2
222 	LDREG PT_GR3 (\regs), %r3
223 	LDREG PT_GR4 (\regs), %r4
224 	LDREG PT_GR5 (\regs), %r5
225 	LDREG PT_GR6 (\regs), %r6
226 	LDREG PT_GR7 (\regs), %r7
227 	LDREG PT_GR8 (\regs), %r8
228 	LDREG PT_GR9 (\regs), %r9
229 	LDREG PT_GR10(\regs), %r10
230 	LDREG PT_GR11(\regs), %r11
231 	LDREG PT_GR12(\regs), %r12
232 	LDREG PT_GR13(\regs), %r13
233 	LDREG PT_GR14(\regs), %r14
234 	LDREG PT_GR15(\regs), %r15
235 	LDREG PT_GR16(\regs), %r16
236 	LDREG PT_GR17(\regs), %r17
237 	LDREG PT_GR18(\regs), %r18
238 	LDREG PT_GR19(\regs), %r19
239 	LDREG PT_GR20(\regs), %r20
240 	LDREG PT_GR21(\regs), %r21
241 	LDREG PT_GR22(\regs), %r22
242 	LDREG PT_GR23(\regs), %r23
243 	LDREG PT_GR24(\regs), %r24
244 	LDREG PT_GR25(\regs), %r25
245 	LDREG PT_GR26(\regs), %r26
246 	LDREG PT_GR27(\regs), %r27
247 	LDREG PT_GR28(\regs), %r28
248 	/* r29 points to register save area, and is restored in rest_stack */
249 	/* r30 stack pointer restored in rest_stack */
250 	LDREG PT_GR31(\regs), %r31
251 	.endm
252 
253 	.macro	save_fp 	regs
254 	fstd,ma  %fr0, 8(\regs)
255 	fstd,ma	 %fr1, 8(\regs)
256 	fstd,ma	 %fr2, 8(\regs)
257 	fstd,ma	 %fr3, 8(\regs)
258 	fstd,ma	 %fr4, 8(\regs)
259 	fstd,ma	 %fr5, 8(\regs)
260 	fstd,ma	 %fr6, 8(\regs)
261 	fstd,ma	 %fr7, 8(\regs)
262 	fstd,ma	 %fr8, 8(\regs)
263 	fstd,ma	 %fr9, 8(\regs)
264 	fstd,ma	%fr10, 8(\regs)
265 	fstd,ma	%fr11, 8(\regs)
266 	fstd,ma	%fr12, 8(\regs)
267 	fstd,ma	%fr13, 8(\regs)
268 	fstd,ma	%fr14, 8(\regs)
269 	fstd,ma	%fr15, 8(\regs)
270 	fstd,ma	%fr16, 8(\regs)
271 	fstd,ma	%fr17, 8(\regs)
272 	fstd,ma	%fr18, 8(\regs)
273 	fstd,ma	%fr19, 8(\regs)
274 	fstd,ma	%fr20, 8(\regs)
275 	fstd,ma	%fr21, 8(\regs)
276 	fstd,ma	%fr22, 8(\regs)
277 	fstd,ma	%fr23, 8(\regs)
278 	fstd,ma	%fr24, 8(\regs)
279 	fstd,ma	%fr25, 8(\regs)
280 	fstd,ma	%fr26, 8(\regs)
281 	fstd,ma	%fr27, 8(\regs)
282 	fstd,ma	%fr28, 8(\regs)
283 	fstd,ma	%fr29, 8(\regs)
284 	fstd,ma	%fr30, 8(\regs)
285 	fstd	%fr31, 0(\regs)
286 	.endm
287 
288 	.macro	rest_fp 	regs
289 	fldd	0(\regs),	 %fr31
290 	fldd,mb	-8(\regs),       %fr30
291 	fldd,mb	-8(\regs),       %fr29
292 	fldd,mb	-8(\regs),       %fr28
293 	fldd,mb	-8(\regs),       %fr27
294 	fldd,mb	-8(\regs),       %fr26
295 	fldd,mb	-8(\regs),       %fr25
296 	fldd,mb	-8(\regs),       %fr24
297 	fldd,mb	-8(\regs),       %fr23
298 	fldd,mb	-8(\regs),       %fr22
299 	fldd,mb	-8(\regs),       %fr21
300 	fldd,mb	-8(\regs),       %fr20
301 	fldd,mb	-8(\regs),       %fr19
302 	fldd,mb	-8(\regs),       %fr18
303 	fldd,mb	-8(\regs),       %fr17
304 	fldd,mb	-8(\regs),       %fr16
305 	fldd,mb	-8(\regs),       %fr15
306 	fldd,mb	-8(\regs),       %fr14
307 	fldd,mb	-8(\regs),       %fr13
308 	fldd,mb	-8(\regs),       %fr12
309 	fldd,mb	-8(\regs),       %fr11
310 	fldd,mb	-8(\regs),       %fr10
311 	fldd,mb	-8(\regs),       %fr9
312 	fldd,mb	-8(\regs),       %fr8
313 	fldd,mb	-8(\regs),       %fr7
314 	fldd,mb	-8(\regs),       %fr6
315 	fldd,mb	-8(\regs),       %fr5
316 	fldd,mb	-8(\regs),       %fr4
317 	fldd,mb	-8(\regs),       %fr3
318 	fldd,mb	-8(\regs),       %fr2
319 	fldd,mb	-8(\regs),       %fr1
320 	fldd,mb	-8(\regs),       %fr0
321 	.endm
322 
323 	.macro	callee_save_float
324 	fstd,ma	 %fr12,	8(%r30)
325 	fstd,ma	 %fr13,	8(%r30)
326 	fstd,ma	 %fr14,	8(%r30)
327 	fstd,ma	 %fr15,	8(%r30)
328 	fstd,ma	 %fr16,	8(%r30)
329 	fstd,ma	 %fr17,	8(%r30)
330 	fstd,ma	 %fr18,	8(%r30)
331 	fstd,ma	 %fr19,	8(%r30)
332 	fstd,ma	 %fr20,	8(%r30)
333 	fstd,ma	 %fr21,	8(%r30)
334 	.endm
335 
336 	.macro	callee_rest_float
337 	fldd,mb	-8(%r30),   %fr21
338 	fldd,mb	-8(%r30),   %fr20
339 	fldd,mb	-8(%r30),   %fr19
340 	fldd,mb	-8(%r30),   %fr18
341 	fldd,mb	-8(%r30),   %fr17
342 	fldd,mb	-8(%r30),   %fr16
343 	fldd,mb	-8(%r30),   %fr15
344 	fldd,mb	-8(%r30),   %fr14
345 	fldd,mb	-8(%r30),   %fr13
346 	fldd,mb	-8(%r30),   %fr12
347 	.endm
348 
349 #ifdef CONFIG_64BIT
350 	.macro	callee_save
351 	std,ma	  %r3,	 CALLEE_REG_FRAME_SIZE(%r30)
352 	mfctl	  %cr27, %r3
353 	std	  %r4,	-136(%r30)
354 	std	  %r5,	-128(%r30)
355 	std	  %r6,	-120(%r30)
356 	std	  %r7,	-112(%r30)
357 	std	  %r8,	-104(%r30)
358 	std	  %r9,	 -96(%r30)
359 	std	 %r10,	 -88(%r30)
360 	std	 %r11,	 -80(%r30)
361 	std	 %r12,	 -72(%r30)
362 	std	 %r13,	 -64(%r30)
363 	std	 %r14,	 -56(%r30)
364 	std	 %r15,	 -48(%r30)
365 	std	 %r16,	 -40(%r30)
366 	std	 %r17,	 -32(%r30)
367 	std	 %r18,	 -24(%r30)
368 	std	  %r3,	 -16(%r30)
369 	.endm
370 
371 	.macro	callee_rest
372 	ldd	 -16(%r30),    %r3
373 	ldd	 -24(%r30),   %r18
374 	ldd	 -32(%r30),   %r17
375 	ldd	 -40(%r30),   %r16
376 	ldd	 -48(%r30),   %r15
377 	ldd	 -56(%r30),   %r14
378 	ldd	 -64(%r30),   %r13
379 	ldd	 -72(%r30),   %r12
380 	ldd	 -80(%r30),   %r11
381 	ldd	 -88(%r30),   %r10
382 	ldd	 -96(%r30),    %r9
383 	ldd	-104(%r30),    %r8
384 	ldd	-112(%r30),    %r7
385 	ldd	-120(%r30),    %r6
386 	ldd	-128(%r30),    %r5
387 	ldd	-136(%r30),    %r4
388 	mtctl	%r3, %cr27
389 	ldd,mb	-CALLEE_REG_FRAME_SIZE(%r30),    %r3
390 	.endm
391 
392 #else /* ! CONFIG_64BIT */
393 
394 	.macro	callee_save
395 	stw,ma	 %r3,	CALLEE_REG_FRAME_SIZE(%r30)
396 	mfctl	 %cr27, %r3
397 	stw	 %r4,	-124(%r30)
398 	stw	 %r5,	-120(%r30)
399 	stw	 %r6,	-116(%r30)
400 	stw	 %r7,	-112(%r30)
401 	stw	 %r8,	-108(%r30)
402 	stw	 %r9,	-104(%r30)
403 	stw	 %r10,	-100(%r30)
404 	stw	 %r11,	 -96(%r30)
405 	stw	 %r12,	 -92(%r30)
406 	stw	 %r13,	 -88(%r30)
407 	stw	 %r14,	 -84(%r30)
408 	stw	 %r15,	 -80(%r30)
409 	stw	 %r16,	 -76(%r30)
410 	stw	 %r17,	 -72(%r30)
411 	stw	 %r18,	 -68(%r30)
412 	stw	  %r3,	 -64(%r30)
413 	.endm
414 
415 	.macro	callee_rest
416 	ldw	 -64(%r30),    %r3
417 	ldw	 -68(%r30),   %r18
418 	ldw	 -72(%r30),   %r17
419 	ldw	 -76(%r30),   %r16
420 	ldw	 -80(%r30),   %r15
421 	ldw	 -84(%r30),   %r14
422 	ldw	 -88(%r30),   %r13
423 	ldw	 -92(%r30),   %r12
424 	ldw	 -96(%r30),   %r11
425 	ldw	-100(%r30),   %r10
426 	ldw	-104(%r30),   %r9
427 	ldw	-108(%r30),   %r8
428 	ldw	-112(%r30),   %r7
429 	ldw	-116(%r30),   %r6
430 	ldw	-120(%r30),   %r5
431 	ldw	-124(%r30),   %r4
432 	mtctl	%r3, %cr27
433 	ldw,mb	-CALLEE_REG_FRAME_SIZE(%r30),   %r3
434 	.endm
435 #endif /* ! CONFIG_64BIT */
436 
437 	.macro	save_specials	regs
438 
439 	SAVE_SP  (%sr0, PT_SR0 (\regs))
440 	SAVE_SP  (%sr1, PT_SR1 (\regs))
441 	SAVE_SP  (%sr2, PT_SR2 (\regs))
442 	SAVE_SP  (%sr3, PT_SR3 (\regs))
443 	SAVE_SP  (%sr4, PT_SR4 (\regs))
444 	SAVE_SP  (%sr5, PT_SR5 (\regs))
445 	SAVE_SP  (%sr6, PT_SR6 (\regs))
446 
447 	SAVE_CR  (%cr17, PT_IASQ0(\regs))
448 	mtctl	 %r0,	%cr17
449 	SAVE_CR  (%cr17, PT_IASQ1(\regs))
450 
451 	SAVE_CR  (%cr18, PT_IAOQ0(\regs))
452 	mtctl	 %r0,	%cr18
453 	SAVE_CR  (%cr18, PT_IAOQ1(\regs))
454 
455 #ifdef CONFIG_64BIT
456 	/* cr11 (sar) is a funny one.  5 bits on PA1.1 and 6 bit on PA2.0
457 	 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
458 	 * reads 5 bits.  Use mfctl,w to read all six bits.  Otherwise
459 	 * we lose the 6th bit on a save/restore over interrupt.
460 	 */
461 	mfctl,w  %cr11, %r1
462 	STREG    %r1, PT_SAR (\regs)
463 #else
464 	SAVE_CR  (%cr11, PT_SAR  (\regs))
465 #endif
466 	SAVE_CR  (%cr19, PT_IIR  (\regs))
467 
468 	/*
469 	 * Code immediately following this macro (in intr_save) relies
470 	 * on r8 containing ipsw.
471 	 */
472 	mfctl    %cr22, %r8
473 	STREG    %r8,   PT_PSW(\regs)
474 	.endm
475 
476 	.macro	rest_specials	regs
477 
478 	REST_SP  (%sr0, PT_SR0 (\regs))
479 	REST_SP  (%sr1, PT_SR1 (\regs))
480 	REST_SP  (%sr2, PT_SR2 (\regs))
481 	REST_SP  (%sr3, PT_SR3 (\regs))
482 	REST_SP  (%sr4, PT_SR4 (\regs))
483 	REST_SP  (%sr5, PT_SR5 (\regs))
484 	REST_SP  (%sr6, PT_SR6 (\regs))
485 	REST_SP  (%sr7, PT_SR7 (\regs))
486 
487 	REST_CR	(%cr17, PT_IASQ0(\regs))
488 	REST_CR	(%cr17, PT_IASQ1(\regs))
489 
490 	REST_CR	(%cr18, PT_IAOQ0(\regs))
491 	REST_CR	(%cr18, PT_IAOQ1(\regs))
492 
493 	REST_CR (%cr11, PT_SAR	(\regs))
494 
495 	REST_CR	(%cr22, PT_PSW	(\regs))
496 	.endm
497 
498 
499 	/* First step to create a "relied upon translation"
500 	 * See PA 2.0 Arch. page F-4 and F-5.
501 	 *
502 	 * The ssm was originally necessary due to a "PCxT bug".
503 	 * But someone decided it needed to be added to the architecture
504 	 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
505 	 * It's been carried forward into PA 2.0 Arch as well. :^(
506 	 *
507 	 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
508 	 * rsm/ssm prevents the ifetch unit from speculatively fetching
509 	 * instructions past this line in the code stream.
510 	 * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
511 	 */
512 	.macro	pcxt_ssm_bug
513 	rsm	PSW_SM_I,%r0
514 	nop	/* 1 */
515 	nop	/* 2 */
516 	nop	/* 3 */
517 	nop	/* 4 */
518 	nop	/* 5 */
519 	nop	/* 6 */
520 	nop	/* 7 */
521 	.endm
522 
523 	/* Switch to virtual mapping, trashing only %r1 */
524 	.macro  virt_map
525 	/* pcxt_ssm_bug */
526 	rsm	PSW_SM_I, %r0		/* barrier for "Relied upon Translation */
527 	mtsp	%r0, %sr4
528 	mtsp	%r0, %sr5
529 	mtsp	%r0, %sr6
530 	tovirt_r1 %r29
531 	load32	KERNEL_PSW, %r1
532 
533 	rsm     PSW_SM_QUIET,%r0	/* second "heavy weight" ctl op */
534 	mtctl	%r0, %cr17		/* Clear IIASQ tail */
535 	mtctl	%r0, %cr17		/* Clear IIASQ head */
536 	mtctl	%r1, %ipsw
537 	load32	4f, %r1
538 	mtctl	%r1, %cr18		/* Set IIAOQ tail */
539 	ldo	4(%r1), %r1
540 	mtctl	%r1, %cr18		/* Set IIAOQ head */
541 	rfir
542 	nop
543 4:
544 	.endm
545 
546 
547 	/*
548 	 * ASM_EXCEPTIONTABLE_ENTRY
549 	 *
550 	 * Creates an exception table entry.
551 	 * Do not convert to a assembler macro. This won't work.
552 	 */
553 #define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr)	\
554 	.section __ex_table,"aw"			!	\
555 	.word (fault_addr - .), (except_addr - .)	!	\
556 	.previous
557 
558 
559 #endif /* __ASSEMBLY__ */
560 #endif
561