1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * FlexSpi Registers & Bits definition. 7 * 8 */ 9 10 #ifndef FSPI_H 11 #define FSPI_H 12 13 #ifndef __ASSEMBLER__ 14 #include <lib/mmio.h> 15 16 #ifdef NXP_FSPI_BE 17 #define fspi_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 18 #define fspi_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 19 #elif defined(NXP_FSPI_LE) 20 #define fspi_in32(a) mmio_read_32((uintptr_t)(a)) 21 #define fspi_out32(a, v) mmio_write_32((uintptr_t)(a), v) 22 #else 23 #error Please define FSPI register endianness 24 #endif 25 26 #endif 27 28 /* All LE so not swap needed */ 29 #define FSPI_IPDATA_SWAP 0U 30 #define FSPI_AHBDATA_SWAP 0U 31 32 #define CONFIG_FSPI_FASTREAD 1U 33 34 #define FSPI_BYTES_PER_KBYTES 0x400U 35 #define FLASH_NUM 1U 36 37 #define FSPI_READ_SEQ_ID 0U 38 #define FSPI_WREN_SEQ_ID 1U 39 #define FSPI_WRITE_SEQ_ID 2U 40 #define FSPI_SE_SEQ_ID 3U 41 #define FSPI_RDSR_SEQ_ID 4U 42 #define FSPI_BE_SEQ_ID 5U 43 #define FSPI_FASTREAD_SEQ_ID 6U 44 #define FSPI_4K_SEQ_ID 7U 45 46 /* 47 * LUT register layout: 48 * 49 * --------------------------------------------------- 50 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 51 * --------------------------------------------------- 52 * 53 * INSTR_SHIFT- 10, PAD_SHIFT - 8, OPRND_SHIFT -0 54 */ 55 #define FSPI_INSTR_OPRND0_SHIFT 0 56 #define FSPI_INSTR_OPRND0(x) (x << FSPI_INSTR_OPRND0_SHIFT) 57 #define FSPI_INSTR_PAD0_SHIFT 8 58 #define FSPI_INSTR_PAD0(x) ((x) << FSPI_INSTR_PAD0_SHIFT) 59 #define FSPI_INSTR_OPCODE0_SHIFT 10 60 #define FSPI_INSTR_OPCODE0(x) ((x) << FSPI_INSTR_OPCODE0_SHIFT) 61 #define FSPI_INSTR_OPRND1_SHIFT 16 62 #define FSPI_INSTR_OPRND1(x) ((x) << FSPI_INSTR_OPRND1_SHIFT) 63 #define FSPI_INSTR_PAD1_SHIFT 24 64 #define FSPI_INSTR_PAD1(x) ((x) << FSPI_INSTR_PAD1_SHIFT) 65 #define FSPI_INSTR_OPCODE1_SHIFT 26 66 #define FSPI_INSTR_OPCODE1(x) ((x) << FSPI_INSTR_OPCODE1_SHIFT) 67 68 /* Instruction set for the LUT register. */ 69 #define LUT_STOP 0x00 70 #define LUT_CMD 0x01 71 #define LUT_ADDR 0x02 72 #define LUT_CADDR_SDR 0x03 73 #define LUT_MODE 0x04 74 #define LUT_MODE2 0x05 75 #define LUT_MODE4 0x06 76 #define LUT_MODE8 0x07 77 #define LUT_NXP_WRITE 0x08 78 #define LUT_NXP_READ 0x09 79 80 #define LUT_LEARN_SDR 0x0A 81 #define LUT_DATSZ_SDR 0x0B 82 #define LUT_DUMMY 0x0C 83 #define LUT_DUMMY_RWDS_SDR 0x0D 84 #define LUT_JMP_ON_CS 0x1F 85 #define LUT_CMD_DDR 0x21 86 #define LUT_ADDR_DDR 0x22 87 #define LUT_CADDR_DDR 0x23 88 #define LUT_MODE_DDR 0x24 89 #define LUT_MODE2_DDR 0x25 90 #define LUT_MODE4_DDR 0x26 91 #define LUT_MODE8_DDR 0x27 92 #define LUT_WRITE_DDR 0x28 93 #define LUT_READ_DDR 0x29 94 #define LUT_LEARN_DDR 0x2A 95 #define LUT_DATSZ_DDR 0x2B 96 #define LUT_DUMMY_DDR 0x2C 97 #define LUT_DUMMY_RWDS_DDR 0x2D 98 99 #define FSPI_NOR_CMD_READ 0x03 100 #define FSPI_NOR_CMD_READ_4B 0x13 101 #define FSPI_NOR_CMD_FASTREAD 0x0b 102 #define FSPI_NOR_CMD_FASTREAD_4B 0x0c 103 #define FSPI_NOR_CMD_PP 0x02 104 #define FSPI_NOR_CMD_PP_4B 0x12 105 #define FSPI_NOR_CMD_WREN 0x06 106 #define FSPI_NOR_CMD_SE_64K 0xd8 107 #define FSPI_NOR_CMD_SE_64K_4B 0xdc 108 #define FSPI_NOR_CMD_SE_4K 0x20 109 #define FSPI_NOR_CMD_SE_4K_4B 0x21 110 #define FSPI_NOR_CMD_BE 0x60 111 #define FSPI_NOR_CMD_RDSR 0x05 112 #define FSPI_NOR_CMD_WREN_STOP 0x04 113 114 #define FSPI_LUT_STOP 0x00 115 #define FSPI_LUT_CMD 0x01 116 #define FSPI_LUT_ADDR 0x02 117 118 #define FSPI_LUT_PAD1 0 119 #define FSPI_LUT_PAD2 1 120 #define FSPI_LUT_PAD4 2 121 #define FSPI_LUT_PAD8 3 122 123 #define FSPI_LUT_ADDR24BIT 0x18 124 #define FSPI_LUT_ADDR32BIT 0x20 125 126 #define FSPI_LUT_WRITE 0x08 127 #define FSPI_LUT_READ 0x09 128 #define FSPI_DUMMY_SDR 0x0c 129 130 /* TODO Check size if functional*/ 131 #define FSPI_RX_IPBUF_SIZE 0x200 /* 64*64 bits */ 132 #define FSPI_TX_IPBUF_SIZE 0x400 /* 128*64 bits */ 133 134 #define FSPI_RX_MAX_AHBBUF_SIZE 0x800 /* 256 * 64bits */ 135 #define FSPI_TX_MAX_AHBBUF_SIZE 0x40 /* 8 * 64bits */ 136 137 #define FSPI_LUTREG_OFFSET 0x200ul 138 139 #define FSPI_MAX_TIMEOUT_AHBCMD 0xFFU 140 #define FSPI_MAX_TIMEOUT_IPCMD 0xFF 141 #define FSPI_SER_CLK_DIV 0x04 142 #define FSPI_HSEN 0 143 #define FSPI_ENDCFG_BE64 0x01 144 #define FSPI_ENDCFG_BE32 0x03 145 #define FSPI_ENDCFG_LE32 0x02 146 #define FSPI_ENDCFG_LE64 0x0 147 148 #define MASK_24BIT_ADDRESS 0x00ffffff 149 #define MASK_32BIT_ADDRESS 0xffffffff 150 151 /* Registers used by the driver */ 152 #define FSPI_MCR0 0x0ul 153 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) 154 #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) 155 #define FSPI_MCR0_LEARN_EN BIT(15) 156 #define FSPI_MCR0_SCRFRUN_EN BIT(14) 157 #define FSPI_MCR0_OCTCOMB_EN BIT(13) 158 #define FSPI_MCR0_DOZE_EN BIT(12) 159 #define FSPI_MCR0_HSEN BIT(11) 160 #define FSPI_MCR0_SERCLKDIV BIT(8) 161 #define FSPI_MCR0_ATDF_EN BIT(7) 162 #define FSPI_MCR0_ARDF_EN BIT(6) 163 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) 164 #define FSPI_MCR0_END_CFG(x) ((x) << 2) 165 #define FSPI_MCR0_MDIS BIT(1) 166 #define FSPI_MCR0_SWRST BIT(0) 167 168 #define FSPI_MCR0_AHBGRANTWAIT_SHIFT 24 169 #define FSPI_MCR0_AHBGRANTWAIT_MASK (0xFFU << FSPI_MCR0_AHBGRANTWAIT_SHIFT) 170 #define FSPI_MCR0_IPGRANTWAIT_SHIFT 16 171 #define FSPI_MCR0_IPGRANTWAIT_MASK (0xFF << FSPI_MCR0_IPGRANTWAIT_SHIFT) 172 #define FSPI_MCR0_HSEN_SHIFT 11 173 #define FSPI_MCR0_HSEN_MASK (1 << FSPI_MCR0_HSEN_SHIFT) 174 #define FSPI_MCR0_SERCLKDIV_SHIFT 8 175 #define FSPI_MCR0_SERCLKDIV_MASK (7 << FSPI_MCR0_SERCLKDIV_SHIFT) 176 #define FSPI_MCR0_ENDCFG_SHIFT 2 177 #define FSPI_MCR0_ENDCFG_MASK (3 << FSPI_MCR0_ENDCFG_SHIFT) 178 #define FSPI_MCR0_RXCLKSRC_SHIFT 4 179 #define FSPI_MCR0_RXCLKSRC_MASK (3 << FSPI_MCR0_RXCLKSRC_SHIFT) 180 181 #define FSPI_MCR1 0x04 182 #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) 183 #define FSPI_MCR1_AHB_TIMEOUT(x) (x) 184 185 #define FSPI_MCR2 0x08 186 #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) 187 #define FSPI_MCR2_SAMEDEVICEEN BIT(15) 188 #define FSPI_MCR2_CLRLRPHS BIT(14) 189 #define FSPI_MCR2_ABRDATSZ BIT(8) 190 #define FSPI_MCR2_ABRLEARN BIT(7) 191 #define FSPI_MCR2_ABR_READ BIT(6) 192 #define FSPI_MCR2_ABRWRITE BIT(5) 193 #define FSPI_MCR2_ABRDUMMY BIT(4) 194 #define FSPI_MCR2_ABR_MODE BIT(3) 195 #define FSPI_MCR2_ABRCADDR BIT(2) 196 #define FSPI_MCR2_ABRRADDR BIT(1) 197 #define FSPI_MCR2_ABR_CMD BIT(0) 198 199 #define FSPI_AHBCR 0x0c 200 #define FSPI_AHBCR_RDADDROPT BIT(6) 201 #define FSPI_AHBCR_PREF_EN BIT(5) 202 #define FSPI_AHBCR_BUFF_EN BIT(4) 203 #define FSPI_AHBCR_CACH_EN BIT(3) 204 #define FSPI_AHBCR_CLRTXBUF BIT(2) 205 #define FSPI_AHBCR_CLRRXBUF BIT(1) 206 #define FSPI_AHBCR_PAR_EN BIT(0) 207 208 #define FSPI_INTEN 0x10 209 #define FSPI_INTEN_SCLKSBWR BIT(9) 210 #define FSPI_INTEN_SCLKSBRD BIT(8) 211 #define FSPI_INTEN_DATALRNFL BIT(7) 212 #define FSPI_INTEN_IPTXWE BIT(6) 213 #define FSPI_INTEN_IPRXWA BIT(5) 214 #define FSPI_INTEN_AHBCMDERR BIT(4) 215 #define FSPI_INTEN_IPCMDERR BIT(3) 216 #define FSPI_INTEN_AHBCMDGE BIT(2) 217 #define FSPI_INTEN_IPCMDGE BIT(1) 218 #define FSPI_INTEN_IPCMDDONE BIT(0) 219 220 #define FSPI_INTR 0x14 221 #define FSPI_INTR_SCLKSBWR BIT(9) 222 #define FSPI_INTR_SCLKSBRD BIT(8) 223 #define FSPI_INTR_DATALRNFL BIT(7) 224 #define FSPI_INTR_IPTXWE BIT(6) 225 #define FSPI_INTR_IPRXWA BIT(5) 226 #define FSPI_INTR_AHBCMDERR BIT(4) 227 #define FSPI_INTR_IPCMDERR BIT(3) 228 #define FSPI_INTR_AHBCMDGE BIT(2) 229 #define FSPI_INTR_IPCMDGE BIT(1) 230 #define FSPI_INTR_IPCMDDONE BIT(0) 231 232 #define FSPI_LUTKEY 0x18 233 #define FSPI_LUTKEY_VALUE 0x5AF05AF0 234 235 #define FSPI_LCKCR 0x1C 236 237 #define FSPI_LCKER_LOCK 0x1 238 #define FSPI_LCKER_UNLOCK 0x2 239 240 #define FSPI_BUFXCR_INVALID_MSTRID 0xE 241 #define FSPI_AHBRX_BUF0CR0 0x20 242 #define FSPI_AHBRX_BUF1CR0 0x24 243 #define FSPI_AHBRX_BUF2CR0 0x28 244 #define FSPI_AHBRX_BUF3CR0 0x2C 245 #define FSPI_AHBRX_BUF4CR0 0x30 246 #define FSPI_AHBRX_BUF5CR0 0x34 247 #define FSPI_AHBRX_BUF6CR0 0x38 248 #define FSPI_AHBRX_BUF7CR0 0x3C 249 250 #define FSPI_AHBRXBUF0CR7_PREF BIT(31) 251 252 #define FSPI_AHBRX_BUF0CR1 0x40 253 #define FSPI_AHBRX_BUF1CR1 0x44 254 #define FSPI_AHBRX_BUF2CR1 0x48 255 #define FSPI_AHBRX_BUF3CR1 0x4C 256 #define FSPI_AHBRX_BUF4CR1 0x50 257 #define FSPI_AHBRX_BUF5CR1 0x54 258 #define FSPI_AHBRX_BUF6CR1 0x58 259 #define FSPI_AHBRX_BUF7CR1 0x5C 260 261 #define FSPI_FLSHA1CR0 0x60 262 #define FSPI_FLSHA2CR0 0x64 263 #define FSPI_FLSHB1CR0 0x68 264 #define FSPI_FLSHB2CR0 0x6C 265 #define FSPI_FLSHXCR0_SZ_KB 10 266 #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) 267 268 #define FSPI_FLSHA1CR1 0x70 269 #define FSPI_FLSHA2CR1 0x74 270 #define FSPI_FLSHB1CR1 0x78 271 #define FSPI_FLSHB2CR1 0x7C 272 #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) 273 #define FSPI_FLSHXCR1_CAS(x) ((x) << 11) 274 #define FSPI_FLSHXCR1_WA BIT(10) 275 #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) 276 #define FSPI_FLSHXCR1_TCSS(x) (x) 277 278 #define FSPI_FLSHXCR1_TCSH_SHIFT 5 279 #define FSPI_FLSHXCR1_TCSH_MASK (0x1F << FSPI_FLSHXCR1_TCSH_SHIFT) 280 #define FSPI_FLSHXCR1_TCSS_SHIFT 0 281 #define FSPI_FLSHXCR1_TCSS_MASK (0x1F << FSPI_FLSHXCR1_TCSS_SHIFT) 282 283 #define FSPI_FLSHA1CR2 0x80 284 #define FSPI_FLSHA2CR2 0x84 285 #define FSPI_FLSHB1CR2 0x88 286 #define FSPI_FLSHB2CR2 0x8C 287 #define FSPI_FLSHXCR2_CLRINSP BIT(24) 288 #define FSPI_FLSHXCR2_AWRWAIT BIT(16) 289 #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 290 #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 291 #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 292 #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 293 294 #define FSPI_IPCR0 0xA0 295 296 #define FSPI_IPCR1 0xA4 297 #define FSPI_IPCR1_IPAREN BIT(31) 298 #define FSPI_IPCR1_SEQNUM_SHIFT 24 299 #define FSPI_IPCR1_SEQID_SHIFT 16 300 #define FSPI_IPCR1_IDATSZ(x) (x) 301 302 #define FSPI_IPCMD 0xB0 303 #define FSPI_IPCMD_TRG BIT(0) 304 305 306 /* IP Command Register */ 307 #define FSPI_IPCMD_TRG_SHIFT 0 308 #define FSPI_IPCMD_TRG_MASK (1 << FSPI_IPCMD_TRG_SHIFT) 309 310 #define FSPI_INTR_IPRXWA_SHIFT 5 311 #define FSPI_INTR_IPRXWA_MASK (1 << FSPI_INTR_IPRXWA_SHIFT) 312 313 #define FSPI_INTR_IPCMDDONE_SHIFT 0 314 #define FSPI_INTR_IPCMDDONE_MASK (1 << FSPI_INTR_IPCMDDONE_SHIFT) 315 316 #define FSPI_INTR_IPTXWE_SHIFT 6 317 #define FSPI_INTR_IPTXWE_MASK (1 << FSPI_INTR_IPTXWE_SHIFT) 318 319 #define FSPI_IPTXFSTS_FILL_SHIFT 0 320 #define FSPI_IPTXFSTS_FILL_MASK (0xFF << FSPI_IPTXFSTS_FILL_SHIFT) 321 322 #define FSPI_IPCR1_ISEQID_SHIFT 16 323 #define FSPI_IPCR1_ISEQID_MASK (0x1F << FSPI_IPCR1_ISEQID_SHIFT) 324 325 #define FSPI_IPRXFSTS_FILL_SHIFT 0 326 #define FSPI_IPRXFSTS_FILL_MASK (0xFF << FSPI_IPRXFSTS_FILL_SHIFT) 327 328 #define FSPI_DLPR 0xB4 329 330 #define FSPI_IPRXFCR 0xB8 331 #define FSPI_IPRXFCR_CLR BIT(0) 332 #define FSPI_IPRXFCR_DMA_EN BIT(1) 333 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2) 334 335 #define FSPI_IPTXFCR 0xBC 336 #define FSPI_IPTXFCR_CLR BIT(0) 337 #define FSPI_IPTXFCR_DMA_EN BIT(1) 338 #define FSPI_IPTXFCR_WMRK(x) ((x) << 2) 339 340 #define FSPI_DLLACR 0xC0 341 #define FSPI_DLLACR_OVRDEN BIT(8) 342 343 #define FSPI_DLLBCR 0xC4 344 #define FSPI_DLLBCR_OVRDEN BIT(8) 345 346 #define FSPI_STS0 0xE0 347 #define FSPI_STS0_DLPHB(x) ((x) << 8) 348 #define FSPI_STS0_DLPHA(x) ((x) << 4) 349 #define FSPI_STS0_CMD_SRC(x) ((x) << 2) 350 #define FSPI_STS0_ARB_IDLE BIT(1) 351 #define FSPI_STS0_SEQ_IDLE BIT(0) 352 353 #define FSPI_STS1 0xE4 354 #define FSPI_STS1_IP_ERRCD(x) ((x) << 24) 355 #define FSPI_STS1_IP_ERRID(x) ((x) << 16) 356 #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) 357 #define FSPI_STS1_AHB_ERRID(x) (x) 358 359 #define FSPI_AHBSPNST 0xEC 360 #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) 361 #define FSPI_AHBSPNST_BUFID(x) ((x) << 1) 362 #define FSPI_AHBSPNST_ACTIVE BIT(0) 363 364 #define FSPI_IPRXFSTS 0xF0 365 #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) 366 #define FSPI_IPRXFSTS_FILL(x) (x) 367 368 #define FSPI_IPTXFSTS 0xF4 369 #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) 370 #define FSPI_IPTXFSTS_FILL(x) (x) 371 372 #define FSPI_NOR_SR_WIP_SHIFT (0) 373 #define FSPI_NOR_SR_WIP_MASK (1 << FSPI_NOR_SR_WIP_SHIFT) 374 375 #define FSPI_RFDR 0x100 376 #define FSPI_TFDR 0x180 377 378 #define FSPI_LUT_BASE 0x200 379 #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) 380 #define FSPI_LUT_REG(idx) \ 381 (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) 382 383 /* register map end */ 384 385 #endif 386