1 /* 2 * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef FVP_DEF_H 8 #define FVP_DEF_H 9 10 #include <lib/utils_def.h> 11 12 #ifndef FVP_CLUSTER_COUNT 13 #error "FVP_CLUSTER_COUNT is not set in makefile" 14 #endif 15 16 #ifndef FVP_MAX_CPUS_PER_CLUSTER 17 #error "FVP_MAX_CPUS_PER_CLUSTER is not set in makefile" 18 #endif 19 20 #ifndef FVP_MAX_PE_PER_CPU 21 #error "FVP_MAX_PE_PER_CPU is not set in makefile" 22 #endif 23 24 #define FVP_PRIMARY_CPU 0x0 25 26 /* Defines for the Interconnect build selection */ 27 #define FVP_CCI 1 28 #define FVP_CCN 2 29 30 /****************************************************************************** 31 * Definition of platform soc id 32 *****************************************************************************/ 33 #define FVP_SOC_ID 0 34 35 /******************************************************************************* 36 * FVP memory map related constants 37 ******************************************************************************/ 38 39 #define FLASH1_BASE UL(0x0c000000) 40 #define FLASH1_SIZE UL(0x04000000) 41 42 #define PSRAM_BASE UL(0x14000000) 43 #define PSRAM_SIZE UL(0x04000000) 44 45 #define VRAM_BASE UL(0x18000000) 46 #define VRAM_SIZE UL(0x02000000) 47 48 /* Aggregate of all devices in the first GB */ 49 #define DEVICE0_BASE UL(0x20000000) 50 #define DEVICE0_SIZE UL(0x0c200000) 51 52 /* 53 * In case of FVP models with CCN, the CCN register space overlaps into 54 * the NSRAM area. 55 */ 56 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 57 #define DEVICE1_BASE UL(0x2e000000) 58 #define DEVICE1_SIZE UL(0x1A00000) 59 #else 60 #define DEVICE1_BASE BASE_GICD_BASE 61 62 #if GIC_ENABLE_V4_EXTN 63 /* GICv4 mapping: GICD + CORE_COUNT * 256KB */ 64 #define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \ 65 (PLATFORM_CORE_COUNT * 0x40000)) 66 #else 67 /* GICv2 and GICv3 mapping: GICD + CORE_COUNT * 128KB */ 68 #define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \ 69 (PLATFORM_CORE_COUNT * 0x20000)) 70 #endif /* GIC_ENABLE_V4_EXTN */ 71 72 #define NSRAM_BASE UL(0x2e000000) 73 #define NSRAM_SIZE UL(0x10000) 74 #endif 75 /* Devices in the second GB */ 76 #define DEVICE2_BASE UL(0x7fe00000) 77 #define DEVICE2_SIZE UL(0x00200000) 78 79 #define PCIE_EXP_BASE UL(0x40000000) 80 #define TZRNG_BASE UL(0x7fe60000) 81 82 /* Non-volatile counters */ 83 #define TRUSTED_NVCTR_BASE UL(0x7fe70000) 84 #define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0000)) 85 #define TFW_NVCTR_SIZE UL(4) 86 #define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0004)) 87 #define NTFW_CTR_SIZE UL(4) 88 89 /* Keys */ 90 #define SOC_KEYS_BASE UL(0x7fe80000) 91 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + UL(0x0000)) 92 #define TZ_PUB_KEY_HASH_SIZE UL(32) 93 #define HU_KEY_BASE (SOC_KEYS_BASE + UL(0x0020)) 94 #define HU_KEY_SIZE UL(16) 95 #define END_KEY_BASE (SOC_KEYS_BASE + UL(0x0044)) 96 #define END_KEY_SIZE UL(32) 97 98 /* Constants to distinguish FVP type */ 99 #define HBI_BASE_FVP U(0x020) 100 #define REV_BASE_FVP_V0 U(0x0) 101 #define REV_BASE_FVP_REVC U(0x2) 102 103 #define HBI_FOUNDATION_FVP U(0x010) 104 #define REV_FOUNDATION_FVP_V2_0 U(0x0) 105 #define REV_FOUNDATION_FVP_V2_1 U(0x1) 106 #define REV_FOUNDATION_FVP_v9_1 U(0x2) 107 #define REV_FOUNDATION_FVP_v9_6 U(0x3) 108 109 #define BLD_GIC_VE_MMAP U(0x0) 110 #define BLD_GIC_A53A57_MMAP U(0x1) 111 112 #define ARCH_MODEL U(0x1) 113 114 /* FVP Power controller base address*/ 115 #define PWRC_BASE UL(0x1c100000) 116 117 /* FVP SP804 timer frequency is 35 MHz*/ 118 #define SP804_TIMER_CLKMULT 1 119 #define SP804_TIMER_CLKDIV 35 120 121 /* SP810 controller. FVP specific flags */ 122 #define FVP_SP810_CTRL_TIM0_OV BIT_32(16) 123 #define FVP_SP810_CTRL_TIM1_OV BIT_32(18) 124 #define FVP_SP810_CTRL_TIM2_OV BIT_32(20) 125 #define FVP_SP810_CTRL_TIM3_OV BIT_32(22) 126 127 /******************************************************************************* 128 * GIC & interrupt handling related constants 129 ******************************************************************************/ 130 /* VE compatible GIC memory map */ 131 #define VE_GICD_BASE UL(0x2c001000) 132 #define VE_GICC_BASE UL(0x2c002000) 133 #define VE_GICH_BASE UL(0x2c004000) 134 #define VE_GICV_BASE UL(0x2c006000) 135 136 /* Base FVP compatible GIC memory map */ 137 #define BASE_GICD_BASE UL(0x2f000000) 138 #define BASE_GICD_SIZE UL(0x10000) 139 #define BASE_GICR_BASE UL(0x2f100000) 140 141 #if GIC_ENABLE_V4_EXTN 142 /* GICv4 redistributor size: 256KB */ 143 #define BASE_GICR_SIZE UL(0x40000) 144 #else 145 #define BASE_GICR_SIZE UL(0x20000) 146 #endif /* GIC_ENABLE_V4_EXTN */ 147 148 #define BASE_GICC_BASE UL(0x2c000000) 149 #define BASE_GICH_BASE UL(0x2c010000) 150 #define BASE_GICV_BASE UL(0x2c02f000) 151 152 #define FVP_IRQ_TZ_WDOG 56 153 #define FVP_IRQ_SEC_SYS_TIMER 57 154 155 /******************************************************************************* 156 * TrustZone address space controller related constants 157 ******************************************************************************/ 158 159 /* NSAIDs used by devices in TZC filter 0 on FVP */ 160 #define FVP_NSAID_DEFAULT 0 161 #define FVP_NSAID_PCI 1 162 #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ 163 #define FVP_NSAID_AP 9 /* Application Processors */ 164 #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ 165 166 /* NSAIDs used by devices in TZC filter 2 on FVP */ 167 #define FVP_NSAID_HDLCD0 2 168 #define FVP_NSAID_CLCD 7 169 170 /******************************************************************************* 171 * Memprotect definitions 172 ******************************************************************************/ 173 /* PSCI memory protect definitions: 174 * This variable is stored in a non-secure flash because some ARM reference 175 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 176 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 177 */ 178 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 179 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 180 181 #endif /* FVP_DEF_H */ 182