1 /*
2 * ARM Generic Interrupt Controller support
3 *
4 * Tim Deegan <tim@xen.org>
5 * Copyright (c) 2011 Citrix Systems.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #ifndef __ASM_ARM_GIC_H__
19 #define __ASM_ARM_GIC_H__
20
21 #define NR_GIC_LOCAL_IRQS NR_LOCAL_IRQS
22 #define NR_GIC_SGI 16
23
24 #define GICD_CTLR (0x000)
25 #define GICD_TYPER (0x004)
26 #define GICD_IIDR (0x008)
27 #define GICD_IGROUPR (0x080)
28 #define GICD_IGROUPRN (0x0FC)
29 #define GICD_ISENABLER (0x100)
30 #define GICD_ISENABLERN (0x17C)
31 #define GICD_ICENABLER (0x180)
32 #define GICD_ICENABLERN (0x1fC)
33 #define GICD_ISPENDR (0x200)
34 #define GICD_ISPENDRN (0x27C)
35 #define GICD_ICPENDR (0x280)
36 #define GICD_ICPENDRN (0x2FC)
37 #define GICD_ISACTIVER (0x300)
38 #define GICD_ISACTIVERN (0x37C)
39 #define GICD_ICACTIVER (0x380)
40 #define GICD_ICACTIVERN (0x3FC)
41 #define GICD_IPRIORITYR (0x400)
42 #define GICD_IPRIORITYRN (0x7F8)
43 #define GICD_ITARGETSR (0x800)
44 #define GICD_ITARGETSR7 (0x81C)
45 #define GICD_ITARGETSR8 (0x820)
46 #define GICD_ITARGETSRN (0xBF8)
47 #define GICD_ICFGR (0xC00)
48 #define GICD_ICFGR1 (0xC04)
49 #define GICD_ICFGR2 (0xC08)
50 #define GICD_ICFGRN (0xCFC)
51 #define GICD_NSACR (0xE00)
52 #define GICD_NSACRN (0xEFC)
53 #define GICD_SGIR (0xF00)
54 #define GICD_CPENDSGIR (0xF10)
55 #define GICD_CPENDSGIRN (0xF1C)
56 #define GICD_SPENDSGIR (0xF20)
57 #define GICD_SPENDSGIRN (0xF2C)
58 #define GICD_ICPIDR2 (0xFE8)
59
60 #define GICD_SGI_TARGET_LIST_SHIFT (24)
61 #define GICD_SGI_TARGET_LIST_MASK (0x3UL << GICD_SGI_TARGET_LIST_SHIFT)
62 #define GICD_SGI_TARGET_LIST (0UL<<GICD_SGI_TARGET_LIST_SHIFT)
63 #define GICD_SGI_TARGET_LIST_VAL (0)
64 #define GICD_SGI_TARGET_OTHERS (1UL<<GICD_SGI_TARGET_LIST_SHIFT)
65 #define GICD_SGI_TARGET_OTHERS_VAL (1)
66 #define GICD_SGI_TARGET_SELF (2UL<<GICD_SGI_TARGET_LIST_SHIFT)
67 #define GICD_SGI_TARGET_SELF_VAL (2)
68 #define GICD_SGI_TARGET_SHIFT (16)
69 #define GICD_SGI_TARGET_MASK (0xFFUL<<GICD_SGI_TARGET_SHIFT)
70 #define GICD_SGI_GROUP1 (1UL<<15)
71 #define GICD_SGI_INTID_MASK (0xFUL)
72
73 #define GICC_CTLR (0x0000)
74 #define GICC_PMR (0x0004)
75 #define GICC_BPR (0x0008)
76 #define GICC_IAR (0x000C)
77 #define GICC_EOIR (0x0010)
78 #define GICC_RPR (0x0014)
79 #define GICC_HPPIR (0x0018)
80 #define GICC_APR (0x00D0)
81 #define GICC_NSAPR (0x00E0)
82 #define GICC_IIDR (0x00FC)
83 #define GICC_DIR (0x1000)
84
85 #define GICH_HCR (0x00)
86 #define GICH_VTR (0x04)
87 #define GICH_VMCR (0x08)
88 #define GICH_MISR (0x10)
89 #define GICH_EISR0 (0x20)
90 #define GICH_EISR1 (0x24)
91 #define GICH_ELSR0 (0x30)
92 #define GICH_ELSR1 (0x34)
93 #define GICH_APR (0xF0)
94 #define GICH_LR (0x100)
95
96 /* Register bits */
97 #define GICD_CTL_ENABLE 0x1
98
99 #define GICD_TYPE_LINES 0x01f
100 #define GICD_TYPE_CPUS_SHIFT 5
101 #define GICD_TYPE_CPUS 0x0e0
102 #define GICD_TYPE_SEC 0x400
103 #define GICD_TYPER_DVIS (1U << 18)
104
105 #define GICC_CTL_ENABLE 0x1
106 #define GICC_CTL_EOI (0x1 << 9)
107
108 #define GICC_IA_IRQ 0x03ff
109 #define GICC_IA_CPU_MASK 0x1c00
110 #define GICC_IA_CPU_SHIFT 10
111
112 #define GICH_HCR_EN (1 << 0)
113 #define GICH_HCR_UIE (1 << 1)
114 #define GICH_HCR_LRENPIE (1 << 2)
115 #define GICH_HCR_NPIE (1 << 3)
116 #define GICH_HCR_VGRP0EIE (1 << 4)
117 #define GICH_HCR_VGRP0DIE (1 << 5)
118 #define GICH_HCR_VGRP1EIE (1 << 6)
119 #define GICH_HCR_VGRP1DIE (1 << 7)
120
121 #define GICH_MISR_EOI (1 << 0)
122 #define GICH_MISR_U (1 << 1)
123 #define GICH_MISR_LRENP (1 << 2)
124 #define GICH_MISR_NP (1 << 3)
125 #define GICH_MISR_VGRP0E (1 << 4)
126 #define GICH_MISR_VGRP0D (1 << 5)
127 #define GICH_MISR_VGRP1E (1 << 6)
128 #define GICH_MISR_VGRP1D (1 << 7)
129
130 /*
131 * The minimum GICC_BPR is required to be in the range 0-3. We set
132 * GICC_BPR to 0 but we must expect that it might be 3. This means we
133 * can rely on premption between the following ranges:
134 * 0xf0..0xff
135 * 0xe0..0xdf
136 * 0xc0..0xcf
137 * 0xb0..0xbf
138 * 0xa0..0xaf
139 * 0x90..0x9f
140 * 0x80..0x8f
141 *
142 * Priorities within a range will not preempt each other.
143 *
144 * A GIC must support a mimimum of 16 priority levels.
145 */
146 #define GIC_PRI_LOWEST 0xf0
147 #define GIC_PRI_IRQ 0xa0
148 #define GIC_PRI_IPI 0x90 /* IPIs must preempt normal interrupts */
149 #define GIC_PRI_HIGHEST 0x80 /* Higher priorities belong to Secure-World */
150 #define GIC_PRI_TO_GUEST(pri) (pri >> 3) /* GICH_LR and GICH_VMCR only support
151 5 bits for guest irq priority */
152
153 #define GICH_LR_PENDING 1
154 #define GICH_LR_ACTIVE 2
155
156 #ifndef __ASSEMBLY__
157 #include <xen/device_tree.h>
158 #include <xen/irq.h>
159
160 #define DT_COMPAT_GIC_CORTEX_A15 "arm,cortex-a15-gic"
161
162 #define DT_MATCH_GIC_V2 \
163 DT_MATCH_COMPATIBLE(DT_COMPAT_GIC_CORTEX_A15), \
164 DT_MATCH_COMPATIBLE("arm,cortex-a7-gic"), \
165 DT_MATCH_COMPATIBLE("arm,gic-400")
166
167 #define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE("arm,gic-v3")
168
169 #ifdef CONFIG_GICV3
170 /*
171 * GICv3 registers that needs to be saved/restored
172 */
173 struct gic_v3 {
174 uint32_t hcr, vmcr, sre_el1;
175 uint32_t apr0[4];
176 uint32_t apr1[4];
177 uint64_t lr[16];
178 };
179 #endif
180
181 /*
182 * GICv2 register that needs to be saved/restored
183 * on VCPU context switch
184 */
185 struct gic_v2 {
186 uint32_t hcr;
187 uint32_t vmcr;
188 uint32_t apr;
189 uint32_t lr[64];
190 };
191
192 /*
193 * Union to hold underlying hw version context information
194 */
195 union gic_state_data {
196 struct gic_v2 v2;
197 #ifdef CONFIG_GICV3
198 struct gic_v3 v3;
199 #endif
200 };
201
202 /*
203 * Decode LR register content.
204 * The LR register format is different for GIC HW version
205 */
206 struct gic_lr {
207 /* Virtual IRQ */
208 uint32_t virq;
209 uint8_t priority;
210 bool active;
211 bool pending;
212 bool hw_status;
213 union
214 {
215 /* Only filled when there are a corresponding pIRQ (hw_state = true) */
216 struct
217 {
218 uint32_t pirq;
219 } hw;
220 /* Only filled when there are no corresponding pIRQ (hw_state = false) */
221 struct
222 {
223 bool eoi;
224 uint8_t source; /* GICv2 only */
225 } virt;
226 };
227 };
228
229 enum gic_version {
230 GIC_INVALID = 0, /* the default until explicitly set up */
231 GIC_V2,
232 GIC_V3,
233 };
234
235 DECLARE_PER_CPU(uint64_t, lr_mask);
236
237 extern enum gic_version gic_hw_version(void);
238
239 /* Program the IRQ type into the GIC */
240 void gic_set_irq_type(struct irq_desc *desc, unsigned int type);
241
242 /* Program the GIC to route an interrupt */
243 extern void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority);
244 extern int gic_route_irq_to_guest(struct domain *, unsigned int virq,
245 struct irq_desc *desc,
246 unsigned int priority);
247
248 /* Remove an IRQ passthrough to a guest */
249 int gic_remove_irq_from_guest(struct domain *d, unsigned int virq,
250 struct irq_desc *desc);
251
252 extern void gic_clear_pending_irqs(struct vcpu *v);
253
254 extern void init_maintenance_interrupt(void);
255 extern void gic_raise_guest_irq(struct vcpu *v, unsigned int irq,
256 unsigned int priority);
257 extern void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq);
258
259 /* Accept an interrupt from the GIC and dispatch its handler */
260 extern void gic_interrupt(struct cpu_user_regs *regs, int is_fiq);
261 /* Find the interrupt controller and set up the callback to translate
262 * device tree IRQ.
263 */
264 extern void gic_preinit(void);
265 /* Bring up the interrupt controller, and report # cpus attached */
266 extern void gic_init(void);
267 /* Bring up a secondary CPU's per-CPU GIC interface */
268 extern void gic_init_secondary_cpu(void);
269 /* Take down a CPU's per-CPU GIC interface */
270 extern void gic_disable_cpu(void);
271 /* setup the gic virtual interface for a guest */
272 extern int gicv_setup(struct domain *d);
273
274 /* Context switch */
275 extern void gic_save_state(struct vcpu *v);
276 extern void gic_restore_state(struct vcpu *v);
277
278 /* SGI (AKA IPIs) */
279 enum gic_sgi {
280 GIC_SGI_EVENT_CHECK,
281 GIC_SGI_DUMP_STATE,
282 GIC_SGI_CALL_FUNCTION,
283 GIC_SGI_MAX,
284 };
285
286 /* SGI irq mode types */
287 enum gic_sgi_mode {
288 SGI_TARGET_LIST,
289 SGI_TARGET_OTHERS,
290 SGI_TARGET_SELF,
291 };
292
293 extern void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi);
294 extern void send_SGI_one(unsigned int cpu, enum gic_sgi sgi);
295 extern void send_SGI_self(enum gic_sgi sgi);
296 extern void send_SGI_allbutself(enum gic_sgi sgi);
297
298 /* print useful debug info */
299 extern void gic_dump_info(struct vcpu *v);
300 extern void gic_dump_vgic_info(struct vcpu *v);
301
302 /* Number of interrupt lines */
303 extern unsigned int gic_number_lines(void);
304
305 /* IRQ translation function for the device tree */
306 int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
307 unsigned int *out_hwirq, unsigned int *out_type);
308
309 struct gic_info {
310 /* GIC version */
311 enum gic_version hw_version;
312 /* Number of GIC lines supported */
313 unsigned int nr_lines;
314 /* Number of LR registers */
315 uint8_t nr_lrs;
316 /* Maintenance irq number */
317 unsigned int maintenance_irq;
318 /* Pointer to the device tree node representing the interrupt controller */
319 const struct dt_device_node *node;
320 };
321
322 struct gic_hw_operations {
323 /* Hold GIC HW information */
324 const struct gic_info *info;
325 /* Initialize the GIC and the boot CPU */
326 int (*init)(void);
327 /* Save GIC registers */
328 void (*save_state)(struct vcpu *);
329 /* Restore GIC registers */
330 void (*restore_state)(const struct vcpu *);
331 /* Dump GIC LR register information */
332 void (*dump_state)(const struct vcpu *);
333
334 /* hw_irq_controller to enable/disable/eoi host irq */
335 hw_irq_controller *gic_host_irq_type;
336
337 /* hw_irq_controller to enable/disable/eoi guest irq */
338 hw_irq_controller *gic_guest_irq_type;
339
340 /* End of Interrupt */
341 void (*eoi_irq)(struct irq_desc *irqd);
342 /* Deactivate/reduce priority of irq */
343 void (*deactivate_irq)(struct irq_desc *irqd);
344 /* Read IRQ id and Ack */
345 unsigned int (*read_irq)(void);
346 /* Force the active state of an IRQ by accessing the distributor */
347 void (*set_active_state)(struct irq_desc *irqd, bool state);
348 /* Force the pending state of an IRQ by accessing the distributor */
349 void (*set_pending_state)(struct irq_desc *irqd, bool state);
350 /* Set IRQ type */
351 void (*set_irq_type)(struct irq_desc *desc, unsigned int type);
352 /* Set IRQ priority */
353 void (*set_irq_priority)(struct irq_desc *desc, unsigned int priority);
354 /* Send SGI */
355 void (*send_SGI)(enum gic_sgi sgi, enum gic_sgi_mode irqmode,
356 const cpumask_t *online_mask);
357 /* Disable CPU physical and virtual interfaces */
358 void (*disable_interface)(void);
359 /* Update LR register with state and priority */
360 void (*update_lr)(int lr, unsigned int virq, uint8_t priority,
361 unsigned int hw_irq, unsigned int state);
362 /* Update HCR status register */
363 void (*update_hcr_status)(uint32_t flag, bool set);
364 /* Clear LR register */
365 void (*clear_lr)(int lr);
366 /* Read LR register and populate gic_lr structure */
367 void (*read_lr)(int lr, struct gic_lr *);
368 /* Write LR register from gic_lr structure */
369 void (*write_lr)(int lr, const struct gic_lr *);
370 /* Read VMCR priority */
371 unsigned int (*read_vmcr_priority)(void);
372 /* Read APRn register */
373 unsigned int (*read_apr)(int apr_reg);
374 /* Query the pending state of an interrupt at the distributor level. */
375 bool (*read_pending_state)(struct irq_desc *irqd);
376 /* Secondary CPU init */
377 int (*secondary_init)(void);
378 /* Create GIC node for the hardware domain */
379 int (*make_hwdom_dt_node)(const struct domain *d,
380 const struct dt_device_node *gic, void *fdt);
381 /* Create MADT table for the hardware domain */
382 int (*make_hwdom_madt)(const struct domain *d, u32 offset);
383 /* Map extra GIC MMIO, irqs and other hw stuffs to the hardware domain. */
384 int (*map_hwdom_extra_mappings)(struct domain *d);
385 /* Query the size of hardware domain madt table */
386 unsigned long (*get_hwdom_extra_madt_size)(const struct domain *d);
387 /* Deny access to GIC regions */
388 int (*iomem_deny_access)(const struct domain *d);
389 /* Handle LPIs, which require special handling */
390 void (*do_LPI)(unsigned int lpi);
391 };
392
393 extern const struct gic_hw_operations *gic_hw_ops;
394
gic_get_nr_lrs(void)395 static inline unsigned int gic_get_nr_lrs(void)
396 {
397 return gic_hw_ops->info->nr_lrs;
398 }
399
400 /*
401 * Set the active state of an IRQ. This should be used with care, as this
402 * directly forces the active bit, without considering the GIC state machine.
403 * For private IRQs this only works for those of the current CPU.
404 *
405 * This function should only be called for interrupts routed to the
406 * guest. The flow of interrupts routed to Xen is not able cope with
407 * software changes to the active state.
408 */
gic_set_active_state(struct irq_desc * irqd,bool state)409 static inline void gic_set_active_state(struct irq_desc *irqd, bool state)
410 {
411 ASSERT(test_bit(_IRQ_GUEST, &irqd->status));
412 gic_hw_ops->set_active_state(irqd, state);
413 }
414
415 /*
416 * Set the pending state of an IRQ. This should be used with care, as this
417 * directly forces the pending bit, without considering the GIC state machine.
418 * For private IRQs this only works for those of the current CPU.
419 */
gic_set_pending_state(struct irq_desc * irqd,bool state)420 static inline void gic_set_pending_state(struct irq_desc *irqd, bool state)
421 {
422 gic_hw_ops->set_pending_state(irqd, state);
423 }
424
425 /*
426 * Read the pending state of an interrupt from the distributor.
427 * For private IRQs this only works for those of the current CPU.
428 */
gic_read_pending_state(struct irq_desc * irqd)429 static inline bool gic_read_pending_state(struct irq_desc *irqd)
430 {
431 return gic_hw_ops->read_pending_state(irqd);
432 }
433
434 void register_gic_ops(const struct gic_hw_operations *ops);
435 int gic_make_hwdom_dt_node(const struct domain *d,
436 const struct dt_device_node *gic,
437 void *fdt);
438 int gic_make_hwdom_madt(const struct domain *d, u32 offset);
439 unsigned long gic_get_hwdom_madt_size(const struct domain *d);
440 int gic_map_hwdom_extra_mappings(struct domain *d);
441 int gic_iomem_deny_access(const struct domain *d);
442
443 #endif /* __ASSEMBLY__ */
444 #endif
445
446 /*
447 * Local variables:
448 * mode: C
449 * c-file-style: "BSD"
450 * c-basic-offset: 4
451 * indent-tabs-mode: nil
452 * End:
453 */
454