1 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
2 /*
3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4  * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
5  */
6 
7 #ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
8 #define _DT_BINDINGS_STM32MP1_CLKS_H_
9 
10 /* OSCILLATOR clocks */
11 #define CK_HSE		0
12 #define CK_CSI		1
13 #define CK_LSI		2
14 #define CK_LSE		3
15 #define CK_HSI		4
16 #define CK_HSE_DIV2	5
17 
18 /* Bus clocks */
19 #define TIM2		6
20 #define TIM3		7
21 #define TIM4		8
22 #define TIM5		9
23 #define TIM6		10
24 #define TIM7		11
25 #define TIM12		12
26 #define TIM13		13
27 #define TIM14		14
28 #define LPTIM1		15
29 #define SPI2		16
30 #define SPI3		17
31 #define USART2		18
32 #define USART3		19
33 #define UART4		20
34 #define UART5		21
35 #define UART7		22
36 #define UART8		23
37 #define I2C1		24
38 #define I2C2		25
39 #define I2C3		26
40 #define I2C5		27
41 #define SPDIF		28
42 #define CEC		29
43 #define DAC12		30
44 #define MDIO		31
45 #define TIM1		32
46 #define TIM8		33
47 #define TIM15		34
48 #define TIM16		35
49 #define TIM17		36
50 #define SPI1		37
51 #define SPI4		38
52 #define SPI5		39
53 #define USART6		40
54 #define SAI1		41
55 #define SAI2		42
56 #define SAI3		43
57 #define DFSDM		44
58 #define FDCAN		45
59 #define LPTIM2		46
60 #define LPTIM3		47
61 #define LPTIM4		48
62 #define LPTIM5		49
63 #define SAI4		50
64 #define SYSCFG		51
65 #define VREF		52
66 #define TMPSENS		53
67 #define PMBCTRL		54
68 #define HDP		55
69 #define LTDC		56
70 #define DSI		57
71 #define IWDG2		58
72 #define USBPHY		59
73 #define STGENRO		60
74 #define SPI6		61
75 #define I2C4		62
76 #define I2C6		63
77 #define USART1		64
78 #define RTCAPB		65
79 #define TZC1		66
80 #define TZPC		67
81 #define IWDG1		68
82 #define BSEC		69
83 #define STGEN		70
84 #define DMA1		71
85 #define DMA2		72
86 #define DMAMUX		73
87 #define ADC12		74
88 #define USBO		75
89 #define SDMMC3		76
90 #define DCMI		77
91 #define CRYP2		78
92 #define HASH2		79
93 #define RNG2		80
94 #define CRC2		81
95 #define HSEM		82
96 #define IPCC		83
97 #define GPIOA		84
98 #define GPIOB		85
99 #define GPIOC		86
100 #define GPIOD		87
101 #define GPIOE		88
102 #define GPIOF		89
103 #define GPIOG		90
104 #define GPIOH		91
105 #define GPIOI		92
106 #define GPIOJ		93
107 #define GPIOK		94
108 #define GPIOZ		95
109 #define CRYP1		96
110 #define HASH1		97
111 #define RNG1		98
112 #define BKPSRAM		99
113 #define MDMA		100
114 #define GPU		101
115 #define ETHCK		102
116 #define ETHTX		103
117 #define ETHRX		104
118 #define ETHMAC		105
119 #define FMC		106
120 #define QSPI		107
121 #define SDMMC1		108
122 #define SDMMC2		109
123 #define CRC1		110
124 #define USBH		111
125 #define ETHSTP		112
126 #define TZC2		113
127 
128 /* Kernel clocks */
129 #define SDMMC1_K	118
130 #define SDMMC2_K	119
131 #define SDMMC3_K	120
132 #define FMC_K		121
133 #define QSPI_K		122
134 #define ETHCK_K		123
135 #define RNG1_K		124
136 #define RNG2_K		125
137 #define GPU_K		126
138 #define USBPHY_K	127
139 #define STGEN_K		128
140 #define SPDIF_K		129
141 #define SPI1_K		130
142 #define SPI2_K		131
143 #define SPI3_K		132
144 #define SPI4_K		133
145 #define SPI5_K		134
146 #define SPI6_K		135
147 #define CEC_K		136
148 #define I2C1_K		137
149 #define I2C2_K		138
150 #define I2C3_K		139
151 #define I2C4_K		140
152 #define I2C5_K		141
153 #define I2C6_K		142
154 #define LPTIM1_K	143
155 #define LPTIM2_K	144
156 #define LPTIM3_K	145
157 #define LPTIM4_K	146
158 #define LPTIM5_K	147
159 #define USART1_K	148
160 #define USART2_K	149
161 #define USART3_K	150
162 #define UART4_K		151
163 #define UART5_K		152
164 #define USART6_K	153
165 #define UART7_K		154
166 #define UART8_K		155
167 #define DFSDM_K		156
168 #define FDCAN_K		157
169 #define SAI1_K		158
170 #define SAI2_K		159
171 #define SAI3_K		160
172 #define SAI4_K		161
173 #define ADC12_K		162
174 #define DSI_K		163
175 #define DSI_PX		164
176 #define ADFSDM_K	165
177 #define USBO_K		166
178 #define LTDC_PX		167
179 #define DAC12_K		168
180 #define ETHPTP_K	169
181 
182 /* PLL */
183 #define PLL1		176
184 #define PLL2		177
185 #define PLL3		178
186 #define PLL4		179
187 
188 /* ODF */
189 #define PLL1_P		180
190 #define PLL1_Q		181
191 #define PLL1_R		182
192 #define PLL2_P		183
193 #define PLL2_Q		184
194 #define PLL2_R		185
195 #define PLL3_P		186
196 #define PLL3_Q		187
197 #define PLL3_R		188
198 #define PLL4_P		189
199 #define PLL4_Q		190
200 #define PLL4_R		191
201 
202 /* AUX */
203 #define RTC		192
204 
205 /* MCLK */
206 #define CK_PER		193
207 #define CK_MPU		194
208 #define CK_AXI		195
209 #define CK_MCU		196
210 
211 /* Time base */
212 #define TIM2_K		197
213 #define TIM3_K		198
214 #define TIM4_K		199
215 #define TIM5_K		200
216 #define TIM6_K		201
217 #define TIM7_K		202
218 #define TIM12_K		203
219 #define TIM13_K		204
220 #define TIM14_K		205
221 #define TIM1_K		206
222 #define TIM8_K		207
223 #define TIM15_K		208
224 #define TIM16_K		209
225 #define TIM17_K		210
226 
227 /* MCO clocks */
228 #define CK_MCO1		211
229 #define CK_MCO2		212
230 
231 /* TRACE & DEBUG clocks */
232 #define CK_DBG		214
233 #define CK_TRACE	215
234 
235 /* DDR */
236 #define DDRC1		220
237 #define DDRC1LP		221
238 #define DDRC2		222
239 #define DDRC2LP		223
240 #define DDRPHYC		224
241 #define DDRPHYCLP	225
242 #define DDRCAPB		226
243 #define DDRCAPBLP	227
244 #define AXIDCG		228
245 #define DDRPHYCAPB	229
246 #define DDRPHYCAPBLP	230
247 #define DDRPERFM	231
248 
249 #define STM32MP1_LAST_CLK 232
250 
251 #define LTDC_K		LTDC_PX
252 #define ETHMAC_K	ETHCK_K
253 
254 /* SCMI clock identifiers */
255 #define CK_SCMI0_HSE		0
256 #define CK_SCMI0_HSI		1
257 #define CK_SCMI0_CSI		2
258 #define CK_SCMI0_LSE		3
259 #define CK_SCMI0_LSI		4
260 #define CK_SCMI0_PLL2_Q		5
261 #define CK_SCMI0_PLL2_R		6
262 #define CK_SCMI0_MPU		7
263 #define CK_SCMI0_AXI		8
264 #define CK_SCMI0_BSEC		9
265 #define CK_SCMI0_CRYP1		10
266 #define CK_SCMI0_GPIOZ		11
267 #define CK_SCMI0_HASH1		12
268 #define CK_SCMI0_I2C4		13
269 #define CK_SCMI0_I2C6		14
270 #define CK_SCMI0_IWDG1		15
271 #define CK_SCMI0_RNG1		16
272 #define CK_SCMI0_RTC		17
273 #define CK_SCMI0_RTCAPB		18
274 #define CK_SCMI0_SPI6		19
275 #define CK_SCMI0_USART1		20
276 
277 #define CK_SCMI1_PLL3_Q		0
278 #define CK_SCMI1_PLL3_R		1
279 #define CK_SCMI1_MCU		2
280 
281 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
282