1 /*
2  * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef ARCH_H
8 #define ARCH_H
9 
10 #include <lib/utils_def.h>
11 
12 /*******************************************************************************
13  * MIDR bit definitions
14  ******************************************************************************/
15 #define MIDR_IMPL_MASK		U(0xff)
16 #define MIDR_IMPL_SHIFT		U(24)
17 #define MIDR_VAR_SHIFT		U(20)
18 #define MIDR_VAR_BITS		U(4)
19 #define MIDR_REV_SHIFT		U(0)
20 #define MIDR_REV_BITS		U(4)
21 #define MIDR_PN_MASK		U(0xfff)
22 #define MIDR_PN_SHIFT		U(4)
23 
24 /*******************************************************************************
25  * MPIDR macros
26  ******************************************************************************/
27 #define MPIDR_MT_MASK		(U(1) << 24)
28 #define MPIDR_CPU_MASK		MPIDR_AFFLVL_MASK
29 #define MPIDR_CLUSTER_MASK	(MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
30 #define MPIDR_AFFINITY_BITS	U(8)
31 #define MPIDR_AFFLVL_MASK	U(0xff)
32 #define MPIDR_AFFLVL_SHIFT	U(3)
33 #define MPIDR_AFF0_SHIFT	U(0)
34 #define MPIDR_AFF1_SHIFT	U(8)
35 #define MPIDR_AFF2_SHIFT	U(16)
36 #define MPIDR_AFF_SHIFT(_n)	MPIDR_AFF##_n##_SHIFT
37 #define MPIDR_AFFINITY_MASK	U(0x00ffffff)
38 #define MPIDR_AFFLVL0		U(0)
39 #define MPIDR_AFFLVL1		U(1)
40 #define MPIDR_AFFLVL2		U(2)
41 #define MPIDR_AFFLVL(_n)	MPIDR_AFFLVL##_n
42 
43 #define MPIDR_AFFLVL0_VAL(mpidr) \
44 		(((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
45 #define MPIDR_AFFLVL1_VAL(mpidr) \
46 		(((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
47 #define MPIDR_AFFLVL2_VAL(mpidr) \
48 		(((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
49 #define MPIDR_AFFLVL3_VAL(mpidr)	U(0)
50 
51 #define MPIDR_AFF_ID(mpid, n)					\
52 	(((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
53 
54 #define MPID_MASK		(MPIDR_MT_MASK				|\
55 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\
56 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\
57 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
58 
59 /*
60  * An invalid MPID. This value can be used by functions that return an MPID to
61  * indicate an error.
62  */
63 #define INVALID_MPID		U(0xFFFFFFFF)
64 
65 /*
66  * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
67  * add one while using this macro to define array sizes.
68  */
69 #define MPIDR_MAX_AFFLVL	U(2)
70 
71 /* Data Cache set/way op type defines */
72 #define DC_OP_ISW			U(0x0)
73 #define DC_OP_CISW			U(0x1)
74 #if ERRATA_A53_827319
75 #define DC_OP_CSW			DC_OP_CISW
76 #else
77 #define DC_OP_CSW			U(0x2)
78 #endif
79 
80 /*******************************************************************************
81  * Generic timer memory mapped registers & offsets
82  ******************************************************************************/
83 #define CNTCR_OFF			U(0x000)
84 /* Counter Count Value Lower register */
85 #define CNTCVL_OFF			U(0x008)
86 /* Counter Count Value Upper register */
87 #define CNTCVU_OFF			U(0x00C)
88 #define CNTFID_OFF			U(0x020)
89 
90 #define CNTCR_EN			(U(1) << 0)
91 #define CNTCR_HDBG			(U(1) << 1)
92 #define CNTCR_FCREQ(x)			((x) << 8)
93 
94 /*******************************************************************************
95  * System register bit definitions
96  ******************************************************************************/
97 /* CLIDR definitions */
98 #define LOUIS_SHIFT		U(21)
99 #define LOC_SHIFT		U(24)
100 #define CLIDR_FIELD_WIDTH	U(3)
101 
102 /* CSSELR definitions */
103 #define LEVEL_SHIFT		U(1)
104 
105 /* ID_DFR0_EL1 definitions */
106 #define ID_DFR0_COPTRC_SHIFT		U(12)
107 #define ID_DFR0_COPTRC_MASK		U(0xf)
108 #define ID_DFR0_COPTRC_SUPPORTED	U(1)
109 #define ID_DFR0_COPTRC_LENGTH		U(4)
110 #define ID_DFR0_TRACEFILT_SHIFT		U(28)
111 #define ID_DFR0_TRACEFILT_MASK		U(0xf)
112 #define ID_DFR0_TRACEFILT_SUPPORTED	U(1)
113 #define ID_DFR0_TRACEFILT_LENGTH	U(4)
114 
115 /* ID_DFR1_EL1 definitions */
116 #define ID_DFR1_MTPMU_SHIFT	U(0)
117 #define ID_DFR1_MTPMU_MASK	U(0xf)
118 #define ID_DFR1_MTPMU_SUPPORTED	U(1)
119 
120 /* ID_MMFR4 definitions */
121 #define ID_MMFR4_CNP_SHIFT	U(12)
122 #define ID_MMFR4_CNP_LENGTH	U(4)
123 #define ID_MMFR4_CNP_MASK	U(0xf)
124 
125 /* ID_PFR0 definitions */
126 #define ID_PFR0_AMU_SHIFT	U(20)
127 #define ID_PFR0_AMU_LENGTH	U(4)
128 #define ID_PFR0_AMU_MASK	U(0xf)
129 #define ID_PFR0_AMU_NOT_SUPPORTED	U(0x0)
130 #define ID_PFR0_AMU_V1		U(0x1)
131 #define ID_PFR0_AMU_V1P1	U(0x2)
132 
133 #define ID_PFR0_DIT_SHIFT	U(24)
134 #define ID_PFR0_DIT_LENGTH	U(4)
135 #define ID_PFR0_DIT_MASK	U(0xf)
136 #define ID_PFR0_DIT_SUPPORTED	(U(1) << ID_PFR0_DIT_SHIFT)
137 
138 /* ID_PFR1 definitions */
139 #define ID_PFR1_VIRTEXT_SHIFT	U(12)
140 #define ID_PFR1_VIRTEXT_MASK	U(0xf)
141 #define GET_VIRT_EXT(id)	(((id) >> ID_PFR1_VIRTEXT_SHIFT) \
142 				 & ID_PFR1_VIRTEXT_MASK)
143 #define ID_PFR1_GENTIMER_SHIFT	U(16)
144 #define ID_PFR1_GENTIMER_MASK	U(0xf)
145 #define ID_PFR1_GIC_SHIFT	U(28)
146 #define ID_PFR1_GIC_MASK	U(0xf)
147 #define ID_PFR1_SEC_SHIFT	U(4)
148 #define ID_PFR1_SEC_MASK	U(0xf)
149 #define ID_PFR1_ELx_ENABLED	U(1)
150 
151 /* SCTLR definitions */
152 #define SCTLR_RES1_DEF		((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
153 				 (U(1) << 3))
154 #if ARM_ARCH_MAJOR == 7
155 #define SCTLR_RES1		SCTLR_RES1_DEF
156 #else
157 #define SCTLR_RES1		(SCTLR_RES1_DEF | (U(1) << 11))
158 #endif
159 #define SCTLR_M_BIT		(U(1) << 0)
160 #define SCTLR_A_BIT		(U(1) << 1)
161 #define SCTLR_C_BIT		(U(1) << 2)
162 #define SCTLR_CP15BEN_BIT	(U(1) << 5)
163 #define SCTLR_ITD_BIT		(U(1) << 7)
164 #define SCTLR_Z_BIT		(U(1) << 11)
165 #define SCTLR_I_BIT		(U(1) << 12)
166 #define SCTLR_V_BIT		(U(1) << 13)
167 #define SCTLR_RR_BIT		(U(1) << 14)
168 #define SCTLR_NTWI_BIT		(U(1) << 16)
169 #define SCTLR_NTWE_BIT		(U(1) << 18)
170 #define SCTLR_WXN_BIT		(U(1) << 19)
171 #define SCTLR_UWXN_BIT		(U(1) << 20)
172 #define SCTLR_EE_BIT		(U(1) << 25)
173 #define SCTLR_TRE_BIT		(U(1) << 28)
174 #define SCTLR_AFE_BIT		(U(1) << 29)
175 #define SCTLR_TE_BIT		(U(1) << 30)
176 #define SCTLR_DSSBS_BIT		(U(1) << 31)
177 #define SCTLR_RESET_VAL         (SCTLR_RES1 | SCTLR_NTWE_BIT |		\
178 				SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
179 
180 /* SDCR definitions */
181 #define SDCR_SPD(x)		((x) << 14)
182 #define SDCR_SPD_LEGACY		U(0x0)
183 #define SDCR_SPD_DISABLE	U(0x2)
184 #define SDCR_SPD_ENABLE		U(0x3)
185 #define SDCR_SCCD_BIT		(U(1) << 23)
186 #define SDCR_TTRF_BIT		(U(1) << 19)
187 #define SDCR_SPME_BIT		(U(1) << 17)
188 #define SDCR_RESET_VAL		U(0x0)
189 #define SDCR_MTPME_BIT		(U(1) << 28)
190 
191 /* HSCTLR definitions */
192 #define HSCTLR_RES1	((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
193 			 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
194 			 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
195 
196 #define HSCTLR_M_BIT		(U(1) << 0)
197 #define HSCTLR_A_BIT		(U(1) << 1)
198 #define HSCTLR_C_BIT		(U(1) << 2)
199 #define HSCTLR_CP15BEN_BIT	(U(1) << 5)
200 #define HSCTLR_ITD_BIT		(U(1) << 7)
201 #define HSCTLR_SED_BIT		(U(1) << 8)
202 #define HSCTLR_I_BIT		(U(1) << 12)
203 #define HSCTLR_WXN_BIT		(U(1) << 19)
204 #define HSCTLR_EE_BIT		(U(1) << 25)
205 #define HSCTLR_TE_BIT		(U(1) << 30)
206 
207 /* CPACR definitions */
208 #define CPACR_FPEN(x)		((x) << 20)
209 #define CPACR_FP_TRAP_PL0	UL(0x1)
210 #define CPACR_FP_TRAP_ALL	UL(0x2)
211 #define CPACR_FP_TRAP_NONE	UL(0x3)
212 
213 /* SCR definitions */
214 #define SCR_TWE_BIT		(UL(1) << 13)
215 #define SCR_TWI_BIT		(UL(1) << 12)
216 #define SCR_SIF_BIT		(UL(1) << 9)
217 #define SCR_HCE_BIT		(UL(1) << 8)
218 #define SCR_SCD_BIT		(UL(1) << 7)
219 #define SCR_NET_BIT		(UL(1) << 6)
220 #define SCR_AW_BIT		(UL(1) << 5)
221 #define SCR_FW_BIT		(UL(1) << 4)
222 #define SCR_EA_BIT		(UL(1) << 3)
223 #define SCR_FIQ_BIT		(UL(1) << 2)
224 #define SCR_IRQ_BIT		(UL(1) << 1)
225 #define SCR_NS_BIT		(UL(1) << 0)
226 #define SCR_VALID_BIT_MASK	U(0x33ff)
227 #define SCR_RESET_VAL		U(0x0)
228 
229 #define GET_NS_BIT(scr)		((scr) & SCR_NS_BIT)
230 
231 /* HCR definitions */
232 #define HCR_TGE_BIT		(U(1) << 27)
233 #define HCR_AMO_BIT		(U(1) << 5)
234 #define HCR_IMO_BIT		(U(1) << 4)
235 #define HCR_FMO_BIT		(U(1) << 3)
236 #define HCR_RESET_VAL		U(0x0)
237 
238 /* CNTHCTL definitions */
239 #define CNTHCTL_RESET_VAL	U(0x0)
240 #define PL1PCEN_BIT		(U(1) << 1)
241 #define PL1PCTEN_BIT		(U(1) << 0)
242 
243 /* CNTKCTL definitions */
244 #define PL0PTEN_BIT		(U(1) << 9)
245 #define PL0VTEN_BIT		(U(1) << 8)
246 #define PL0PCTEN_BIT		(U(1) << 0)
247 #define PL0VCTEN_BIT		(U(1) << 1)
248 #define EVNTEN_BIT		(U(1) << 2)
249 #define EVNTDIR_BIT		(U(1) << 3)
250 #define EVNTI_SHIFT		U(4)
251 #define EVNTI_MASK		U(0xf)
252 
253 /* HCPTR definitions */
254 #define HCPTR_RES1		((U(1) << 13) | (U(1) << 12) | U(0x3ff))
255 #define TCPAC_BIT		(U(1) << 31)
256 #define TAM_SHIFT		U(30)
257 #define TAM_BIT			(U(1) << TAM_SHIFT)
258 #define TTA_BIT			(U(1) << 20)
259 #define TCP11_BIT		(U(1) << 11)
260 #define TCP10_BIT		(U(1) << 10)
261 #define HCPTR_RESET_VAL		HCPTR_RES1
262 
263 /* VTTBR defintions */
264 #define VTTBR_RESET_VAL		ULL(0x0)
265 #define VTTBR_VMID_MASK		ULL(0xff)
266 #define VTTBR_VMID_SHIFT	U(48)
267 #define VTTBR_BADDR_MASK	ULL(0xffffffffffff)
268 #define VTTBR_BADDR_SHIFT	U(0)
269 
270 /* HDCR definitions */
271 #define HDCR_MTPME_BIT		(U(1) << 28)
272 #define HDCR_HLP_BIT		(U(1) << 26)
273 #define HDCR_HPME_BIT		(U(1) << 7)
274 #define HDCR_RESET_VAL		U(0x0)
275 
276 /* HSTR definitions */
277 #define HSTR_RESET_VAL		U(0x0)
278 
279 /* CNTHP_CTL definitions */
280 #define CNTHP_CTL_RESET_VAL	U(0x0)
281 
282 /* NSACR definitions */
283 #define NSASEDIS_BIT		(U(1) << 15)
284 #define NSTRCDIS_BIT		(U(1) << 20)
285 #define NSACR_CP11_BIT		(U(1) << 11)
286 #define NSACR_CP10_BIT		(U(1) << 10)
287 #define NSACR_IMP_DEF_MASK	(U(0x7) << 16)
288 #define NSACR_ENABLE_FP_ACCESS	(NSACR_CP11_BIT | NSACR_CP10_BIT)
289 #define NSACR_RESET_VAL		U(0x0)
290 
291 /* CPACR definitions */
292 #define ASEDIS_BIT		(U(1) << 31)
293 #define TRCDIS_BIT		(U(1) << 28)
294 #define CPACR_CP11_SHIFT	U(22)
295 #define CPACR_CP10_SHIFT	U(20)
296 #define CPACR_ENABLE_FP_ACCESS	((U(0x3) << CPACR_CP11_SHIFT) |\
297 				 (U(0x3) << CPACR_CP10_SHIFT))
298 #define CPACR_RESET_VAL         U(0x0)
299 
300 /* FPEXC definitions */
301 #define FPEXC_RES1		((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
302 #define FPEXC_EN_BIT		(U(1) << 30)
303 #define FPEXC_RESET_VAL		FPEXC_RES1
304 
305 /* SPSR/CPSR definitions */
306 #define SPSR_FIQ_BIT		(U(1) << 0)
307 #define SPSR_IRQ_BIT		(U(1) << 1)
308 #define SPSR_ABT_BIT		(U(1) << 2)
309 #define SPSR_AIF_SHIFT		U(6)
310 #define SPSR_AIF_MASK		U(0x7)
311 
312 #define SPSR_E_SHIFT		U(9)
313 #define SPSR_E_MASK		U(0x1)
314 #define SPSR_E_LITTLE		U(0)
315 #define SPSR_E_BIG		U(1)
316 
317 #define SPSR_T_SHIFT		U(5)
318 #define SPSR_T_MASK		U(0x1)
319 #define SPSR_T_ARM		U(0)
320 #define SPSR_T_THUMB		U(1)
321 
322 #define SPSR_MODE_SHIFT		U(0)
323 #define SPSR_MODE_MASK		U(0x7)
324 
325 #define SPSR_SSBS_BIT		BIT_32(23)
326 
327 #define DISABLE_ALL_EXCEPTIONS \
328 		(SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
329 
330 #define CPSR_DIT_BIT		(U(1) << 21)
331 /*
332  * TTBCR definitions
333  */
334 #define TTBCR_EAE_BIT		(U(1) << 31)
335 
336 #define TTBCR_SH1_NON_SHAREABLE		(U(0x0) << 28)
337 #define TTBCR_SH1_OUTER_SHAREABLE	(U(0x2) << 28)
338 #define TTBCR_SH1_INNER_SHAREABLE	(U(0x3) << 28)
339 
340 #define TTBCR_RGN1_OUTER_NC	(U(0x0) << 26)
341 #define TTBCR_RGN1_OUTER_WBA	(U(0x1) << 26)
342 #define TTBCR_RGN1_OUTER_WT	(U(0x2) << 26)
343 #define TTBCR_RGN1_OUTER_WBNA	(U(0x3) << 26)
344 
345 #define TTBCR_RGN1_INNER_NC	(U(0x0) << 24)
346 #define TTBCR_RGN1_INNER_WBA	(U(0x1) << 24)
347 #define TTBCR_RGN1_INNER_WT	(U(0x2) << 24)
348 #define TTBCR_RGN1_INNER_WBNA	(U(0x3) << 24)
349 
350 #define TTBCR_EPD1_BIT		(U(1) << 23)
351 #define TTBCR_A1_BIT		(U(1) << 22)
352 
353 #define TTBCR_T1SZ_SHIFT	U(16)
354 #define TTBCR_T1SZ_MASK		U(0x7)
355 #define TTBCR_TxSZ_MIN		U(0)
356 #define TTBCR_TxSZ_MAX		U(7)
357 
358 #define TTBCR_SH0_NON_SHAREABLE		(U(0x0) << 12)
359 #define TTBCR_SH0_OUTER_SHAREABLE	(U(0x2) << 12)
360 #define TTBCR_SH0_INNER_SHAREABLE	(U(0x3) << 12)
361 
362 #define TTBCR_RGN0_OUTER_NC	(U(0x0) << 10)
363 #define TTBCR_RGN0_OUTER_WBA	(U(0x1) << 10)
364 #define TTBCR_RGN0_OUTER_WT	(U(0x2) << 10)
365 #define TTBCR_RGN0_OUTER_WBNA	(U(0x3) << 10)
366 
367 #define TTBCR_RGN0_INNER_NC	(U(0x0) << 8)
368 #define TTBCR_RGN0_INNER_WBA	(U(0x1) << 8)
369 #define TTBCR_RGN0_INNER_WT	(U(0x2) << 8)
370 #define TTBCR_RGN0_INNER_WBNA	(U(0x3) << 8)
371 
372 #define TTBCR_EPD0_BIT		(U(1) << 7)
373 #define TTBCR_T0SZ_SHIFT	U(0)
374 #define TTBCR_T0SZ_MASK		U(0x7)
375 
376 /*
377  * HTCR definitions
378  */
379 #define HTCR_RES1			((U(1) << 31) | (U(1) << 23))
380 
381 #define HTCR_SH0_NON_SHAREABLE		(U(0x0) << 12)
382 #define HTCR_SH0_OUTER_SHAREABLE	(U(0x2) << 12)
383 #define HTCR_SH0_INNER_SHAREABLE	(U(0x3) << 12)
384 
385 #define HTCR_RGN0_OUTER_NC	(U(0x0) << 10)
386 #define HTCR_RGN0_OUTER_WBA	(U(0x1) << 10)
387 #define HTCR_RGN0_OUTER_WT	(U(0x2) << 10)
388 #define HTCR_RGN0_OUTER_WBNA	(U(0x3) << 10)
389 
390 #define HTCR_RGN0_INNER_NC	(U(0x0) << 8)
391 #define HTCR_RGN0_INNER_WBA	(U(0x1) << 8)
392 #define HTCR_RGN0_INNER_WT	(U(0x2) << 8)
393 #define HTCR_RGN0_INNER_WBNA	(U(0x3) << 8)
394 
395 #define HTCR_T0SZ_SHIFT		U(0)
396 #define HTCR_T0SZ_MASK		U(0x7)
397 
398 #define MODE_RW_SHIFT		U(0x4)
399 #define MODE_RW_MASK		U(0x1)
400 #define MODE_RW_32		U(0x1)
401 
402 #define MODE32_SHIFT		U(0)
403 #define MODE32_MASK		U(0x1f)
404 #define MODE32_usr		U(0x10)
405 #define MODE32_fiq		U(0x11)
406 #define MODE32_irq		U(0x12)
407 #define MODE32_svc		U(0x13)
408 #define MODE32_mon		U(0x16)
409 #define MODE32_abt		U(0x17)
410 #define MODE32_hyp		U(0x1a)
411 #define MODE32_und		U(0x1b)
412 #define MODE32_sys		U(0x1f)
413 
414 #define GET_M32(mode)		(((mode) >> MODE32_SHIFT) & MODE32_MASK)
415 
416 #define SPSR_MODE32(mode, isa, endian, aif) \
417 ( \
418 	( \
419 		(MODE_RW_32 << MODE_RW_SHIFT) | \
420 		(((mode) & MODE32_MASK) << MODE32_SHIFT) | \
421 		(((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
422 		(((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
423 		(((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \
424 	) & \
425 	(~(SPSR_SSBS_BIT)) \
426 )
427 
428 /*
429  * TTBR definitions
430  */
431 #define TTBR_CNP_BIT		ULL(0x1)
432 
433 /*
434  * CTR definitions
435  */
436 #define CTR_CWG_SHIFT		U(24)
437 #define CTR_CWG_MASK		U(0xf)
438 #define CTR_ERG_SHIFT		U(20)
439 #define CTR_ERG_MASK		U(0xf)
440 #define CTR_DMINLINE_SHIFT	U(16)
441 #define CTR_DMINLINE_WIDTH	U(4)
442 #define CTR_DMINLINE_MASK	((U(1) << 4) - U(1))
443 #define CTR_L1IP_SHIFT		U(14)
444 #define CTR_L1IP_MASK		U(0x3)
445 #define CTR_IMINLINE_SHIFT	U(0)
446 #define CTR_IMINLINE_MASK	U(0xf)
447 
448 #define MAX_CACHE_LINE_SIZE	U(0x800) /* 2KB */
449 
450 /* PMCR definitions */
451 #define PMCR_N_SHIFT		U(11)
452 #define PMCR_N_MASK		U(0x1f)
453 #define PMCR_N_BITS		(PMCR_N_MASK << PMCR_N_SHIFT)
454 #define PMCR_LP_BIT		(U(1) << 7)
455 #define PMCR_LC_BIT		(U(1) << 6)
456 #define PMCR_DP_BIT		(U(1) << 5)
457 #define	PMCR_RESET_VAL		U(0x0)
458 
459 /*******************************************************************************
460  * Definitions of register offsets, fields and macros for CPU system
461  * instructions.
462  ******************************************************************************/
463 
464 #define TLBI_ADDR_SHIFT		U(0)
465 #define TLBI_ADDR_MASK		U(0xFFFFF000)
466 #define TLBI_ADDR(x)		(((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
467 
468 /*******************************************************************************
469  * Definitions of register offsets and fields in the CNTCTLBase Frame of the
470  * system level implementation of the Generic Timer.
471  ******************************************************************************/
472 #define CNTCTLBASE_CNTFRQ	U(0x0)
473 #define CNTNSAR			U(0x4)
474 #define CNTNSAR_NS_SHIFT(x)	(x)
475 
476 #define CNTACR_BASE(x)		(U(0x40) + ((x) << 2))
477 #define CNTACR_RPCT_SHIFT	U(0x0)
478 #define CNTACR_RVCT_SHIFT	U(0x1)
479 #define CNTACR_RFRQ_SHIFT	U(0x2)
480 #define CNTACR_RVOFF_SHIFT	U(0x3)
481 #define CNTACR_RWVT_SHIFT	U(0x4)
482 #define CNTACR_RWPT_SHIFT	U(0x5)
483 
484 /*******************************************************************************
485  * Definitions of register offsets and fields in the CNTBaseN Frame of the
486  * system level implementation of the Generic Timer.
487  ******************************************************************************/
488 /* Physical Count register. */
489 #define CNTPCT_LO		U(0x0)
490 /* Counter Frequency register. */
491 #define CNTBASEN_CNTFRQ		U(0x10)
492 /* Physical Timer CompareValue register. */
493 #define CNTP_CVAL_LO		U(0x20)
494 /* Physical Timer Control register. */
495 #define CNTP_CTL		U(0x2c)
496 
497 /* Physical timer control register bit fields shifts and masks */
498 #define CNTP_CTL_ENABLE_SHIFT   0
499 #define CNTP_CTL_IMASK_SHIFT    1
500 #define CNTP_CTL_ISTATUS_SHIFT  2
501 
502 #define CNTP_CTL_ENABLE_MASK    U(1)
503 #define CNTP_CTL_IMASK_MASK     U(1)
504 #define CNTP_CTL_ISTATUS_MASK   U(1)
505 
506 /* MAIR macros */
507 #define MAIR0_ATTR_SET(attr, index)	((attr) << ((index) << U(3)))
508 #define MAIR1_ATTR_SET(attr, index)	((attr) << (((index) - U(3)) << U(3)))
509 
510 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
511 #define SCR		p15, 0, c1, c1, 0
512 #define SCTLR		p15, 0, c1, c0, 0
513 #define ACTLR		p15, 0, c1, c0, 1
514 #define SDCR		p15, 0, c1, c3, 1
515 #define MPIDR		p15, 0, c0, c0, 5
516 #define MIDR		p15, 0, c0, c0, 0
517 #define HVBAR		p15, 4, c12, c0, 0
518 #define VBAR		p15, 0, c12, c0, 0
519 #define MVBAR		p15, 0, c12, c0, 1
520 #define NSACR		p15, 0, c1, c1, 2
521 #define CPACR		p15, 0, c1, c0, 2
522 #define DCCIMVAC	p15, 0, c7, c14, 1
523 #define DCCMVAC		p15, 0, c7, c10, 1
524 #define DCIMVAC		p15, 0, c7, c6, 1
525 #define DCCISW		p15, 0, c7, c14, 2
526 #define DCCSW		p15, 0, c7, c10, 2
527 #define DCISW		p15, 0, c7, c6, 2
528 #define CTR		p15, 0, c0, c0, 1
529 #define CNTFRQ		p15, 0, c14, c0, 0
530 #define ID_MMFR4	p15, 0, c0, c2, 6
531 #define ID_DFR0		p15, 0, c0, c1, 2
532 #define ID_DFR1		p15, 0, c0, c3, 5
533 #define ID_PFR0		p15, 0, c0, c1, 0
534 #define ID_PFR1		p15, 0, c0, c1, 1
535 #define MAIR0		p15, 0, c10, c2, 0
536 #define MAIR1		p15, 0, c10, c2, 1
537 #define TTBCR		p15, 0, c2, c0, 2
538 #define TTBR0		p15, 0, c2, c0, 0
539 #define TTBR1		p15, 0, c2, c0, 1
540 #define TLBIALL		p15, 0, c8, c7, 0
541 #define TLBIALLH	p15, 4, c8, c7, 0
542 #define TLBIALLIS	p15, 0, c8, c3, 0
543 #define TLBIMVA		p15, 0, c8, c7, 1
544 #define TLBIMVAA	p15, 0, c8, c7, 3
545 #define TLBIMVAAIS	p15, 0, c8, c3, 3
546 #define TLBIMVAHIS	p15, 4, c8, c3, 1
547 #define BPIALLIS	p15, 0, c7, c1, 6
548 #define BPIALL		p15, 0, c7, c5, 6
549 #define ICIALLU		p15, 0, c7, c5, 0
550 #define HSCTLR		p15, 4, c1, c0, 0
551 #define HCR		p15, 4, c1, c1, 0
552 #define HCPTR		p15, 4, c1, c1, 2
553 #define HSTR		p15, 4, c1, c1, 3
554 #define CNTHCTL		p15, 4, c14, c1, 0
555 #define CNTKCTL		p15, 0, c14, c1, 0
556 #define VPIDR		p15, 4, c0, c0, 0
557 #define VMPIDR		p15, 4, c0, c0, 5
558 #define ISR		p15, 0, c12, c1, 0
559 #define CLIDR		p15, 1, c0, c0, 1
560 #define CSSELR		p15, 2, c0, c0, 0
561 #define CCSIDR		p15, 1, c0, c0, 0
562 #define HTCR		p15, 4, c2, c0, 2
563 #define HMAIR0		p15, 4, c10, c2, 0
564 #define ATS1CPR		p15, 0, c7, c8, 0
565 #define ATS1HR		p15, 4, c7, c8, 0
566 #define DBGOSDLR	p14, 0, c1, c3, 4
567 
568 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
569 #define HDCR		p15, 4, c1, c1, 1
570 #define PMCR		p15, 0, c9, c12, 0
571 #define CNTHP_TVAL	p15, 4, c14, c2, 0
572 #define CNTHP_CTL	p15, 4, c14, c2, 1
573 
574 /* AArch32 coproc registers for 32bit MMU descriptor support */
575 #define PRRR		p15, 0, c10, c2, 0
576 #define NMRR		p15, 0, c10, c2, 1
577 #define DACR		p15, 0, c3, c0, 0
578 
579 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
580 #define ICC_IAR1	p15, 0, c12, c12, 0
581 #define ICC_IAR0	p15, 0, c12, c8, 0
582 #define ICC_EOIR1	p15, 0, c12, c12, 1
583 #define ICC_EOIR0	p15, 0, c12, c8, 1
584 #define ICC_HPPIR1	p15, 0, c12, c12, 2
585 #define ICC_HPPIR0	p15, 0, c12, c8, 2
586 #define ICC_BPR1	p15, 0, c12, c12, 3
587 #define ICC_BPR0	p15, 0, c12, c8, 3
588 #define ICC_DIR		p15, 0, c12, c11, 1
589 #define ICC_PMR		p15, 0, c4, c6, 0
590 #define ICC_RPR		p15, 0, c12, c11, 3
591 #define ICC_CTLR	p15, 0, c12, c12, 4
592 #define ICC_MCTLR	p15, 6, c12, c12, 4
593 #define ICC_SRE		p15, 0, c12, c12, 5
594 #define ICC_HSRE	p15, 4, c12, c9, 5
595 #define ICC_MSRE	p15, 6, c12, c12, 5
596 #define ICC_IGRPEN0	p15, 0, c12, c12, 6
597 #define ICC_IGRPEN1	p15, 0, c12, c12, 7
598 #define ICC_MGRPEN1	p15, 6, c12, c12, 7
599 
600 /* 64 bit system register defines The format is: coproc, opt1, CRm */
601 #define TTBR0_64	p15, 0, c2
602 #define TTBR1_64	p15, 1, c2
603 #define CNTVOFF_64	p15, 4, c14
604 #define VTTBR_64	p15, 6, c2
605 #define CNTPCT_64	p15, 0, c14
606 #define HTTBR_64	p15, 4, c2
607 #define CNTHP_CVAL_64	p15, 6, c14
608 #define PAR_64		p15, 0, c7
609 
610 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
611 #define ICC_SGI1R_EL1_64	p15, 0, c12
612 #define ICC_ASGI1R_EL1_64	p15, 1, c12
613 #define ICC_SGI0R_EL1_64	p15, 2, c12
614 
615 /*******************************************************************************
616  * Definitions of MAIR encodings for device and normal memory
617  ******************************************************************************/
618 /*
619  * MAIR encodings for device memory attributes.
620  */
621 #define MAIR_DEV_nGnRnE		U(0x0)
622 #define MAIR_DEV_nGnRE		U(0x4)
623 #define MAIR_DEV_nGRE		U(0x8)
624 #define MAIR_DEV_GRE		U(0xc)
625 
626 /*
627  * MAIR encodings for normal memory attributes.
628  *
629  * Cache Policy
630  *  WT:	 Write Through
631  *  WB:	 Write Back
632  *  NC:	 Non-Cacheable
633  *
634  * Transient Hint
635  *  NTR: Non-Transient
636  *  TR:	 Transient
637  *
638  * Allocation Policy
639  *  RA:	 Read Allocate
640  *  WA:	 Write Allocate
641  *  RWA: Read and Write Allocate
642  *  NA:	 No Allocation
643  */
644 #define MAIR_NORM_WT_TR_WA	U(0x1)
645 #define MAIR_NORM_WT_TR_RA	U(0x2)
646 #define MAIR_NORM_WT_TR_RWA	U(0x3)
647 #define MAIR_NORM_NC		U(0x4)
648 #define MAIR_NORM_WB_TR_WA	U(0x5)
649 #define MAIR_NORM_WB_TR_RA	U(0x6)
650 #define MAIR_NORM_WB_TR_RWA	U(0x7)
651 #define MAIR_NORM_WT_NTR_NA	U(0x8)
652 #define MAIR_NORM_WT_NTR_WA	U(0x9)
653 #define MAIR_NORM_WT_NTR_RA	U(0xa)
654 #define MAIR_NORM_WT_NTR_RWA	U(0xb)
655 #define MAIR_NORM_WB_NTR_NA	U(0xc)
656 #define MAIR_NORM_WB_NTR_WA	U(0xd)
657 #define MAIR_NORM_WB_NTR_RA	U(0xe)
658 #define MAIR_NORM_WB_NTR_RWA	U(0xf)
659 
660 #define MAIR_NORM_OUTER_SHIFT	U(4)
661 
662 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer)	\
663 		((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
664 
665 /* PAR fields */
666 #define PAR_F_SHIFT	U(0)
667 #define PAR_F_MASK	ULL(0x1)
668 #define PAR_ADDR_SHIFT	U(12)
669 #define PAR_ADDR_MASK	(BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
670 
671 /*******************************************************************************
672  * Definitions for system register interface to AMU for FEAT_AMUv1
673  ******************************************************************************/
674 #define AMCR		p15, 0, c13, c2, 0
675 #define AMCFGR		p15, 0, c13, c2, 1
676 #define AMCGCR		p15, 0, c13, c2, 2
677 #define AMUSERENR	p15, 0, c13, c2, 3
678 #define AMCNTENCLR0	p15, 0, c13, c2, 4
679 #define AMCNTENSET0	p15, 0, c13, c2, 5
680 #define AMCNTENCLR1	p15, 0, c13, c3, 0
681 #define AMCNTENSET1	p15, 0, c13, c3, 1
682 
683 /* Activity Monitor Group 0 Event Counter Registers */
684 #define AMEVCNTR00	p15, 0, c0
685 #define AMEVCNTR01	p15, 1, c0
686 #define AMEVCNTR02	p15, 2, c0
687 #define AMEVCNTR03	p15, 3, c0
688 
689 /* Activity Monitor Group 0 Event Type Registers */
690 #define AMEVTYPER00	p15, 0, c13, c6, 0
691 #define AMEVTYPER01	p15, 0, c13, c6, 1
692 #define AMEVTYPER02	p15, 0, c13, c6, 2
693 #define AMEVTYPER03	p15, 0, c13, c6, 3
694 
695 /* Activity Monitor Group 1 Event Counter Registers */
696 #define AMEVCNTR10	p15, 0, c4
697 #define AMEVCNTR11	p15, 1, c4
698 #define AMEVCNTR12	p15, 2, c4
699 #define AMEVCNTR13	p15, 3, c4
700 #define AMEVCNTR14	p15, 4, c4
701 #define AMEVCNTR15	p15, 5, c4
702 #define AMEVCNTR16	p15, 6, c4
703 #define AMEVCNTR17	p15, 7, c4
704 #define AMEVCNTR18	p15, 0, c5
705 #define AMEVCNTR19	p15, 1, c5
706 #define AMEVCNTR1A	p15, 2, c5
707 #define AMEVCNTR1B	p15, 3, c5
708 #define AMEVCNTR1C	p15, 4, c5
709 #define AMEVCNTR1D	p15, 5, c5
710 #define AMEVCNTR1E	p15, 6, c5
711 #define AMEVCNTR1F	p15, 7, c5
712 
713 /* Activity Monitor Group 1 Event Type Registers */
714 #define AMEVTYPER10	p15, 0, c13, c14, 0
715 #define AMEVTYPER11	p15, 0, c13, c14, 1
716 #define AMEVTYPER12	p15, 0, c13, c14, 2
717 #define AMEVTYPER13	p15, 0, c13, c14, 3
718 #define AMEVTYPER14	p15, 0, c13, c14, 4
719 #define AMEVTYPER15	p15, 0, c13, c14, 5
720 #define AMEVTYPER16	p15, 0, c13, c14, 6
721 #define AMEVTYPER17	p15, 0, c13, c14, 7
722 #define AMEVTYPER18	p15, 0, c13, c15, 0
723 #define AMEVTYPER19	p15, 0, c13, c15, 1
724 #define AMEVTYPER1A	p15, 0, c13, c15, 2
725 #define AMEVTYPER1B	p15, 0, c13, c15, 3
726 #define AMEVTYPER1C	p15, 0, c13, c15, 4
727 #define AMEVTYPER1D	p15, 0, c13, c15, 5
728 #define AMEVTYPER1E	p15, 0, c13, c15, 6
729 #define AMEVTYPER1F	p15, 0, c13, c15, 7
730 
731 /* AMCNTENSET0 definitions */
732 #define AMCNTENSET0_Pn_SHIFT	U(0)
733 #define AMCNTENSET0_Pn_MASK	U(0xffff)
734 
735 /* AMCNTENSET1 definitions */
736 #define AMCNTENSET1_Pn_SHIFT	U(0)
737 #define AMCNTENSET1_Pn_MASK	U(0xffff)
738 
739 /* AMCNTENCLR0 definitions */
740 #define AMCNTENCLR0_Pn_SHIFT	U(0)
741 #define AMCNTENCLR0_Pn_MASK	U(0xffff)
742 
743 /* AMCNTENCLR1 definitions */
744 #define AMCNTENCLR1_Pn_SHIFT	U(0)
745 #define AMCNTENCLR1_Pn_MASK	U(0xffff)
746 
747 /* AMCR definitions */
748 #define AMCR_CG1RZ_SHIFT	U(17)
749 #define AMCR_CG1RZ_BIT		(ULL(1) << AMCR_CG1RZ_SHIFT)
750 
751 /* AMCFGR definitions */
752 #define AMCFGR_NCG_SHIFT	U(28)
753 #define AMCFGR_NCG_MASK		U(0xf)
754 #define AMCFGR_N_SHIFT		U(0)
755 #define AMCFGR_N_MASK		U(0xff)
756 
757 /* AMCGCR definitions */
758 #define AMCGCR_CG0NC_SHIFT	U(0)
759 #define AMCGCR_CG0NC_MASK	U(0xff)
760 #define AMCGCR_CG1NC_SHIFT	U(8)
761 #define AMCGCR_CG1NC_MASK	U(0xff)
762 
763 /*******************************************************************************
764  * Definitions for DynamicIQ Shared Unit registers
765  ******************************************************************************/
766 #define CLUSTERPWRDN	p15, 0, c15, c3, 6
767 
768 /* CLUSTERPWRDN register definitions */
769 #define DSU_CLUSTER_PWR_OFF	0
770 #define DSU_CLUSTER_PWR_ON	1
771 #define DSU_CLUSTER_PWR_MASK	U(1)
772 
773 #endif /* ARCH_H */
774