1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef HIKEY_DEF_H 8 #define HIKEY_DEF_H 9 10 /* Always assume DDR is 1GB size. */ 11 #define DDR_BASE 0x0 12 #define DDR_SIZE 0x40000000 13 14 #define DEVICE_BASE 0xF4000000 15 #define DEVICE_SIZE 0x05800000 16 17 /* Memory location options for TSP */ 18 #define HIKEY_SRAM_ID 0 19 #define HIKEY_DRAM_ID 1 20 21 /* 22 * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several 23 * regions 24 * - Secure DDR (default is the top 16MB) used by OP-TEE 25 * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) 26 * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature 27 * - Non-secure DDR (8MB) reserved for OP-TEE's future use 28 */ 29 #define DDR_SEC_SIZE 0x01000000 30 #define DDR_SEC_BASE (DDR_BASE + DDR_SIZE - DDR_SEC_SIZE) /* 0x3F000000 */ 31 32 #define DDR_SDP_SIZE 0x00400000 33 #define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \ 34 DDR_SDP_SIZE) 35 36 #define SRAM_BASE 0xFFF80000 37 #define SRAM_SIZE 0x00012000 38 39 /* 40 * PL011 related constants 41 */ 42 #define PL011_UART0_BASE 0xF8015000 43 #define PL011_UART2_BASE 0xF7112000 44 #define PL011_UART3_BASE 0xF7113000 45 #define PL011_BAUDRATE 115200 46 #define PL011_UART_CLK_IN_HZ 19200000 47 48 #define HIKEY_USB_DESC_BASE (DDR_BASE + 0x00800000) 49 #define HIKEY_USB_DESC_SIZE 0x00100000 50 #define HIKEY_USB_DATA_BASE (DDR_BASE + 0x10000000) 51 #define HIKEY_USB_DATA_SIZE 0x10000000 52 #define HIKEY_FB_BUFFER_BASE (HIKEY_USB_DATA_BASE) 53 #define HIKEY_FB_BUFFER_SIZE HIKEY_USB_DATA_SIZE 54 #define HIKEY_FB_DOWNLOAD_BASE (HIKEY_FB_BUFFER_BASE + \ 55 HIKEY_FB_BUFFER_SIZE) 56 #define HIKEY_FB_DOWNLOAD_SIZE HIKEY_USB_DATA_SIZE 57 58 #define HIKEY_USB_DESC_IN_BASE (DDR_BASE + 0x00800000) 59 #define HIKEY_USB_DESC_IN_SIZE 0x00040000 60 #define HIKEY_USB_DESC_EP0_OUT_BASE (HIKEY_USB_DESC_IN_BASE + \ 61 HIKEY_USB_DESC_IN_SIZE) 62 #define HIKEY_USB_DESC_EP0_OUT_SIZE 0x00040000 63 #define HIKEY_USB_DESC_EPX_OUT_BASE (HIKEY_USB_DESC_EP0_OUT_BASE + \ 64 HIKEY_USB_DESC_EP0_OUT_SIZE) 65 #define HIKEY_USB_DESC_EPX_OUT_SIZE 0x00080000 66 67 #define HIKEY_MMC_DESC_BASE (DDR_BASE + 0x03000000) 68 #define HIKEY_MMC_DESC_SIZE 0x00100000 69 70 /* 71 * HIKEY_MMC_DATA_BASE & HIKEY_MMC_DATA_SIZE are shared between fastboot 72 * and eMMC driver. Since it could avoid to memory copy. 73 * So this SRAM region is used twice. First, it's used in BL1 as temporary 74 * buffer in eMMC driver. Second, it's used by MCU in BL2. The SRAM region 75 * needs to be clear before used in BL2. 76 */ 77 #define HIKEY_MMC_DATA_BASE (DDR_BASE + 0x10000000) 78 #define HIKEY_MMC_DATA_SIZE 0x20000000 79 #define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000) 80 #define HIKEY_BL1_MMC_DESC_BASE (SRAM_BASE) 81 #define HIKEY_BL1_MMC_DESC_SIZE 0x00001000 82 #define HIKEY_BL1_MMC_DATA_BASE (HIKEY_BL1_MMC_DESC_BASE + \ 83 HIKEY_BL1_MMC_DESC_SIZE) 84 #define HIKEY_BL1_MMC_DATA_SIZE 0x0000B000 85 86 #define EMMC_BASE 0 87 #define HIKEY_EMMC_RPMB_BASE (EMMC_BASE + 0) 88 #define HIKEY_EMMC_RPMB_MAX_SIZE (128 << 10) 89 #define HIKEY_EMMC_USERDATA_BASE (EMMC_BASE + 0) 90 #define HIKEY_EMMC_USERDATA_MAX_SIZE (4 << 30) 91 92 /* 93 * GIC400 interrupt handling related constants 94 */ 95 #define IRQ_SEC_PHY_TIMER 29 96 #define IRQ_SEC_SGI_0 8 97 #define IRQ_SEC_SGI_1 9 98 #define IRQ_SEC_SGI_2 10 99 #define IRQ_SEC_SGI_3 11 100 #define IRQ_SEC_SGI_4 12 101 #define IRQ_SEC_SGI_5 13 102 #define IRQ_SEC_SGI_6 14 103 #define IRQ_SEC_SGI_7 15 104 #define IRQ_SEC_SGI_8 16 105 106 #endif /* HIKEY_DEF_H */ 107