1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_SRE_EL1 S3_0_C12_C12_5 83 #define ICC_SRE_EL2 S3_4_C12_C9_5 84 #define ICC_SRE_EL3 S3_6_C12_C12_5 85 #define ICC_CTLR_EL1 S3_0_C12_C12_4 86 #define ICC_CTLR_EL3 S3_6_C12_C12_4 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_RPR_EL1 S3_0_C12_C11_3 89 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 90 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 91 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 92 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 93 #define ICC_IAR0_EL1 S3_0_c12_c8_0 94 #define ICC_IAR1_EL1 S3_0_c12_c12_0 95 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 96 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 97 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 98 99 /******************************************************************************* 100 * Definitions for EL2 system registers for save/restore routine 101 ******************************************************************************/ 102 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C5_0 113 #define MPAMVPM1_EL2 S3_4_C10_C5_1 114 #define MPAMVPM2_EL2 S3_4_C10_C5_2 115 #define MPAMVPM3_EL2 S3_4_C10_C5_3 116 #define MPAMVPM4_EL2 S3_4_C10_C5_4 117 #define MPAMVPM5_EL2 S3_4_C10_C5_5 118 #define MPAMVPM6_EL2 S3_4_C10_C5_6 119 #define MPAMVPM7_EL2 S3_4_C10_C5_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define PMSCR_EL2 S3_4_C9_C9_0 123 #define TFSR_EL2 S3_4_C5_C6_0 124 125 /******************************************************************************* 126 * Generic timer memory mapped registers & offsets 127 ******************************************************************************/ 128 #define CNTCR_OFF U(0x000) 129 #define CNTCV_OFF U(0x008) 130 #define CNTFID_OFF U(0x020) 131 132 #define CNTCR_EN (U(1) << 0) 133 #define CNTCR_HDBG (U(1) << 1) 134 #define CNTCR_FCREQ(x) ((x) << 8) 135 136 /******************************************************************************* 137 * System register bit definitions 138 ******************************************************************************/ 139 /* CLIDR definitions */ 140 #define LOUIS_SHIFT U(21) 141 #define LOC_SHIFT U(24) 142 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 143 #define CLIDR_FIELD_WIDTH U(3) 144 145 /* CSSELR definitions */ 146 #define LEVEL_SHIFT U(1) 147 148 /* Data cache set/way op type defines */ 149 #define DCISW U(0x0) 150 #define DCCISW U(0x1) 151 #if ERRATA_A53_827319 152 #define DCCSW DCCISW 153 #else 154 #define DCCSW U(0x2) 155 #endif 156 157 /* ID_AA64PFR0_EL1 definitions */ 158 #define ID_AA64PFR0_EL0_SHIFT U(0) 159 #define ID_AA64PFR0_EL1_SHIFT U(4) 160 #define ID_AA64PFR0_EL2_SHIFT U(8) 161 #define ID_AA64PFR0_EL3_SHIFT U(12) 162 #define ID_AA64PFR0_AMU_SHIFT U(44) 163 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 164 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 165 #define ID_AA64PFR0_AMU_V1 U(0x1) 166 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 167 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 168 #define ID_AA64PFR0_GIC_SHIFT U(24) 169 #define ID_AA64PFR0_GIC_WIDTH U(4) 170 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 171 #define ID_AA64PFR0_SVE_SHIFT U(32) 172 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 173 #define ID_AA64PFR0_SVE_LENGTH U(4) 174 #define ID_AA64PFR0_SEL2_SHIFT U(36) 175 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 176 #define ID_AA64PFR0_MPAM_SHIFT U(40) 177 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 178 #define ID_AA64PFR0_DIT_SHIFT U(48) 179 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 180 #define ID_AA64PFR0_DIT_LENGTH U(4) 181 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 182 #define ID_AA64PFR0_CSV2_SHIFT U(56) 183 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 184 #define ID_AA64PFR0_CSV2_LENGTH U(4) 185 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 186 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 187 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 188 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 189 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 190 191 /* Exception level handling */ 192 #define EL_IMPL_NONE ULL(0) 193 #define EL_IMPL_A64ONLY ULL(1) 194 #define EL_IMPL_A64_A32 ULL(2) 195 196 /* ID_AA64DFR0_EL1.TraceVer definitions */ 197 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 198 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 199 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 200 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 201 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 202 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 203 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 204 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 205 206 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 207 #define ID_AA64DFR0_PMS_SHIFT U(32) 208 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 209 210 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 211 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 212 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 213 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 214 215 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 216 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 217 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 218 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 219 220 /* ID_AA64ISAR0_EL1 definitions */ 221 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 222 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 223 224 /* ID_AA64ISAR1_EL1 definitions */ 225 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 226 #define ID_AA64ISAR1_GPI_SHIFT U(28) 227 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 228 #define ID_AA64ISAR1_GPA_SHIFT U(24) 229 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 230 #define ID_AA64ISAR1_API_SHIFT U(8) 231 #define ID_AA64ISAR1_API_MASK ULL(0xf) 232 #define ID_AA64ISAR1_APA_SHIFT U(4) 233 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 234 235 /* ID_AA64MMFR0_EL1 definitions */ 236 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 237 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 238 239 #define PARANGE_0000 U(32) 240 #define PARANGE_0001 U(36) 241 #define PARANGE_0010 U(40) 242 #define PARANGE_0011 U(42) 243 #define PARANGE_0100 U(44) 244 #define PARANGE_0101 U(48) 245 #define PARANGE_0110 U(52) 246 247 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 248 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 249 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 250 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 251 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 252 253 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 254 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 255 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 256 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 257 258 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 259 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 260 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 261 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 262 263 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 264 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 265 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 266 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 267 268 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 269 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 270 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 271 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 272 273 /* ID_AA64MMFR1_EL1 definitions */ 274 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 275 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 276 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 277 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 278 279 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 280 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 281 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 282 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 283 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 284 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 285 286 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 287 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 288 289 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 290 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 291 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 292 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 293 294 /* ID_AA64MMFR2_EL1 definitions */ 295 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 296 297 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 298 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 299 300 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 301 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 302 303 /* ID_AA64PFR1_EL1 definitions */ 304 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 305 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 306 307 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 308 309 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 310 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 311 312 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 313 314 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 315 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 316 317 /* Memory Tagging Extension is not implemented */ 318 #define MTE_UNIMPLEMENTED U(0) 319 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 320 #define MTE_IMPLEMENTED_EL0 U(1) 321 /* FEAT_MTE2: Full MTE is implemented */ 322 #define MTE_IMPLEMENTED_ELX U(2) 323 /* 324 * FEAT_MTE3: MTE is implemented with support for 325 * asymmetric Tag Check Fault handling 326 */ 327 #define MTE_IMPLEMENTED_ASY U(3) 328 329 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 330 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 331 332 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 333 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 334 335 /* ID_PFR1_EL1 definitions */ 336 #define ID_PFR1_VIRTEXT_SHIFT U(12) 337 #define ID_PFR1_VIRTEXT_MASK U(0xf) 338 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 339 & ID_PFR1_VIRTEXT_MASK) 340 341 /* SCTLR definitions */ 342 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 343 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 344 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 345 346 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 347 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 348 349 #define SCTLR_AARCH32_EL1_RES1 \ 350 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 351 (U(1) << 4) | (U(1) << 3)) 352 353 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 354 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 355 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 356 357 #define SCTLR_M_BIT (ULL(1) << 0) 358 #define SCTLR_A_BIT (ULL(1) << 1) 359 #define SCTLR_C_BIT (ULL(1) << 2) 360 #define SCTLR_SA_BIT (ULL(1) << 3) 361 #define SCTLR_SA0_BIT (ULL(1) << 4) 362 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 363 #define SCTLR_nAA_BIT (ULL(1) << 6) 364 #define SCTLR_ITD_BIT (ULL(1) << 7) 365 #define SCTLR_SED_BIT (ULL(1) << 8) 366 #define SCTLR_UMA_BIT (ULL(1) << 9) 367 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 368 #define SCTLR_EOS_BIT (ULL(1) << 11) 369 #define SCTLR_I_BIT (ULL(1) << 12) 370 #define SCTLR_EnDB_BIT (ULL(1) << 13) 371 #define SCTLR_DZE_BIT (ULL(1) << 14) 372 #define SCTLR_UCT_BIT (ULL(1) << 15) 373 #define SCTLR_NTWI_BIT (ULL(1) << 16) 374 #define SCTLR_NTWE_BIT (ULL(1) << 18) 375 #define SCTLR_WXN_BIT (ULL(1) << 19) 376 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 377 #define SCTLR_IESB_BIT (ULL(1) << 21) 378 #define SCTLR_EIS_BIT (ULL(1) << 22) 379 #define SCTLR_SPAN_BIT (ULL(1) << 23) 380 #define SCTLR_E0E_BIT (ULL(1) << 24) 381 #define SCTLR_EE_BIT (ULL(1) << 25) 382 #define SCTLR_UCI_BIT (ULL(1) << 26) 383 #define SCTLR_EnDA_BIT (ULL(1) << 27) 384 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 385 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 386 #define SCTLR_EnIB_BIT (ULL(1) << 30) 387 #define SCTLR_EnIA_BIT (ULL(1) << 31) 388 #define SCTLR_BT0_BIT (ULL(1) << 35) 389 #define SCTLR_BT1_BIT (ULL(1) << 36) 390 #define SCTLR_BT_BIT (ULL(1) << 36) 391 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 392 #define SCTLR_TCF0_SHIFT U(38) 393 #define SCTLR_TCF0_MASK ULL(3) 394 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 395 396 /* Tag Check Faults in EL0 have no effect on the PE */ 397 #define SCTLR_TCF0_NO_EFFECT U(0) 398 /* Tag Check Faults in EL0 cause a synchronous exception */ 399 #define SCTLR_TCF0_SYNC U(1) 400 /* Tag Check Faults in EL0 are asynchronously accumulated */ 401 #define SCTLR_TCF0_ASYNC U(2) 402 /* 403 * Tag Check Faults in EL0 cause a synchronous exception on reads, 404 * and are asynchronously accumulated on writes 405 */ 406 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 407 408 #define SCTLR_TCF_SHIFT U(40) 409 #define SCTLR_TCF_MASK ULL(3) 410 411 /* Tag Check Faults in EL1 have no effect on the PE */ 412 #define SCTLR_TCF_NO_EFFECT U(0) 413 /* Tag Check Faults in EL1 cause a synchronous exception */ 414 #define SCTLR_TCF_SYNC U(1) 415 /* Tag Check Faults in EL1 are asynchronously accumulated */ 416 #define SCTLR_TCF_ASYNC U(2) 417 /* 418 * Tag Check Faults in EL1 cause a synchronous exception on reads, 419 * and are asynchronously accumulated on writes 420 */ 421 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 422 423 #define SCTLR_ATA0_BIT (ULL(1) << 42) 424 #define SCTLR_ATA_BIT (ULL(1) << 43) 425 #define SCTLR_DSSBS_SHIFT U(44) 426 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 427 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 428 #define SCTLR_TWEDEL_SHIFT U(46) 429 #define SCTLR_TWEDEL_MASK ULL(0xf) 430 #define SCTLR_EnASR_BIT (ULL(1) << 54) 431 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 432 #define SCTLR_EnALS_BIT (ULL(1) << 56) 433 #define SCTLR_EPAN_BIT (ULL(1) << 57) 434 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 435 436 /* CPACR_EL1 definitions */ 437 #define CPACR_EL1_FPEN(x) ((x) << 20) 438 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 439 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 440 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 441 442 /* SCR definitions */ 443 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 444 #define SCR_NSE_SHIFT U(62) 445 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 446 #define SCR_GPF_BIT (UL(1) << 48) 447 #define SCR_TWEDEL_SHIFT U(30) 448 #define SCR_TWEDEL_MASK ULL(0xf) 449 #define SCR_HXEn_BIT (UL(1) << 38) 450 #define SCR_ENTP2_SHIFT U(41) 451 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 452 #define SCR_AMVOFFEN_BIT (UL(1) << 35) 453 #define SCR_TWEDEn_BIT (UL(1) << 29) 454 #define SCR_ECVEN_BIT (UL(1) << 28) 455 #define SCR_FGTEN_BIT (UL(1) << 27) 456 #define SCR_ATA_BIT (UL(1) << 26) 457 #define SCR_EnSCXT_BIT (UL(1) << 25) 458 #define SCR_FIEN_BIT (UL(1) << 21) 459 #define SCR_EEL2_BIT (UL(1) << 18) 460 #define SCR_API_BIT (UL(1) << 17) 461 #define SCR_APK_BIT (UL(1) << 16) 462 #define SCR_TERR_BIT (UL(1) << 15) 463 #define SCR_TWE_BIT (UL(1) << 13) 464 #define SCR_TWI_BIT (UL(1) << 12) 465 #define SCR_ST_BIT (UL(1) << 11) 466 #define SCR_RW_BIT (UL(1) << 10) 467 #define SCR_SIF_BIT (UL(1) << 9) 468 #define SCR_HCE_BIT (UL(1) << 8) 469 #define SCR_SMD_BIT (UL(1) << 7) 470 #define SCR_EA_BIT (UL(1) << 3) 471 #define SCR_FIQ_BIT (UL(1) << 2) 472 #define SCR_IRQ_BIT (UL(1) << 1) 473 #define SCR_NS_BIT (UL(1) << 0) 474 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 475 #define SCR_RESET_VAL SCR_RES1_BITS 476 477 /* MDCR_EL3 definitions */ 478 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 479 #define MDCR_MPMX_BIT (ULL(1) << 35) 480 #define MDCR_MCCD_BIT (ULL(1) << 34) 481 #define MDCR_NSTB(x) ((x) << 24) 482 #define MDCR_NSTB_EL1 ULL(0x3) 483 #define MDCR_NSTBE (ULL(1) << 26) 484 #define MDCR_MTPME_BIT (ULL(1) << 28) 485 #define MDCR_TDCC_BIT (ULL(1) << 27) 486 #define MDCR_SCCD_BIT (ULL(1) << 23) 487 #define MDCR_EPMAD_BIT (ULL(1) << 21) 488 #define MDCR_EDAD_BIT (ULL(1) << 20) 489 #define MDCR_TTRF_BIT (ULL(1) << 19) 490 #define MDCR_STE_BIT (ULL(1) << 18) 491 #define MDCR_SPME_BIT (ULL(1) << 17) 492 #define MDCR_SDD_BIT (ULL(1) << 16) 493 #define MDCR_SPD32(x) ((x) << 14) 494 #define MDCR_SPD32_LEGACY ULL(0x0) 495 #define MDCR_SPD32_DISABLE ULL(0x2) 496 #define MDCR_SPD32_ENABLE ULL(0x3) 497 #define MDCR_NSPB(x) ((x) << 12) 498 #define MDCR_NSPB_EL1 ULL(0x3) 499 #define MDCR_TDOSA_BIT (ULL(1) << 10) 500 #define MDCR_TDA_BIT (ULL(1) << 9) 501 #define MDCR_TPM_BIT (ULL(1) << 6) 502 #define MDCR_EL3_RESET_VAL ULL(0x0) 503 504 /* MDCR_EL2 definitions */ 505 #define MDCR_EL2_MTPME (U(1) << 28) 506 #define MDCR_EL2_HLP (U(1) << 26) 507 #define MDCR_EL2_E2TB(x) ((x) << 24) 508 #define MDCR_EL2_E2TB_EL1 U(0x3) 509 #define MDCR_EL2_HCCD (U(1) << 23) 510 #define MDCR_EL2_TTRF (U(1) << 19) 511 #define MDCR_EL2_HPMD (U(1) << 17) 512 #define MDCR_EL2_TPMS (U(1) << 14) 513 #define MDCR_EL2_E2PB(x) ((x) << 12) 514 #define MDCR_EL2_E2PB_EL1 U(0x3) 515 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 516 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 517 #define MDCR_EL2_TDA_BIT (U(1) << 9) 518 #define MDCR_EL2_TDE_BIT (U(1) << 8) 519 #define MDCR_EL2_HPME_BIT (U(1) << 7) 520 #define MDCR_EL2_TPM_BIT (U(1) << 6) 521 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 522 #define MDCR_EL2_RESET_VAL U(0x0) 523 524 /* HSTR_EL2 definitions */ 525 #define HSTR_EL2_RESET_VAL U(0x0) 526 #define HSTR_EL2_T_MASK U(0xff) 527 528 /* CNTHP_CTL_EL2 definitions */ 529 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 530 #define CNTHP_CTL_RESET_VAL U(0x0) 531 532 /* VTTBR_EL2 definitions */ 533 #define VTTBR_RESET_VAL ULL(0x0) 534 #define VTTBR_VMID_MASK ULL(0xff) 535 #define VTTBR_VMID_SHIFT U(48) 536 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 537 #define VTTBR_BADDR_SHIFT U(0) 538 539 /* HCR definitions */ 540 #define HCR_RESET_VAL ULL(0x0) 541 #define HCR_AMVOFFEN_SHIFT U(51) 542 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 543 #define HCR_TEA_BIT (ULL(1) << 47) 544 #define HCR_API_BIT (ULL(1) << 41) 545 #define HCR_APK_BIT (ULL(1) << 40) 546 #define HCR_E2H_BIT (ULL(1) << 34) 547 #define HCR_HCD_BIT (ULL(1) << 29) 548 #define HCR_TGE_BIT (ULL(1) << 27) 549 #define HCR_RW_SHIFT U(31) 550 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 551 #define HCR_TWE_BIT (ULL(1) << 14) 552 #define HCR_TWI_BIT (ULL(1) << 13) 553 #define HCR_AMO_BIT (ULL(1) << 5) 554 #define HCR_IMO_BIT (ULL(1) << 4) 555 #define HCR_FMO_BIT (ULL(1) << 3) 556 557 /* ISR definitions */ 558 #define ISR_A_SHIFT U(8) 559 #define ISR_I_SHIFT U(7) 560 #define ISR_F_SHIFT U(6) 561 562 /* CNTHCTL_EL2 definitions */ 563 #define CNTHCTL_RESET_VAL U(0x0) 564 #define EVNTEN_BIT (U(1) << 2) 565 #define EL1PCEN_BIT (U(1) << 1) 566 #define EL1PCTEN_BIT (U(1) << 0) 567 568 /* CNTKCTL_EL1 definitions */ 569 #define EL0PTEN_BIT (U(1) << 9) 570 #define EL0VTEN_BIT (U(1) << 8) 571 #define EL0PCTEN_BIT (U(1) << 0) 572 #define EL0VCTEN_BIT (U(1) << 1) 573 #define EVNTEN_BIT (U(1) << 2) 574 #define EVNTDIR_BIT (U(1) << 3) 575 #define EVNTI_SHIFT U(4) 576 #define EVNTI_MASK U(0xf) 577 578 /* CPTR_EL3 definitions */ 579 #define TCPAC_BIT (U(1) << 31) 580 #define TAM_SHIFT U(30) 581 #define TAM_BIT (U(1) << TAM_SHIFT) 582 #define TTA_BIT (U(1) << 20) 583 #define ESM_BIT (U(1) << 12) 584 #define TFP_BIT (U(1) << 10) 585 #define CPTR_EZ_BIT (U(1) << 8) 586 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 587 ~(CPTR_EZ_BIT | ESM_BIT)) 588 589 /* CPTR_EL2 definitions */ 590 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 591 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 592 #define CPTR_EL2_TAM_SHIFT U(30) 593 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 594 #define CPTR_EL2_SMEN_MASK ULL(0x3) 595 #define CPTR_EL2_SMEN_SHIFT U(24) 596 #define CPTR_EL2_TTA_BIT (U(1) << 20) 597 #define CPTR_EL2_TSM_BIT (U(1) << 12) 598 #define CPTR_EL2_TFP_BIT (U(1) << 10) 599 #define CPTR_EL2_TZ_BIT (U(1) << 8) 600 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 601 602 /* VTCR_EL2 definitions */ 603 #define VTCR_RESET_VAL U(0x0) 604 #define VTCR_EL2_MSA (U(1) << 31) 605 606 /* CPSR/SPSR definitions */ 607 #define DAIF_FIQ_BIT (U(1) << 0) 608 #define DAIF_IRQ_BIT (U(1) << 1) 609 #define DAIF_ABT_BIT (U(1) << 2) 610 #define DAIF_DBG_BIT (U(1) << 3) 611 #define SPSR_DAIF_SHIFT U(6) 612 #define SPSR_DAIF_MASK U(0xf) 613 614 #define SPSR_AIF_SHIFT U(6) 615 #define SPSR_AIF_MASK U(0x7) 616 617 #define SPSR_E_SHIFT U(9) 618 #define SPSR_E_MASK U(0x1) 619 #define SPSR_E_LITTLE U(0x0) 620 #define SPSR_E_BIG U(0x1) 621 622 #define SPSR_T_SHIFT U(5) 623 #define SPSR_T_MASK U(0x1) 624 #define SPSR_T_ARM U(0x0) 625 #define SPSR_T_THUMB U(0x1) 626 627 #define SPSR_M_SHIFT U(4) 628 #define SPSR_M_MASK U(0x1) 629 #define SPSR_M_AARCH64 U(0x0) 630 #define SPSR_M_AARCH32 U(0x1) 631 #define SPSR_M_EL2H U(0x9) 632 633 #define SPSR_EL_SHIFT U(2) 634 #define SPSR_EL_WIDTH U(2) 635 636 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 637 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 638 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 639 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 640 641 #define SPSR_PAN_BIT BIT_64(22) 642 643 #define SPSR_DIT_BIT BIT(24) 644 645 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 646 647 #define DISABLE_ALL_EXCEPTIONS \ 648 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 649 650 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 651 652 /* 653 * RMR_EL3 definitions 654 */ 655 #define RMR_EL3_RR_BIT (U(1) << 1) 656 #define RMR_EL3_AA64_BIT (U(1) << 0) 657 658 /* 659 * HI-VECTOR address for AArch32 state 660 */ 661 #define HI_VECTOR_BASE U(0xFFFF0000) 662 663 /* 664 * TCR defintions 665 */ 666 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 667 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 668 #define TCR_EL1_IPS_SHIFT U(32) 669 #define TCR_EL2_PS_SHIFT U(16) 670 #define TCR_EL3_PS_SHIFT U(16) 671 672 #define TCR_TxSZ_MIN ULL(16) 673 #define TCR_TxSZ_MAX ULL(39) 674 #define TCR_TxSZ_MAX_TTST ULL(48) 675 676 #define TCR_T0SZ_SHIFT U(0) 677 #define TCR_T1SZ_SHIFT U(16) 678 679 /* (internal) physical address size bits in EL3/EL1 */ 680 #define TCR_PS_BITS_4GB ULL(0x0) 681 #define TCR_PS_BITS_64GB ULL(0x1) 682 #define TCR_PS_BITS_1TB ULL(0x2) 683 #define TCR_PS_BITS_4TB ULL(0x3) 684 #define TCR_PS_BITS_16TB ULL(0x4) 685 #define TCR_PS_BITS_256TB ULL(0x5) 686 687 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 688 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 689 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 690 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 691 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 692 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 693 694 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 695 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 696 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 697 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 698 699 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 700 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 701 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 702 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 703 704 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 705 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 706 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 707 708 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 709 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 710 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 711 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 712 713 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 714 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 715 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 716 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 717 718 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 719 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 720 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 721 722 #define TCR_TG0_SHIFT U(14) 723 #define TCR_TG0_MASK ULL(3) 724 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 725 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 726 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 727 728 #define TCR_TG1_SHIFT U(30) 729 #define TCR_TG1_MASK ULL(3) 730 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 731 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 732 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 733 734 #define TCR_EPD0_BIT (ULL(1) << 7) 735 #define TCR_EPD1_BIT (ULL(1) << 23) 736 737 #define MODE_SP_SHIFT U(0x0) 738 #define MODE_SP_MASK U(0x1) 739 #define MODE_SP_EL0 U(0x0) 740 #define MODE_SP_ELX U(0x1) 741 742 #define MODE_RW_SHIFT U(0x4) 743 #define MODE_RW_MASK U(0x1) 744 #define MODE_RW_64 U(0x0) 745 #define MODE_RW_32 U(0x1) 746 747 #define MODE_EL_SHIFT U(0x2) 748 #define MODE_EL_MASK U(0x3) 749 #define MODE_EL_WIDTH U(0x2) 750 #define MODE_EL3 U(0x3) 751 #define MODE_EL2 U(0x2) 752 #define MODE_EL1 U(0x1) 753 #define MODE_EL0 U(0x0) 754 755 #define MODE32_SHIFT U(0) 756 #define MODE32_MASK U(0xf) 757 #define MODE32_usr U(0x0) 758 #define MODE32_fiq U(0x1) 759 #define MODE32_irq U(0x2) 760 #define MODE32_svc U(0x3) 761 #define MODE32_mon U(0x6) 762 #define MODE32_abt U(0x7) 763 #define MODE32_hyp U(0xa) 764 #define MODE32_und U(0xb) 765 #define MODE32_sys U(0xf) 766 767 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 768 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 769 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 770 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 771 772 #define SPSR_64(el, sp, daif) \ 773 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 774 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 775 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 776 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 777 (~(SPSR_SSBS_BIT_AARCH64))) 778 779 #define SPSR_MODE32(mode, isa, endian, aif) \ 780 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 781 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 782 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 783 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 784 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 785 (~(SPSR_SSBS_BIT_AARCH32))) 786 787 /* 788 * TTBR Definitions 789 */ 790 #define TTBR_CNP_BIT ULL(0x1) 791 792 /* 793 * CTR_EL0 definitions 794 */ 795 #define CTR_CWG_SHIFT U(24) 796 #define CTR_CWG_MASK U(0xf) 797 #define CTR_ERG_SHIFT U(20) 798 #define CTR_ERG_MASK U(0xf) 799 #define CTR_DMINLINE_SHIFT U(16) 800 #define CTR_DMINLINE_MASK U(0xf) 801 #define CTR_L1IP_SHIFT U(14) 802 #define CTR_L1IP_MASK U(0x3) 803 #define CTR_IMINLINE_SHIFT U(0) 804 #define CTR_IMINLINE_MASK U(0xf) 805 806 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 807 808 /* Physical timer control register bit fields shifts and masks */ 809 #define CNTP_CTL_ENABLE_SHIFT U(0) 810 #define CNTP_CTL_IMASK_SHIFT U(1) 811 #define CNTP_CTL_ISTATUS_SHIFT U(2) 812 813 #define CNTP_CTL_ENABLE_MASK U(1) 814 #define CNTP_CTL_IMASK_MASK U(1) 815 #define CNTP_CTL_ISTATUS_MASK U(1) 816 817 /* Physical timer control macros */ 818 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 819 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 820 821 /* Exception Syndrome register bits and bobs */ 822 #define ESR_EC_SHIFT U(26) 823 #define ESR_EC_MASK U(0x3f) 824 #define ESR_EC_LENGTH U(6) 825 #define ESR_ISS_SHIFT U(0) 826 #define ESR_ISS_LENGTH U(25) 827 #define EC_UNKNOWN U(0x0) 828 #define EC_WFE_WFI U(0x1) 829 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 830 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 831 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 832 #define EC_AARCH32_CP14_LDC_STC U(0x6) 833 #define EC_FP_SIMD U(0x7) 834 #define EC_AARCH32_CP10_MRC U(0x8) 835 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 836 #define EC_ILLEGAL U(0xe) 837 #define EC_AARCH32_SVC U(0x11) 838 #define EC_AARCH32_HVC U(0x12) 839 #define EC_AARCH32_SMC U(0x13) 840 #define EC_AARCH64_SVC U(0x15) 841 #define EC_AARCH64_HVC U(0x16) 842 #define EC_AARCH64_SMC U(0x17) 843 #define EC_AARCH64_SYS U(0x18) 844 #define EC_IABORT_LOWER_EL U(0x20) 845 #define EC_IABORT_CUR_EL U(0x21) 846 #define EC_PC_ALIGN U(0x22) 847 #define EC_DABORT_LOWER_EL U(0x24) 848 #define EC_DABORT_CUR_EL U(0x25) 849 #define EC_SP_ALIGN U(0x26) 850 #define EC_AARCH32_FP U(0x28) 851 #define EC_AARCH64_FP U(0x2c) 852 #define EC_SERROR U(0x2f) 853 #define EC_BRK U(0x3c) 854 855 /* 856 * External Abort bit in Instruction and Data Aborts synchronous exception 857 * syndromes. 858 */ 859 #define ESR_ISS_EABORT_EA_BIT U(9) 860 861 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 862 863 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 864 #define RMR_RESET_REQUEST_SHIFT U(0x1) 865 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 866 867 /******************************************************************************* 868 * Definitions of register offsets, fields and macros for CPU system 869 * instructions. 870 ******************************************************************************/ 871 872 #define TLBI_ADDR_SHIFT U(12) 873 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 874 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 875 876 /******************************************************************************* 877 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 878 * system level implementation of the Generic Timer. 879 ******************************************************************************/ 880 #define CNTCTLBASE_CNTFRQ U(0x0) 881 #define CNTNSAR U(0x4) 882 #define CNTNSAR_NS_SHIFT(x) (x) 883 884 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 885 #define CNTACR_RPCT_SHIFT U(0x0) 886 #define CNTACR_RVCT_SHIFT U(0x1) 887 #define CNTACR_RFRQ_SHIFT U(0x2) 888 #define CNTACR_RVOFF_SHIFT U(0x3) 889 #define CNTACR_RWVT_SHIFT U(0x4) 890 #define CNTACR_RWPT_SHIFT U(0x5) 891 892 /******************************************************************************* 893 * Definitions of register offsets and fields in the CNTBaseN Frame of the 894 * system level implementation of the Generic Timer. 895 ******************************************************************************/ 896 /* Physical Count register. */ 897 #define CNTPCT_LO U(0x0) 898 /* Counter Frequency register. */ 899 #define CNTBASEN_CNTFRQ U(0x10) 900 /* Physical Timer CompareValue register. */ 901 #define CNTP_CVAL_LO U(0x20) 902 /* Physical Timer Control register. */ 903 #define CNTP_CTL U(0x2c) 904 905 /* PMCR_EL0 definitions */ 906 #define PMCR_EL0_RESET_VAL U(0x0) 907 #define PMCR_EL0_N_SHIFT U(11) 908 #define PMCR_EL0_N_MASK U(0x1f) 909 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 910 #define PMCR_EL0_LP_BIT (U(1) << 7) 911 #define PMCR_EL0_LC_BIT (U(1) << 6) 912 #define PMCR_EL0_DP_BIT (U(1) << 5) 913 #define PMCR_EL0_X_BIT (U(1) << 4) 914 #define PMCR_EL0_D_BIT (U(1) << 3) 915 #define PMCR_EL0_C_BIT (U(1) << 2) 916 #define PMCR_EL0_P_BIT (U(1) << 1) 917 #define PMCR_EL0_E_BIT (U(1) << 0) 918 919 /******************************************************************************* 920 * Definitions for system register interface to SVE 921 ******************************************************************************/ 922 #define ZCR_EL3 S3_6_C1_C2_0 923 #define ZCR_EL2 S3_4_C1_C2_0 924 925 /* ZCR_EL3 definitions */ 926 #define ZCR_EL3_LEN_MASK U(0xf) 927 928 /* ZCR_EL2 definitions */ 929 #define ZCR_EL2_LEN_MASK U(0xf) 930 931 /******************************************************************************* 932 * Definitions for system register interface to SME as needed in EL3 933 ******************************************************************************/ 934 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 935 #define SMCR_EL3 S3_6_C1_C2_6 936 937 /* ID_AA64SMFR0_EL1 definitions */ 938 #define ID_AA64SMFR0_EL1_FA64_BIT (UL(1) << 63) 939 940 /* SMCR_ELx definitions */ 941 #define SMCR_ELX_LEN_SHIFT U(0) 942 #define SMCR_ELX_LEN_MASK U(0x1ff) 943 #define SMCR_ELX_FA64_BIT (U(1) << 31) 944 945 /******************************************************************************* 946 * Definitions of MAIR encodings for device and normal memory 947 ******************************************************************************/ 948 /* 949 * MAIR encodings for device memory attributes. 950 */ 951 #define MAIR_DEV_nGnRnE ULL(0x0) 952 #define MAIR_DEV_nGnRE ULL(0x4) 953 #define MAIR_DEV_nGRE ULL(0x8) 954 #define MAIR_DEV_GRE ULL(0xc) 955 956 /* 957 * MAIR encodings for normal memory attributes. 958 * 959 * Cache Policy 960 * WT: Write Through 961 * WB: Write Back 962 * NC: Non-Cacheable 963 * 964 * Transient Hint 965 * NTR: Non-Transient 966 * TR: Transient 967 * 968 * Allocation Policy 969 * RA: Read Allocate 970 * WA: Write Allocate 971 * RWA: Read and Write Allocate 972 * NA: No Allocation 973 */ 974 #define MAIR_NORM_WT_TR_WA ULL(0x1) 975 #define MAIR_NORM_WT_TR_RA ULL(0x2) 976 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 977 #define MAIR_NORM_NC ULL(0x4) 978 #define MAIR_NORM_WB_TR_WA ULL(0x5) 979 #define MAIR_NORM_WB_TR_RA ULL(0x6) 980 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 981 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 982 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 983 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 984 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 985 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 986 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 987 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 988 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 989 990 #define MAIR_NORM_OUTER_SHIFT U(4) 991 992 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 993 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 994 995 /* PAR_EL1 fields */ 996 #define PAR_F_SHIFT U(0) 997 #define PAR_F_MASK ULL(0x1) 998 #define PAR_ADDR_SHIFT U(12) 999 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1000 1001 /******************************************************************************* 1002 * Definitions for system register interface to SPE 1003 ******************************************************************************/ 1004 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1005 1006 /******************************************************************************* 1007 * Definitions for system register interface to MPAM 1008 ******************************************************************************/ 1009 #define MPAMIDR_EL1 S3_0_C10_C4_4 1010 #define MPAM2_EL2 S3_4_C10_C5_0 1011 #define MPAMHCR_EL2 S3_4_C10_C4_0 1012 #define MPAM3_EL3 S3_6_C10_C5_0 1013 1014 /******************************************************************************* 1015 * Definitions for system register interface to AMU for FEAT_AMUv1 1016 ******************************************************************************/ 1017 #define AMCR_EL0 S3_3_C13_C2_0 1018 #define AMCFGR_EL0 S3_3_C13_C2_1 1019 #define AMCGCR_EL0 S3_3_C13_C2_2 1020 #define AMUSERENR_EL0 S3_3_C13_C2_3 1021 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1022 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1023 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1024 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1025 1026 /* Activity Monitor Group 0 Event Counter Registers */ 1027 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1028 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1029 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1030 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1031 1032 /* Activity Monitor Group 0 Event Type Registers */ 1033 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1034 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1035 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1036 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1037 1038 /* Activity Monitor Group 1 Event Counter Registers */ 1039 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1040 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1041 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1042 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1043 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1044 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1045 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1046 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1047 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1048 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1049 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1050 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1051 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1052 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1053 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1054 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1055 1056 /* Activity Monitor Group 1 Event Type Registers */ 1057 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1058 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1059 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1060 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1061 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1062 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1063 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1064 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1065 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1066 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1067 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1068 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1069 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1070 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1071 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1072 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1073 1074 /* AMCNTENSET0_EL0 definitions */ 1075 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1076 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1077 1078 /* AMCNTENSET1_EL0 definitions */ 1079 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1080 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1081 1082 /* AMCNTENCLR0_EL0 definitions */ 1083 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1084 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1085 1086 /* AMCNTENCLR1_EL0 definitions */ 1087 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1088 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1089 1090 /* AMCFGR_EL0 definitions */ 1091 #define AMCFGR_EL0_NCG_SHIFT U(28) 1092 #define AMCFGR_EL0_NCG_MASK U(0xf) 1093 #define AMCFGR_EL0_N_SHIFT U(0) 1094 #define AMCFGR_EL0_N_MASK U(0xff) 1095 1096 /* AMCGCR_EL0 definitions */ 1097 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1098 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1099 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1100 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1101 1102 /* MPAM register definitions */ 1103 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1104 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1105 1106 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1107 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1108 1109 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1110 1111 /******************************************************************************* 1112 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1113 ******************************************************************************/ 1114 1115 /* Definition for register defining which virtual offsets are implemented. */ 1116 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1117 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1118 #define AMCG1IDR_CTR_SHIFT U(0) 1119 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1120 #define AMCG1IDR_VOFF_SHIFT U(16) 1121 1122 /* New bit added to AMCR_EL0 */ 1123 #define AMCR_CG1RZ_SHIFT U(17) 1124 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1125 1126 /* 1127 * Definitions for virtual offset registers for architected activity monitor 1128 * event counters. 1129 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1130 */ 1131 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1132 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1133 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1134 1135 /* 1136 * Definitions for virtual offset registers for auxiliary activity monitor event 1137 * counters. 1138 */ 1139 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1140 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1141 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1142 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1143 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1144 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1145 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1146 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1147 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1148 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1149 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1150 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1151 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1152 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1153 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1154 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1155 1156 /******************************************************************************* 1157 * Realm management extension register definitions 1158 ******************************************************************************/ 1159 #define GPCCR_EL3 S3_6_C2_C1_6 1160 #define GPTBR_EL3 S3_6_C2_C1_4 1161 1162 /******************************************************************************* 1163 * RAS system registers 1164 ******************************************************************************/ 1165 #define DISR_EL1 S3_0_C12_C1_1 1166 #define DISR_A_BIT U(31) 1167 1168 #define ERRIDR_EL1 S3_0_C5_C3_0 1169 #define ERRIDR_MASK U(0xffff) 1170 1171 #define ERRSELR_EL1 S3_0_C5_C3_1 1172 1173 /* System register access to Standard Error Record registers */ 1174 #define ERXFR_EL1 S3_0_C5_C4_0 1175 #define ERXCTLR_EL1 S3_0_C5_C4_1 1176 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1177 #define ERXADDR_EL1 S3_0_C5_C4_3 1178 #define ERXPFGF_EL1 S3_0_C5_C4_4 1179 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1180 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1181 #define ERXMISC0_EL1 S3_0_C5_C5_0 1182 #define ERXMISC1_EL1 S3_0_C5_C5_1 1183 1184 #define ERXCTLR_ED_BIT (U(1) << 0) 1185 #define ERXCTLR_UE_BIT (U(1) << 4) 1186 1187 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1188 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1189 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1190 1191 /******************************************************************************* 1192 * Armv8.3 Pointer Authentication Registers 1193 ******************************************************************************/ 1194 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1195 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1196 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1197 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1198 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1199 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1200 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1201 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1202 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1203 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1204 1205 /******************************************************************************* 1206 * Armv8.4 Data Independent Timing Registers 1207 ******************************************************************************/ 1208 #define DIT S3_3_C4_C2_5 1209 #define DIT_BIT BIT(24) 1210 1211 /******************************************************************************* 1212 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1213 ******************************************************************************/ 1214 #define SSBS S3_3_C4_C2_6 1215 1216 /******************************************************************************* 1217 * Armv8.5 - Memory Tagging Extension Registers 1218 ******************************************************************************/ 1219 #define TFSRE0_EL1 S3_0_C5_C6_1 1220 #define TFSR_EL1 S3_0_C5_C6_0 1221 #define RGSR_EL1 S3_0_C1_C0_5 1222 #define GCR_EL1 S3_0_C1_C0_6 1223 1224 /******************************************************************************* 1225 * FEAT_HCX - Extended Hypervisor Configuration Register 1226 ******************************************************************************/ 1227 #define HCRX_EL2 S3_4_C1_C2_2 1228 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1229 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1230 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1231 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1232 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1233 1234 /******************************************************************************* 1235 * Definitions for DynamicIQ Shared Unit registers 1236 ******************************************************************************/ 1237 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1238 1239 /* CLUSTERPWRDN_EL1 register definitions */ 1240 #define DSU_CLUSTER_PWR_OFF 0 1241 #define DSU_CLUSTER_PWR_ON 1 1242 #define DSU_CLUSTER_PWR_MASK U(1) 1243 1244 /******************************************************************************* 1245 * Definitions for CPU Power/Performance Management registers 1246 ******************************************************************************/ 1247 1248 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1249 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1250 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1251 1252 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1253 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1254 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1255 1256 #endif /* ARCH_H */ 1257