1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 5 */ 6 7 #ifndef _SYS_PROTO_H_ 8 #define _SYS_PROTO_H_ 9 10 #include <asm/io.h> 11 #include <asm/mach-imx/regs-common.h> 12 #include <asm/mach-imx/module_fuse.h> 13 #include <linux/bitops.h> 14 #include "../arch-imx/cpu.h" 15 16 struct bd_info; 17 18 #define soc_rev() (get_cpu_rev() & 0xFF) 19 #define is_soc_rev(rev) (soc_rev() == rev) 20 21 /* returns MXC_CPU_ value */ 22 #define cpu_type(rev) (((rev) >> 12) & 0x1ff) 23 #define soc_type(rev) (((rev) >> 12) & 0xf0) 24 /* both macros return/take MXC_CPU_ constants */ 25 #define get_cpu_type() (cpu_type(get_cpu_rev())) 26 #define get_soc_type() (soc_type(get_cpu_rev())) 27 #define is_cpu_type(cpu) (get_cpu_type() == cpu) 28 #define is_soc_type(soc) (get_soc_type() == soc) 29 30 #define is_mx6() (is_soc_type(MXC_SOC_MX6)) 31 #define is_mx7() (is_soc_type(MXC_SOC_MX7)) 32 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) 33 #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) 34 35 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 36 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 37 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL)) 38 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL)) 39 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX)) 40 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) 41 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) 42 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) 43 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ)) 44 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ)) 45 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) 46 47 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) 48 49 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL)) 50 #define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD)) 51 #define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL)) 52 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) 53 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ 54 is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ 55 is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL)) 56 #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML)) 57 #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD)) 58 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL)) 59 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) 60 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) 61 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \ 62 is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \ 63 is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL)) 64 #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND)) 65 #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS)) 66 #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL)) 67 #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) 68 #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) 69 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ 70 is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6)) 71 #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) 72 #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL)) 73 #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6)) 74 75 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) 76 77 #ifdef CONFIG_MX6 78 #define IMX6_SRC_GPR10_BMODE BIT(28) 79 #define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) 80 81 #define IMX6_BMODE_MASK GENMASK(7, 0) 82 #define IMX6_BMODE_SHIFT 4 83 #define IMX6_BMODE_EMI_MASK BIT(3) 84 #define IMX6_BMODE_EMI_SHIFT 3 85 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24) 86 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24 87 88 enum imx6_bmode_serial_rom { 89 IMX6_BMODE_ECSPI1, 90 IMX6_BMODE_ECSPI2, 91 IMX6_BMODE_ECSPI3, 92 IMX6_BMODE_ECSPI4, 93 IMX6_BMODE_ECSPI5, 94 IMX6_BMODE_I2C1, 95 IMX6_BMODE_I2C2, 96 IMX6_BMODE_I2C3, 97 }; 98 99 enum imx6_bmode_emi { 100 IMX6_BMODE_NOR, 101 IMX6_BMODE_ONENAND, 102 }; 103 104 enum imx6_bmode { 105 IMX6_BMODE_EMI, 106 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) 107 IMX6_BMODE_QSPI, 108 IMX6_BMODE_RESERVED, 109 #else 110 IMX6_BMODE_RESERVED, 111 IMX6_BMODE_SATA, 112 #endif 113 IMX6_BMODE_SERIAL_ROM, 114 IMX6_BMODE_SD, 115 IMX6_BMODE_ESD, 116 IMX6_BMODE_MMC, 117 IMX6_BMODE_EMMC, 118 IMX6_BMODE_NAND_MIN, 119 IMX6_BMODE_NAND_MAX = 0xf, 120 }; 121 122 u32 imx6_src_get_boot_mode(void); 123 void gpr_init(void); 124 125 #endif /* CONFIG_MX6 */ 126 127 #ifdef CONFIG_MX7 128 #define IMX7_SRC_GPR10_BMODE BIT(28) 129 #define IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) 130 #endif 131 132 /* address translation table */ 133 struct rproc_att { 134 u32 da; /* device address (From Cortex M4 view) */ 135 u32 sa; /* system bus address */ 136 u32 size; /* size of reg range */ 137 }; 138 139 #ifdef CONFIG_IMX8M 140 struct rom_api { 141 u16 ver; 142 u16 tag; 143 u32 reserved1; 144 u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor); 145 u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor); 146 }; 147 148 enum boot_dev_type_e { 149 BT_DEV_TYPE_SD = 1, 150 BT_DEV_TYPE_MMC = 2, 151 BT_DEV_TYPE_NAND = 3, 152 BT_DEV_TYPE_FLEXSPINOR = 4, 153 154 BT_DEV_TYPE_USB = 0xE, 155 BT_DEV_TYPE_MEM_DEV = 0xF, 156 157 BT_DEV_TYPE_INVALID = 0xFF 158 }; 159 160 #define QUERY_ROM_VER 1 161 #define QUERY_BT_DEV 2 162 #define QUERY_PAGE_SZ 3 163 #define QUERY_IVT_OFF 4 164 #define QUERY_BT_STAGE 5 165 #define QUERY_IMG_OFF 6 166 167 #define ROM_API_OKAY 0xF0 168 169 extern struct rom_api *g_rom_api; 170 #endif 171 172 u32 get_nr_cpus(void); 173 u32 get_cpu_rev(void); 174 u32 get_cpu_speed_grade_hz(void); 175 u32 get_cpu_temp_grade(int *minc, int *maxc); 176 const char *get_imx_type(u32 imxtype); 177 u32 imx_ddr_size(void); 178 void sdelay(unsigned long); 179 void set_chipselect_size(int const); 180 181 void init_aips(void); 182 void init_src(void); 183 void init_snvs(void); 184 void imx_wdog_disable_powerdown(void); 185 186 void board_mem_get_layout(u64 *phys_sdram_1_start, 187 u64 *phys_sdram_1_size, 188 u64 *phys_sdram_2_start, 189 u64 *phys_sdram_2_size); 190 191 int arch_auxiliary_core_check_up(u32 core_id); 192 193 int board_mmc_get_env_dev(int devno); 194 195 int nxp_board_rev(void); 196 char nxp_board_rev_string(void); 197 198 /* 199 * Initializes on-chip ethernet controllers. 200 * to override, implement board_eth_init() 201 */ 202 int fecmxc_initialize(struct bd_info *bis); 203 u32 get_ahb_clk(void); 204 u32 get_periph_clk(void); 205 206 void lcdif_power_down(void); 207 208 int mxs_reset_block(struct mxs_register_32 *reg); 209 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); 210 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); 211 212 unsigned long call_imx_sip(unsigned long id, unsigned long reg0, 213 unsigned long reg1, unsigned long reg2, 214 unsigned long reg3); 215 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, 216 unsigned long *reg1, unsigned long reg2, 217 unsigned long reg3); 218 219 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 220 #endif 221