1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2017-2018, Intel Corporation 4 */ 5 6 #ifndef __INTEL_SMC_H 7 #define __INTEL_SMC_H 8 9 #include <linux/arm-smccc.h> 10 #include <linux/bitops.h> 11 12 /* 13 * This file defines the Secure Monitor Call (SMC) message protocol used for 14 * service layer driver in normal world (EL1) to communicate with secure 15 * monitor software in Secure Monitor Exception Level 3 (EL3). 16 * 17 * This file is shared with secure firmware (FW) which is out of u-boot tree. 18 * 19 * An ARM SMC instruction takes a function identifier and up to 6 64-bit 20 * register values as arguments, and can return up to 4 64-bit register 21 * values. The operation of the secure monitor is determined by the parameter 22 * values passed in through registers. 23 24 * EL1 and EL3 communicates pointer as physical address rather than the 25 * virtual address. 26 */ 27 28 /* 29 * Functions specified by ARM SMC Calling convention: 30 * 31 * FAST call executes atomic operations, returns when the requested operation 32 * has completed. 33 * STD call starts a operation which can be preempted by a non-secure 34 * interrupt. The call can return before the requested operation has 35 * completed. 36 * 37 * a0..a7 is used as register names in the descriptions below, on arm32 38 * that translates to r0..r7 and on arm64 to w0..w7. 39 */ 40 41 #define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ 42 ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ 43 ARM_SMCCC_OWNER_SIP, (func_num)) 44 45 #define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ 46 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ 47 ARM_SMCCC_OWNER_SIP, (func_num)) 48 49 /* 50 * Return values in INTEL_SIP_SMC_* call 51 * 52 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION: 53 * Secure monitor software doesn't recognize the request. 54 * 55 * INTEL_SIP_SMC_STATUS_OK: 56 * SMC call completed successfully, 57 * In case of FPGA configuration write operation, it means secure monitor 58 * software can accept the next chunk of FPGA configuration data. 59 * 60 * INTEL_SIP_SMC_STATUS_BUSY: 61 * In case of FPGA configuration write operation, it means secure monitor 62 * software is still processing previous data & can't accept the next chunk 63 * of data. Service driver needs to issue 64 * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the 65 * completed block(s). 66 * 67 * INTEL_SIP_SMC_STATUS_ERROR: 68 * There is error during the SMC call process. 69 * 70 * INTEL_SIP_SMC_REG_ERROR: 71 * There is error during a read or write operation of the protected 72 * registers. 73 */ 74 #define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF 75 #define INTEL_SIP_SMC_STATUS_OK 0x0 76 #define INTEL_SIP_SMC_STATUS_BUSY 0x1 77 #define INTEL_SIP_SMC_STATUS_REJECTED 0x2 78 #define INTEL_SIP_SMC_STATUS_ERROR 0x4 79 #define INTEL_SIP_SMC_REG_ERROR 0x5 80 #define INTEL_SIP_SMC_RSU_ERROR 0x7 81 82 /* 83 * Request INTEL_SIP_SMC_FPGA_CONFIG_START 84 * 85 * Sync call used by service driver at EL1 to request the FPGA in EL3 to 86 * be prepare to receive a new configuration. 87 * 88 * Call register usage: 89 * a0: INTEL_SIP_SMC_FPGA_CONFIG_START. 90 * a1: flag for full or partial configuration 91 * 0 full reconfiguration. 92 * 1 partial reconfiguration. 93 * a2-7: not used. 94 * 95 * Return status: 96 * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR. 97 * a1-3: not used. 98 */ 99 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1 100 #define INTEL_SIP_SMC_FPGA_CONFIG_START \ 101 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START) 102 103 /* 104 * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE 105 * 106 * Async call used by service driver at EL1 to provide FPGA configuration data 107 * to secure world. 108 * 109 * Call register usage: 110 * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE. 111 * a1: 64bit physical address of the configuration data memory block 112 * a2: Size of configuration data block. 113 * a3-7: not used. 114 * 115 * Return status: 116 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY, 117 * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR. 118 * a1: 64bit physical address of 1st completed memory block if any completed 119 * block, otherwise zero value. 120 * a2: 64bit physical address of 2nd completed memory block if any completed 121 * block, otherwise zero value. 122 * a3: 64bit physical address of 3rd completed memory block if any completed 123 * block, otherwise zero value. 124 */ 125 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2 126 #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \ 127 INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE) 128 129 /* 130 * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 131 * 132 * Sync call used by service driver at EL1 to track the completed write 133 * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE 134 * call returns INTEL_SIP_SMC_STATUS_BUSY. 135 * 136 * Call register usage: 137 * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE. 138 * a1-7: not used. 139 * 140 * Return status: 141 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or 142 * INTEL_SIP_SMC_STATUS_ERROR. 143 * a1: 64bit physical address of 1st completed memory block. 144 * a2: 64bit physical address of 2nd completed memory block if 145 * any completed block, otherwise zero value. 146 * a3: 64bit physical address of 3rd completed memory block if 147 * any completed block, otherwise zero value. 148 */ 149 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3 150 #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \ 151 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) 152 153 /* 154 * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 155 * 156 * Sync call used by service driver at EL1 to inform secure world that all 157 * data are sent, to check whether or not the secure world had completed 158 * the FPGA configuration process. 159 * 160 * Call register usage: 161 * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE. 162 * a1-7: not used. 163 * 164 * Return status: 165 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or 166 * INTEL_SIP_SMC_STATUS_ERROR. 167 * a1-3: not used. 168 */ 169 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4 170 #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \ 171 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE) 172 173 /* 174 * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 175 * 176 * Sync call used by service driver at EL1 to query the physical address of 177 * memory block reserved by secure monitor software. 178 * 179 * Call register usage: 180 * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM. 181 * a1-7: not used. 182 * 183 * Return status: 184 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. 185 * a1: start of physical address of reserved memory block. 186 * a2: size of reserved memory block. 187 * a3: not used. 188 */ 189 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5 190 #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \ 191 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM) 192 193 /* 194 * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK 195 * 196 * For SMC loop-back mode only, used for internal integration, debugging 197 * or troubleshooting. 198 * 199 * Call register usage: 200 * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK. 201 * a1-7: not used. 202 * 203 * Return status: 204 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR. 205 * a1-3: not used. 206 */ 207 #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6 208 #define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \ 209 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK) 210 211 /* 212 * Request INTEL_SIP_SMC_REG_READ 213 * 214 * Read a protected register using SMCCC 215 * 216 * Call register usage: 217 * a0: INTEL_SIP_SMC_REG_READ. 218 * a1: register address. 219 * a2-7: not used. 220 * 221 * Return status: 222 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. 223 * a1: Value in the register 224 * a2-3: not used. 225 */ 226 #define INTEL_SIP_SMC_FUNCID_REG_READ 7 227 #define INTEL_SIP_SMC_REG_READ \ 228 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ) 229 230 /* 231 * Request INTEL_SIP_SMC_REG_WRITE 232 * 233 * Write a protected register using SMCCC 234 * 235 * Call register usage: 236 * a0: INTEL_SIP_SMC_REG_WRITE. 237 * a1: register address 238 * a2: value to program into register. 239 * a3-7: not used. 240 * 241 * Return status: 242 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. 243 * a1-3: not used. 244 */ 245 #define INTEL_SIP_SMC_FUNCID_REG_WRITE 8 246 #define INTEL_SIP_SMC_REG_WRITE \ 247 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE) 248 249 /* 250 * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE 251 * 252 * Update one or more bits in a protected register using a 253 * read-modify-write operation. 254 * 255 * Call register usage: 256 * a0: INTEL_SIP_SMC_REG_UPDATE. 257 * a1: register address 258 * a2: Write Mask. 259 * a3: Value to write. 260 * a4-7: not used. 261 * 262 * Return status: 263 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. 264 * a1-3: Not used. 265 */ 266 #define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9 267 #define INTEL_SIP_SMC_REG_UPDATE \ 268 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE) 269 270 /* 271 * Request INTEL_SIP_SMC_RSU_STATUS 272 * 273 * Sync call used by service driver at EL1 to query the RSU status 274 * 275 * Call register usage: 276 * a0 INTEL_SIP_SMC_RSU_STATUS 277 * a1-7 not used 278 * 279 * Return status 280 * a0: Current Image 281 * a1: Last Failing Image 282 * a2: Version [width 32 bit] | State [width 32 bit] 283 * a3: Error details [width 32 bit] | Error location [width 32 bit] 284 * 285 * Or 286 * 287 * a0: INTEL_SIP_SMC_RSU_ERROR 288 */ 289 #define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11 290 #define INTEL_SIP_SMC_RSU_STATUS \ 291 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS) 292 293 /* 294 * Request INTEL_SIP_SMC_RSU_UPDATE 295 * 296 * Sync call used by service driver at EL1 to tell you next reboot is RSU_UPDATE 297 * 298 * Call register usage: 299 * a0 INTEL_SIP_SMC_RSU_UPDATE 300 * a1 64bit physical address of the configuration data memory in flash 301 * a2-7 not used 302 * 303 * Return status 304 * a0 INTEL_SIP_SMC_STATUS_OK 305 */ 306 #define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12 307 #define INTEL_SIP_SMC_RSU_UPDATE \ 308 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE) 309 310 /* 311 * Request INTEL_SIP_SMC_ECC_DBE 312 * 313 * Sync call used by service driver at EL1 alert EL3 that a Double Bit 314 * ECC error has occurred. 315 * 316 * Call register usage: 317 * a0 INTEL_SIP_SMC_ECC_DBE 318 * a1 SysManager Double Bit Error value 319 * a2-7 not used 320 * 321 * Return status 322 * a0 INTEL_SIP_SMC_STATUS_OK 323 */ 324 #define INTEL_SIP_SMC_FUNCID_ECC_DBE 13 325 #define INTEL_SIP_SMC_ECC_DBE \ 326 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE) 327 328 /* 329 * Request INTEL_SIP_SMC_RSU_NOTIFY 330 * 331 * Sync call used by service driver at EL1 to report HPS software execution stage 332 * 333 * Call register usage: 334 * a0 INTEL_SIP_SMC_RSU_NOTIFY 335 * a1 32bit HPS software execution stage 336 * a2-7 not used 337 * 338 * Return status 339 * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR. 340 */ 341 #define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14 342 #define INTEL_SIP_SMC_RSU_NOTIFY \ 343 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY) 344 345 /* 346 * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER 347 * 348 * Sync call used by service driver at EL1 to query the RSU retry counter 349 * 350 * Call register usage: 351 * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER 352 * a1-7 not used 353 * 354 * Return status 355 * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_RSU_ERROR. 356 * a1 retry counter 357 */ 358 #define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15 359 #define INTEL_SIP_SMC_RSU_RETRY_COUNTER \ 360 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER) 361 362 /* 363 * Request INTEL_SIP_SMC_RSU_DCMF_VERSION 364 * 365 * Sync call used by service driver at EL1 to query DCMF version 366 * 367 * Call register usage: 368 * a0 INTEL_SIP_SMC_RSU_DCMF_VERSION 369 * a1-7 not used 370 * 371 * Return status 372 * a0 INTEL_SIP_SMC_STATUS_OK 373 * a1 dcmf1 version | dcmf0 version 374 * a2 dcmf3 version | dcmf2 version 375 * 376 * Or 377 * 378 * a0 INTEL_SIP_SMC_RSU_ERROR 379 */ 380 #define INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION 16 381 #define INTEL_SIP_SMC_RSU_DCMF_VERSION \ 382 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION) 383 384 /* 385 * Request INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 386 * 387 * Sync call used by SSBL (EL2) to copy DCMF version to ATF memory 388 * 389 * Call register usage: 390 * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 391 * a1 dcmf1 version | dcmf0 version 392 * a2 dcmf3 version | dcmf2 version 393 * 394 * Return status 395 * a0 INTEL_SIP_SMC_STATUS_OK 396 */ 397 #define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION 17 398 #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION \ 399 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION) 400 401 /* 402 * Request INTEL_SIP_SMC_RSU_MAX_RETRY 403 * 404 * Sync call used by service driver at EL1 to query max_retry parameter 405 * 406 * Call register usage: 407 * a0 INTEL_SIP_SMC_RSU_MAX_RETRY 408 * a1-7 not used 409 * 410 * Return status 411 * a0 INTEL_SIP_SMC_STATUS_OK 412 * a1 max_retry 413 * 414 * Or 415 * 416 * a0 INTEL_SIP_SMC_RSU_ERROR 417 */ 418 #define INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY 18 419 #define INTEL_SIP_SMC_RSU_MAX_RETRY \ 420 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY) 421 422 /* 423 * Request INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 424 * 425 * Sync call used by SSBL (EL2) to copy RSU 'max retry' to ATF memory 426 * 427 * Call register usage: 428 * a0 INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 429 * a1 max retry 430 * a2-7 not used 431 * 432 * Return status 433 * a0 INTEL_SIP_SMC_STATUS_OK 434 */ 435 #define INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY 19 436 #define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY \ 437 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY) 438 439 /* 440 * Request INTEL_SIP_SMC_RSU_DCMF_STATUS 441 * 442 * Sync call used by service driver at EL1 to query DCMF status 443 * 444 * Call register usage: 445 * a0 INTEL_SIP_SMC_RSU_DCMF_STATUS 446 * a1-7 not used 447 * 448 * Return status 449 * a0 INTEL_SIP_SMC_STATUS_OK 450 * a1 dcmf3 status | dcmf2 status | dcmf1 status | dcmf0 status 451 * 452 * Or 453 * 454 * a0 INTEL_SIP_SMC_RSU_ERROR 455 */ 456 #define INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS 20 457 #define INTEL_SIP_SMC_RSU_DCMF_STATUS \ 458 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS) 459 460 /* 461 * Request INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 462 * 463 * Sync call used by SSBL (EL2) to copy RSU 'dcmf status' to ATF memory 464 * 465 * Call register usage: 466 * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 467 * a1 dcmf status 468 * a2-7 not used 469 * 470 * Return status 471 * a0 INTEL_SIP_SMC_STATUS_OK 472 */ 473 #define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS 21 474 #define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS \ 475 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS) 476 477 /* 478 * Request INTEL_SIP_SMC_HPS_SET_BRIDGES 479 * 480 * Enable/disable the SoC FPGA bridges 481 * 482 * Call register usage: 483 * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES 484 * a1 Set bridges status: 485 * 0 - Disable 486 * 1 - Enable 487 * a2-7 not used 488 * 489 * Return status 490 * a0 INTEL_SIP_SMC_STATUS_OK 491 */ 492 #define INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES 50 493 #define INTEL_SIP_SMC_HPS_SET_BRIDGES \ 494 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES) 495 496 /* 497 * Request INTEL_SIP_SMC_MBOX_SEND_CMD 498 * 499 * Send mailbox command to SDM 500 * 501 * Call register usage: 502 * a0 INTEL_SIP_SMC_MBOX_SEND_CMD 503 * a1 Mailbox command 504 * a2 64bit physical address pointer to command's arguments 505 * a3 Length of the argument 506 * a4 Urgent command: 507 * 0 - Disable 508 * 1 - Enable 509 * a5 64bit physical address pointer to a buffer for receiving responses 510 * a6 Length of the buffer 511 * 512 * Return status 513 * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR 514 * a1 Status of mailbox response 515 * a2 Received length in the buffer 516 */ 517 #define INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD 60 518 #define INTEL_SIP_SMC_MBOX_SEND_CMD \ 519 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD) 520 521 /* 522 * Request INTEL_SIP_SMC_HPS_SET_PHYINTF 523 * 524 * Select EMACx PHY interface 525 * 526 * Call register usage: 527 * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF 528 * a1 EMAC number: 529 * 0 - EMAC0 530 * 1 - EMAC1 531 * 2 - EMAC2 532 * a2 Type of PHY interface: 533 * 0 - GMII_MII 534 * 1 - RGMII 535 * 2 - RMII 536 * 3 - RESET 537 * a3-7 not used 538 * 539 * Return status 540 * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR 541 */ 542 #define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF 61 543 #define INTEL_SIP_SMC_HPS_SET_PHYINTF \ 544 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF) 545 546 /* 547 * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK 548 * 549 * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC 550 * 551 * Call register usage: 552 * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK 553 * a1 Select which phase shift of the clock for cclk_in_drv (drvsel): 554 * 0 - 0 degree 555 * 1 - 45 degrees 556 * 2 - 90 degrees 557 * 3 - 135 degrees 558 * 4 - 180 degrees 559 * 5 - 225 degrees 560 * 6 - 270 degrees 561 * 7 - 315 degrees 562 * a2 Select which phase shift of the clock for cclk_in_sample (smplsel): 563 * (Same as above) 564 * a3-7 not used 565 * 566 * Return status 567 * a0 INTEL_SIP_SMC_STATUS_OK 568 */ 569 #define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK 62 570 #define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \ 571 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK) 572 573 #endif 574