1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2017 Intel Corporation. 4 * Take from coreboot project file of the same name 5 */ 6 7 #ifndef _ASM_ARCH_IOMAP_H 8 #define _ASM_ARCH_IOMAP_H 9 10 #define R_ACPI_PM1_TMR 0x8 11 12 /* Put p2sb at 0xd0000000 in TPL */ 13 #define IOMAP_P2SB_BAR 0xd0000000 14 #define IOMAP_P2SB_SIZE 0x10000000 15 16 #define IOMAP_SPI_BASE 0xfe010000 17 18 #define IOMAP_ACPI_BASE 0x400 19 #define IOMAP_ACPI_SIZE 0x100 20 #define ACPI_BASE_ADDRESS IOMAP_ACPI_BASE 21 22 #define PMC_BAR0 0xfe042000 23 24 #define MCH_BASE_ADDRESS 0xfed10000 25 #define MCH_SIZE 0x8000 26 27 #ifdef __ACPI__ 28 #define HPET_BASE_ADDRESS 0xfed00000 29 30 #define SRAM_BASE_0 0xfe900000 31 #define SRAM_SIZE_0 (8 * KiB) 32 #define SRAM_BASE_2 0xfe902000 33 #define SRAM_SIZE_2 (4 * KiB) 34 #endif 35 36 /* Early address for I2C port 2 */ 37 #define IOMAP_I2C2_BASE (0xfe020000 + 2 * 0x1000) 38 39 /* 40 * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial 41 * node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE. 42 */ 43 #define PCH_DEV_UART PCI_BDF(0, 0x18, 2) 44 45 #define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0) 46 #define PCH_DEV_SPI PCI_BDF(0, 0x0d, 2) 47 48 #endif 49