1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #ifndef A8K_PLAT_DEF_H 9 #define A8K_PLAT_DEF_H 10 11 #include <marvell_def.h> 12 13 #define MVEBU_PRIMARY_CPU 0x0 14 #define MVEBU_AP0 0x0 15 16 /* APN806 revision ID */ 17 #define MVEBU_CSS_GWD_CTRL_IIDR2_REG (MVEBU_REGS_BASE + 0x610FCC) 18 #define GWD_IIDR2_REV_ID_OFFSET 12 19 #define GWD_IIDR2_REV_ID_MASK 0xF 20 #define GWD_IIDR2_CHIP_ID_OFFSET 20 21 #define GWD_IIDR2_CHIP_ID_MASK (0xFFFu << GWD_IIDR2_CHIP_ID_OFFSET) 22 23 #define CHIP_ID_AP806 0x806 24 #define CHIP_ID_AP807 0x807 25 26 #define COUNTER_FREQUENCY 25000000 27 28 #define MVEBU_REGS_BASE 0xF0000000 29 #define MVEBU_REGS_BASE_MASK 0xF0000000 30 #define MVEBU_REGS_BASE_AP(ap) MVEBU_REGS_BASE 31 #define MVEBU_AP_IO_BASE(ap) 0xF2000000 32 #define MVEBU_CP_OFFSET 0x2000000 33 #define MVEBU_CP_REGS_BASE(cp_index) (MVEBU_AP_IO_BASE(0) + \ 34 (cp_index) * MVEBU_CP_OFFSET) 35 #define MVEBU_RFU_BASE (MVEBU_REGS_BASE + 0x6F0000) 36 #define MVEBU_IO_WIN_BASE(ap_index) (MVEBU_RFU_BASE) 37 #define MVEBU_IO_WIN_GCR_OFFSET (0x70) 38 #define MVEBU_IO_WIN_MAX_WINS (7) 39 40 /* Misc SoC configurations Base */ 41 #define MVEBU_MISC_SOC_BASE (MVEBU_REGS_BASE + 0x6F4300) 42 43 #define MVEBU_CCU_BASE(ap_index) (MVEBU_REGS_BASE + 0x4000) 44 #define MVEBU_CCU_MAX_WINS (8) 45 46 #define MVEBU_LLC_BASE(ap_index) (MVEBU_REGS_BASE + 0x8000) 47 #define MVEBU_DRAM_MAC_BASE (MVEBU_REGS_BASE + 0x20000) 48 #define MVEBU_DRAM_PHY_BASE (MVEBU_REGS_BASE + 0x20000) 49 #define MVEBU_SMMU_BASE (MVEBU_REGS_BASE + 0x100000) 50 #define MVEBU_CP_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 51 0x440000 + ((n) << 2)) 52 #define MVEBU_PM_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 53 0x440000 + ((n / 8) << 2)) 54 #define MVEBU_CP_GPIO_DATA_OUT(cp_index, n) \ 55 (MVEBU_CP_REGS_BASE(cp_index) + \ 56 0x440100 + ((n > 31) ? 0x40 : 0x00)) 57 #define MVEBU_CP_GPIO_DATA_OUT_EN(cp_index, n) \ 58 (MVEBU_CP_REGS_BASE(cp_index) + \ 59 0x440104 + ((n > 31) ? 0x40 : 0x00)) 60 #define MVEBU_CP_GPIO_DATA_IN(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 61 0x440110 + ((n > 31) ? 0x40 : 0x00)) 62 #define MVEBU_AP_MPP_REGS(n) (MVEBU_RFU_BASE + 0x4000 + ((n) << 2)) 63 #define MVEBU_AP_GPIO_REGS (MVEBU_RFU_BASE + 0x5040) 64 #define MVEBU_AP_GPIO_DATA_IN (MVEBU_AP_GPIO_REGS + 0x10) 65 #define MVEBU_AP_I2C_BASE (MVEBU_REGS_BASE + 0x511000) 66 #define MVEBU_CP0_I2C_BASE (MVEBU_CP_REGS_BASE(0) + 0x701000) 67 #define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000) 68 #define MVEBU_AP_EXT_TSEN_BASE (MVEBU_AP_GEN_MGMT_BASE + 0x84) 69 70 #define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ 71 0x20080 + ((win) * 0x8)) 72 #define MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ 73 0x20084 + ((win) * 0x8)) 74 75 /* MCI indirect access definitions */ 76 #define MCI_MAX_UNIT_ID 2 77 /* SoC RFU / IHBx4 Control */ 78 #define MCIX4_REG_START_ADDRESS_REG(unit_id) (MVEBU_RFU_BASE + \ 79 0x4218 + (unit_id * 0x20)) 80 #define MCI_REMAP_OFF_SHIFT 8 81 82 #define MVEBU_MCI_REG_BASE_REMAP(index) (0xFD000000 + \ 83 ((index) * 0x1000000)) 84 85 #define MVEBU_PCIE_X4_MAC_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x600000) 86 #define MVEBU_COMPHY_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x441000) 87 #define MVEBU_HPIPE_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x120000) 88 #define MVEBU_CP_DFX_OFFSET (0x400200) 89 90 /***************************************************************************** 91 * MVEBU memory map related constants 92 ***************************************************************************** 93 */ 94 /* Aggregate of all devices in the first GB */ 95 #define DEVICE0_BASE MVEBU_REGS_BASE 96 #define DEVICE0_SIZE 0x10000000 97 98 /***************************************************************************** 99 * GIC-400 & interrupt handling related constants 100 ***************************************************************************** 101 */ 102 /* Base MVEBU compatible GIC memory map */ 103 #define MVEBU_GICD_BASE 0x210000 104 #define MVEBU_GICC_BASE 0x220000 105 106 107 /***************************************************************************** 108 * AXI Configuration 109 ***************************************************************************** 110 */ 111 #define MVEBU_AXI_ATTR_ARCACHE_OFFSET 4 112 #define MVEBU_AXI_ATTR_ARCACHE_MASK (0xF << \ 113 MVEBU_AXI_ATTR_ARCACHE_OFFSET) 114 #define MVEBU_AXI_ATTR_ARDOMAIN_OFFSET 12 115 #define MVEBU_AXI_ATTR_ARDOMAIN_MASK (0x3 << \ 116 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET) 117 #define MVEBU_AXI_ATTR_AWCACHE_OFFSET 20 118 #define MVEBU_AXI_ATTR_AWCACHE_MASK (0xF << \ 119 MVEBU_AXI_ATTR_AWCACHE_OFFSET) 120 #define MVEBU_AXI_ATTR_AWDOMAIN_OFFSET 28 121 #define MVEBU_AXI_ATTR_AWDOMAIN_MASK (0x3 << \ 122 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET) 123 124 /* SATA MBUS to AXI configuration */ 125 #define MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET 1 126 #define MVEBU_SATA_M2A_AXI_ARCACHE_MASK (0xF << \ 127 MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET) 128 #define MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET 5 129 #define MVEBU_SATA_M2A_AXI_AWCACHE_MASK (0xF << \ 130 MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET) 131 132 /* ARM cache attributes */ 133 #define CACHE_ATTR_BUFFERABLE 0x1 134 #define CACHE_ATTR_CACHEABLE 0x2 135 #define CACHE_ATTR_READ_ALLOC 0x4 136 #define CACHE_ATTR_WRITE_ALLOC 0x8 137 /* Domain */ 138 #define DOMAIN_NON_SHAREABLE 0x0 139 #define DOMAIN_INNER_SHAREABLE 0x1 140 #define DOMAIN_OUTER_SHAREABLE 0x2 141 #define DOMAIN_SYSTEM_SHAREABLE 0x3 142 143 /************************************************************************ 144 * Required platform porting definitions common to all 145 * Management Compute SubSystems (MSS) 146 ************************************************************************ 147 */ 148 /* 149 * Load address of SCP_BL2 150 * SCP_BL2 is loaded to the same place as BL31. 151 * Once SCP_BL2 is transferred to the SCP, 152 * it is discarded and BL31 is loaded over the top. 153 */ 154 #ifdef SCP_IMAGE 155 #define SCP_BL2_BASE BL31_BASE 156 #define SCP_BL2_SIZE BL31_LIMIT 157 #endif 158 159 #ifndef __ASSEMBLER__ 160 enum ap806_sar_target_dev { 161 SAR_PIDI_MCIX2 = 0x0, 162 SAR_MCIX4 = 0x1, 163 SAR_SPI = 0x2, 164 SAR_SD = 0x3, 165 SAR_PIDI_MCIX2_BD = 0x4, /* BootRom disabled */ 166 SAR_MCIX4_DB = 0x5, /* BootRom disabled */ 167 SAR_SPI_DB = 0x6, /* BootRom disabled */ 168 SAR_EMMC = 0x7 169 }; 170 171 enum io_win_target_ids { 172 MCI_0_TID = 0x0, 173 MCI_1_TID = 0x1, 174 MCI_2_TID = 0x2, 175 PIDI_TID = 0x3, 176 SPI_TID = 0x4, 177 STM_TID = 0x5, 178 BOOTROM_TID = 0x6, 179 IO_WIN_MAX_TID 180 }; 181 182 enum ccu_target_ids { 183 IO_0_TID = 0x00, 184 DRAM_0_TID = 0x03, 185 IO_1_TID = 0x0F, 186 CFG_REG_TID = 0x10, 187 RAR_TID = 0x20, 188 SRAM_TID = 0x40, 189 DRAM_1_TID = 0xC0, 190 CCU_MAX_TID, 191 INVALID_TID = 0xFF 192 }; 193 #endif /* __ASSEMBLER__ */ 194 195 #endif /* A8K_PLAT_DEF_H */ 196