1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_IRQ_H
3 #define _LINUX_IRQ_H
4 
5 /*
6  * Please do not include this file in generic code.  There is currently
7  * no requirement for any architecture to implement anything held
8  * within this file.
9  *
10  * Thanks. --rmk
11  */
12 
13 #include <linux/cache.h>
14 #include <linux/spinlock.h>
15 #include <linux/cpumask.h>
16 #include <linux/irqhandler.h>
17 #include <linux/irqreturn.h>
18 #include <linux/irqnr.h>
19 #include <linux/topology.h>
20 #include <linux/io.h>
21 #include <linux/slab.h>
22 
23 #include <asm/irq.h>
24 #include <asm/ptrace.h>
25 #include <asm/irq_regs.h>
26 
27 struct seq_file;
28 struct module;
29 struct msi_msg;
30 struct irq_affinity_desc;
31 enum irqchip_irq_state;
32 
33 /*
34  * IRQ line status.
35  *
36  * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
37  *
38  * IRQ_TYPE_NONE		- default, unspecified type
39  * IRQ_TYPE_EDGE_RISING		- rising edge triggered
40  * IRQ_TYPE_EDGE_FALLING	- falling edge triggered
41  * IRQ_TYPE_EDGE_BOTH		- rising and falling edge triggered
42  * IRQ_TYPE_LEVEL_HIGH		- high level triggered
43  * IRQ_TYPE_LEVEL_LOW		- low level triggered
44  * IRQ_TYPE_LEVEL_MASK		- Mask to filter out the level bits
45  * IRQ_TYPE_SENSE_MASK		- Mask for all the above bits
46  * IRQ_TYPE_DEFAULT		- For use by some PICs to ask irq_set_type
47  *				  to setup the HW to a sane default (used
48  *                                by irqdomain map() callbacks to synchronize
49  *                                the HW state and SW flags for a newly
50  *                                allocated descriptor).
51  *
52  * IRQ_TYPE_PROBE		- Special flag for probing in progress
53  *
54  * Bits which can be modified via irq_set/clear/modify_status_flags()
55  * IRQ_LEVEL			- Interrupt is level type. Will be also
56  *				  updated in the code when the above trigger
57  *				  bits are modified via irq_set_irq_type()
58  * IRQ_PER_CPU			- Mark an interrupt PER_CPU. Will protect
59  *				  it from affinity setting
60  * IRQ_NOPROBE			- Interrupt cannot be probed by autoprobing
61  * IRQ_NOREQUEST		- Interrupt cannot be requested via
62  *				  request_irq()
63  * IRQ_NOTHREAD			- Interrupt cannot be threaded
64  * IRQ_NOAUTOEN			- Interrupt is not automatically enabled in
65  *				  request/setup_irq()
66  * IRQ_NO_BALANCING		- Interrupt cannot be balanced (affinity set)
67  * IRQ_MOVE_PCNTXT		- Interrupt can be migrated from process context
68  * IRQ_NESTED_THREAD		- Interrupt nests into another thread
69  * IRQ_PER_CPU_DEVID		- Dev_id is a per-cpu variable
70  * IRQ_IS_POLLED		- Always polled by another interrupt. Exclude
71  *				  it from the spurious interrupt detection
72  *				  mechanism and from core side polling.
73  * IRQ_DISABLE_UNLAZY		- Disable lazy irq disable
74  * IRQ_HIDDEN			- Don't show up in /proc/interrupts
75  * IRQ_NO_DEBUG			- Exclude from note_interrupt() debugging
76  */
77 enum {
78 	IRQ_TYPE_NONE		= 0x00000000,
79 	IRQ_TYPE_EDGE_RISING	= 0x00000001,
80 	IRQ_TYPE_EDGE_FALLING	= 0x00000002,
81 	IRQ_TYPE_EDGE_BOTH	= (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
82 	IRQ_TYPE_LEVEL_HIGH	= 0x00000004,
83 	IRQ_TYPE_LEVEL_LOW	= 0x00000008,
84 	IRQ_TYPE_LEVEL_MASK	= (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
85 	IRQ_TYPE_SENSE_MASK	= 0x0000000f,
86 	IRQ_TYPE_DEFAULT	= IRQ_TYPE_SENSE_MASK,
87 
88 	IRQ_TYPE_PROBE		= 0x00000010,
89 
90 	IRQ_LEVEL		= (1 <<  8),
91 	IRQ_PER_CPU		= (1 <<  9),
92 	IRQ_NOPROBE		= (1 << 10),
93 	IRQ_NOREQUEST		= (1 << 11),
94 	IRQ_NOAUTOEN		= (1 << 12),
95 	IRQ_NO_BALANCING	= (1 << 13),
96 	IRQ_MOVE_PCNTXT		= (1 << 14),
97 	IRQ_NESTED_THREAD	= (1 << 15),
98 	IRQ_NOTHREAD		= (1 << 16),
99 	IRQ_PER_CPU_DEVID	= (1 << 17),
100 	IRQ_IS_POLLED		= (1 << 18),
101 	IRQ_DISABLE_UNLAZY	= (1 << 19),
102 	IRQ_HIDDEN		= (1 << 20),
103 	IRQ_NO_DEBUG		= (1 << 21),
104 };
105 
106 #define IRQF_MODIFY_MASK	\
107 	(IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
108 	 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
109 	 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
110 	 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN)
111 
112 #define IRQ_NO_BALANCING_MASK	(IRQ_PER_CPU | IRQ_NO_BALANCING)
113 
114 /*
115  * Return value for chip->irq_set_affinity()
116  *
117  * IRQ_SET_MASK_OK	- OK, core updates irq_common_data.affinity
118  * IRQ_SET_MASK_NOCPY	- OK, chip did update irq_common_data.affinity
119  * IRQ_SET_MASK_OK_DONE	- Same as IRQ_SET_MASK_OK for core. Special code to
120  *			  support stacked irqchips, which indicates skipping
121  *			  all descendant irqchips.
122  */
123 enum {
124 	IRQ_SET_MASK_OK = 0,
125 	IRQ_SET_MASK_OK_NOCOPY,
126 	IRQ_SET_MASK_OK_DONE,
127 };
128 
129 struct msi_desc;
130 struct irq_domain;
131 
132 /**
133  * struct irq_common_data - per irq data shared by all irqchips
134  * @state_use_accessors: status information for irq chip functions.
135  *			Use accessor functions to deal with it
136  * @node:		node index useful for balancing
137  * @handler_data:	per-IRQ data for the irq_chip methods
138  * @affinity:		IRQ affinity on SMP. If this is an IPI
139  *			related irq, then this is the mask of the
140  *			CPUs to which an IPI can be sent.
141  * @effective_affinity:	The effective IRQ affinity on SMP as some irq
142  *			chips do not allow multi CPU destinations.
143  *			A subset of @affinity.
144  * @msi_desc:		MSI descriptor
145  * @ipi_offset:		Offset of first IPI target cpu in @affinity. Optional.
146  */
147 struct irq_common_data {
148 	unsigned int		__private state_use_accessors;
149 #ifdef CONFIG_NUMA
150 	unsigned int		node;
151 #endif
152 	void			*handler_data;
153 	struct msi_desc		*msi_desc;
154 	cpumask_var_t		affinity;
155 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
156 	cpumask_var_t		effective_affinity;
157 #endif
158 #ifdef CONFIG_GENERIC_IRQ_IPI
159 	unsigned int		ipi_offset;
160 #endif
161 };
162 
163 /**
164  * struct irq_data - per irq chip data passed down to chip functions
165  * @mask:		precomputed bitmask for accessing the chip registers
166  * @irq:		interrupt number
167  * @hwirq:		hardware interrupt number, local to the interrupt domain
168  * @common:		point to data shared by all irqchips
169  * @chip:		low level interrupt hardware access
170  * @domain:		Interrupt translation domain; responsible for mapping
171  *			between hwirq number and linux irq number.
172  * @parent_data:	pointer to parent struct irq_data to support hierarchy
173  *			irq_domain
174  * @chip_data:		platform-specific per-chip private data for the chip
175  *			methods, to allow shared chip implementations
176  */
177 struct irq_data {
178 	u32			mask;
179 	unsigned int		irq;
180 	unsigned long		hwirq;
181 	struct irq_common_data	*common;
182 	struct irq_chip		*chip;
183 	struct irq_domain	*domain;
184 #ifdef	CONFIG_IRQ_DOMAIN_HIERARCHY
185 	struct irq_data		*parent_data;
186 #endif
187 	void			*chip_data;
188 };
189 
190 /*
191  * Bit masks for irq_common_data.state_use_accessors
192  *
193  * IRQD_TRIGGER_MASK		- Mask for the trigger type bits
194  * IRQD_SETAFFINITY_PENDING	- Affinity setting is pending
195  * IRQD_ACTIVATED		- Interrupt has already been activated
196  * IRQD_NO_BALANCING		- Balancing disabled for this IRQ
197  * IRQD_PER_CPU			- Interrupt is per cpu
198  * IRQD_AFFINITY_SET		- Interrupt affinity was set
199  * IRQD_LEVEL			- Interrupt is level triggered
200  * IRQD_WAKEUP_STATE		- Interrupt is configured for wakeup
201  *				  from suspend
202  * IRQD_MOVE_PCNTXT		- Interrupt can be moved in process
203  *				  context
204  * IRQD_IRQ_DISABLED		- Disabled state of the interrupt
205  * IRQD_IRQ_MASKED		- Masked state of the interrupt
206  * IRQD_IRQ_INPROGRESS		- In progress state of the interrupt
207  * IRQD_WAKEUP_ARMED		- Wakeup mode armed
208  * IRQD_FORWARDED_TO_VCPU	- The interrupt is forwarded to a VCPU
209  * IRQD_AFFINITY_MANAGED	- Affinity is auto-managed by the kernel
210  * IRQD_IRQ_STARTED		- Startup state of the interrupt
211  * IRQD_MANAGED_SHUTDOWN	- Interrupt was shutdown due to empty affinity
212  *				  mask. Applies only to affinity managed irqs.
213  * IRQD_SINGLE_TARGET		- IRQ allows only a single affinity target
214  * IRQD_DEFAULT_TRIGGER_SET	- Expected trigger already been set
215  * IRQD_CAN_RESERVE		- Can use reservation mode
216  * IRQD_MSI_NOMASK_QUIRK	- Non-maskable MSI quirk for affinity change
217  *				  required
218  * IRQD_HANDLE_ENFORCE_IRQCTX	- Enforce that handle_irq_*() is only invoked
219  *				  from actual interrupt context.
220  * IRQD_AFFINITY_ON_ACTIVATE	- Affinity is set on activation. Don't call
221  *				  irq_chip::irq_set_affinity() when deactivated.
222  * IRQD_IRQ_ENABLED_ON_SUSPEND	- Interrupt is enabled on suspend by irq pm if
223  *				  irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set.
224  */
225 enum {
226 	IRQD_TRIGGER_MASK		= 0xf,
227 	IRQD_SETAFFINITY_PENDING	= (1 <<  8),
228 	IRQD_ACTIVATED			= (1 <<  9),
229 	IRQD_NO_BALANCING		= (1 << 10),
230 	IRQD_PER_CPU			= (1 << 11),
231 	IRQD_AFFINITY_SET		= (1 << 12),
232 	IRQD_LEVEL			= (1 << 13),
233 	IRQD_WAKEUP_STATE		= (1 << 14),
234 	IRQD_MOVE_PCNTXT		= (1 << 15),
235 	IRQD_IRQ_DISABLED		= (1 << 16),
236 	IRQD_IRQ_MASKED			= (1 << 17),
237 	IRQD_IRQ_INPROGRESS		= (1 << 18),
238 	IRQD_WAKEUP_ARMED		= (1 << 19),
239 	IRQD_FORWARDED_TO_VCPU		= (1 << 20),
240 	IRQD_AFFINITY_MANAGED		= (1 << 21),
241 	IRQD_IRQ_STARTED		= (1 << 22),
242 	IRQD_MANAGED_SHUTDOWN		= (1 << 23),
243 	IRQD_SINGLE_TARGET		= (1 << 24),
244 	IRQD_DEFAULT_TRIGGER_SET	= (1 << 25),
245 	IRQD_CAN_RESERVE		= (1 << 26),
246 	IRQD_MSI_NOMASK_QUIRK		= (1 << 27),
247 	IRQD_HANDLE_ENFORCE_IRQCTX	= (1 << 28),
248 	IRQD_AFFINITY_ON_ACTIVATE	= (1 << 29),
249 	IRQD_IRQ_ENABLED_ON_SUSPEND	= (1 << 30),
250 };
251 
252 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
253 
irqd_is_setaffinity_pending(struct irq_data * d)254 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
255 {
256 	return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
257 }
258 
irqd_is_per_cpu(struct irq_data * d)259 static inline bool irqd_is_per_cpu(struct irq_data *d)
260 {
261 	return __irqd_to_state(d) & IRQD_PER_CPU;
262 }
263 
irqd_can_balance(struct irq_data * d)264 static inline bool irqd_can_balance(struct irq_data *d)
265 {
266 	return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
267 }
268 
irqd_affinity_was_set(struct irq_data * d)269 static inline bool irqd_affinity_was_set(struct irq_data *d)
270 {
271 	return __irqd_to_state(d) & IRQD_AFFINITY_SET;
272 }
273 
irqd_mark_affinity_was_set(struct irq_data * d)274 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
275 {
276 	__irqd_to_state(d) |= IRQD_AFFINITY_SET;
277 }
278 
irqd_trigger_type_was_set(struct irq_data * d)279 static inline bool irqd_trigger_type_was_set(struct irq_data *d)
280 {
281 	return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET;
282 }
283 
irqd_get_trigger_type(struct irq_data * d)284 static inline u32 irqd_get_trigger_type(struct irq_data *d)
285 {
286 	return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
287 }
288 
289 /*
290  * Must only be called inside irq_chip.irq_set_type() functions or
291  * from the DT/ACPI setup code.
292  */
irqd_set_trigger_type(struct irq_data * d,u32 type)293 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
294 {
295 	__irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
296 	__irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
297 	__irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET;
298 }
299 
irqd_is_level_type(struct irq_data * d)300 static inline bool irqd_is_level_type(struct irq_data *d)
301 {
302 	return __irqd_to_state(d) & IRQD_LEVEL;
303 }
304 
305 /*
306  * Must only be called of irqchip.irq_set_affinity() or low level
307  * hierarchy domain allocation functions.
308  */
irqd_set_single_target(struct irq_data * d)309 static inline void irqd_set_single_target(struct irq_data *d)
310 {
311 	__irqd_to_state(d) |= IRQD_SINGLE_TARGET;
312 }
313 
irqd_is_single_target(struct irq_data * d)314 static inline bool irqd_is_single_target(struct irq_data *d)
315 {
316 	return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
317 }
318 
irqd_set_handle_enforce_irqctx(struct irq_data * d)319 static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d)
320 {
321 	__irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX;
322 }
323 
irqd_is_handle_enforce_irqctx(struct irq_data * d)324 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d)
325 {
326 	return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX;
327 }
328 
irqd_is_enabled_on_suspend(struct irq_data * d)329 static inline bool irqd_is_enabled_on_suspend(struct irq_data *d)
330 {
331 	return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND;
332 }
333 
irqd_is_wakeup_set(struct irq_data * d)334 static inline bool irqd_is_wakeup_set(struct irq_data *d)
335 {
336 	return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
337 }
338 
irqd_can_move_in_process_context(struct irq_data * d)339 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
340 {
341 	return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
342 }
343 
irqd_irq_disabled(struct irq_data * d)344 static inline bool irqd_irq_disabled(struct irq_data *d)
345 {
346 	return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
347 }
348 
irqd_irq_masked(struct irq_data * d)349 static inline bool irqd_irq_masked(struct irq_data *d)
350 {
351 	return __irqd_to_state(d) & IRQD_IRQ_MASKED;
352 }
353 
irqd_irq_inprogress(struct irq_data * d)354 static inline bool irqd_irq_inprogress(struct irq_data *d)
355 {
356 	return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
357 }
358 
irqd_is_wakeup_armed(struct irq_data * d)359 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
360 {
361 	return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
362 }
363 
irqd_is_forwarded_to_vcpu(struct irq_data * d)364 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
365 {
366 	return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
367 }
368 
irqd_set_forwarded_to_vcpu(struct irq_data * d)369 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
370 {
371 	__irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
372 }
373 
irqd_clr_forwarded_to_vcpu(struct irq_data * d)374 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
375 {
376 	__irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
377 }
378 
irqd_affinity_is_managed(struct irq_data * d)379 static inline bool irqd_affinity_is_managed(struct irq_data *d)
380 {
381 	return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
382 }
383 
irqd_is_activated(struct irq_data * d)384 static inline bool irqd_is_activated(struct irq_data *d)
385 {
386 	return __irqd_to_state(d) & IRQD_ACTIVATED;
387 }
388 
irqd_set_activated(struct irq_data * d)389 static inline void irqd_set_activated(struct irq_data *d)
390 {
391 	__irqd_to_state(d) |= IRQD_ACTIVATED;
392 }
393 
irqd_clr_activated(struct irq_data * d)394 static inline void irqd_clr_activated(struct irq_data *d)
395 {
396 	__irqd_to_state(d) &= ~IRQD_ACTIVATED;
397 }
398 
irqd_is_started(struct irq_data * d)399 static inline bool irqd_is_started(struct irq_data *d)
400 {
401 	return __irqd_to_state(d) & IRQD_IRQ_STARTED;
402 }
403 
irqd_is_managed_and_shutdown(struct irq_data * d)404 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
405 {
406 	return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
407 }
408 
irqd_set_can_reserve(struct irq_data * d)409 static inline void irqd_set_can_reserve(struct irq_data *d)
410 {
411 	__irqd_to_state(d) |= IRQD_CAN_RESERVE;
412 }
413 
irqd_clr_can_reserve(struct irq_data * d)414 static inline void irqd_clr_can_reserve(struct irq_data *d)
415 {
416 	__irqd_to_state(d) &= ~IRQD_CAN_RESERVE;
417 }
418 
irqd_can_reserve(struct irq_data * d)419 static inline bool irqd_can_reserve(struct irq_data *d)
420 {
421 	return __irqd_to_state(d) & IRQD_CAN_RESERVE;
422 }
423 
irqd_set_msi_nomask_quirk(struct irq_data * d)424 static inline void irqd_set_msi_nomask_quirk(struct irq_data *d)
425 {
426 	__irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK;
427 }
428 
irqd_clr_msi_nomask_quirk(struct irq_data * d)429 static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d)
430 {
431 	__irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK;
432 }
433 
irqd_msi_nomask_quirk(struct irq_data * d)434 static inline bool irqd_msi_nomask_quirk(struct irq_data *d)
435 {
436 	return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK;
437 }
438 
irqd_set_affinity_on_activate(struct irq_data * d)439 static inline void irqd_set_affinity_on_activate(struct irq_data *d)
440 {
441 	__irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE;
442 }
443 
irqd_affinity_on_activate(struct irq_data * d)444 static inline bool irqd_affinity_on_activate(struct irq_data *d)
445 {
446 	return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE;
447 }
448 
449 #undef __irqd_to_state
450 
irqd_to_hwirq(struct irq_data * d)451 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
452 {
453 	return d->hwirq;
454 }
455 
456 /**
457  * struct irq_chip - hardware interrupt chip descriptor
458  *
459  * @parent_device:	pointer to parent device for irqchip
460  * @name:		name for /proc/interrupts
461  * @irq_startup:	start up the interrupt (defaults to ->enable if NULL)
462  * @irq_shutdown:	shut down the interrupt (defaults to ->disable if NULL)
463  * @irq_enable:		enable the interrupt (defaults to chip->unmask if NULL)
464  * @irq_disable:	disable the interrupt
465  * @irq_ack:		start of a new interrupt
466  * @irq_mask:		mask an interrupt source
467  * @irq_mask_ack:	ack and mask an interrupt source
468  * @irq_unmask:		unmask an interrupt source
469  * @irq_eoi:		end of interrupt
470  * @irq_set_affinity:	Set the CPU affinity on SMP machines. If the force
471  *			argument is true, it tells the driver to
472  *			unconditionally apply the affinity setting. Sanity
473  *			checks against the supplied affinity mask are not
474  *			required. This is used for CPU hotplug where the
475  *			target CPU is not yet set in the cpu_online_mask.
476  * @irq_retrigger:	resend an IRQ to the CPU
477  * @irq_set_type:	set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
478  * @irq_set_wake:	enable/disable power-management wake-on of an IRQ
479  * @irq_bus_lock:	function to lock access to slow bus (i2c) chips
480  * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
481  * @irq_cpu_online:	configure an interrupt source for a secondary CPU
482  * @irq_cpu_offline:	un-configure an interrupt source for a secondary CPU
483  * @irq_suspend:	function called from core code on suspend once per
484  *			chip, when one or more interrupts are installed
485  * @irq_resume:		function called from core code on resume once per chip,
486  *			when one ore more interrupts are installed
487  * @irq_pm_shutdown:	function called from core code on shutdown once per chip
488  * @irq_calc_mask:	Optional function to set irq_data.mask for special cases
489  * @irq_print_chip:	optional to print special chip info in show_interrupts
490  * @irq_request_resources:	optional to request resources before calling
491  *				any other callback related to this irq
492  * @irq_release_resources:	optional to release resources acquired with
493  *				irq_request_resources
494  * @irq_compose_msi_msg:	optional to compose message content for MSI
495  * @irq_write_msi_msg:	optional to write message content for MSI
496  * @irq_get_irqchip_state:	return the internal state of an interrupt
497  * @irq_set_irqchip_state:	set the internal state of a interrupt
498  * @irq_set_vcpu_affinity:	optional to target a vCPU in a virtual machine
499  * @ipi_send_single:	send a single IPI to destination cpus
500  * @ipi_send_mask:	send an IPI to destination cpus in cpumask
501  * @irq_nmi_setup:	function called from core code before enabling an NMI
502  * @irq_nmi_teardown:	function called from core code after disabling an NMI
503  * @flags:		chip specific flags
504  */
505 struct irq_chip {
506 	struct device	*parent_device;
507 	const char	*name;
508 	unsigned int	(*irq_startup)(struct irq_data *data);
509 	void		(*irq_shutdown)(struct irq_data *data);
510 	void		(*irq_enable)(struct irq_data *data);
511 	void		(*irq_disable)(struct irq_data *data);
512 
513 	void		(*irq_ack)(struct irq_data *data);
514 	void		(*irq_mask)(struct irq_data *data);
515 	void		(*irq_mask_ack)(struct irq_data *data);
516 	void		(*irq_unmask)(struct irq_data *data);
517 	void		(*irq_eoi)(struct irq_data *data);
518 
519 	int		(*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
520 	int		(*irq_retrigger)(struct irq_data *data);
521 	int		(*irq_set_type)(struct irq_data *data, unsigned int flow_type);
522 	int		(*irq_set_wake)(struct irq_data *data, unsigned int on);
523 
524 	void		(*irq_bus_lock)(struct irq_data *data);
525 	void		(*irq_bus_sync_unlock)(struct irq_data *data);
526 
527 #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE
528 	void		(*irq_cpu_online)(struct irq_data *data);
529 	void		(*irq_cpu_offline)(struct irq_data *data);
530 #endif
531 	void		(*irq_suspend)(struct irq_data *data);
532 	void		(*irq_resume)(struct irq_data *data);
533 	void		(*irq_pm_shutdown)(struct irq_data *data);
534 
535 	void		(*irq_calc_mask)(struct irq_data *data);
536 
537 	void		(*irq_print_chip)(struct irq_data *data, struct seq_file *p);
538 	int		(*irq_request_resources)(struct irq_data *data);
539 	void		(*irq_release_resources)(struct irq_data *data);
540 
541 	void		(*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
542 	void		(*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
543 
544 	int		(*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
545 	int		(*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
546 
547 	int		(*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
548 
549 	void		(*ipi_send_single)(struct irq_data *data, unsigned int cpu);
550 	void		(*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
551 
552 	int		(*irq_nmi_setup)(struct irq_data *data);
553 	void		(*irq_nmi_teardown)(struct irq_data *data);
554 
555 	unsigned long	flags;
556 };
557 
558 /*
559  * irq_chip specific flags
560  *
561  * IRQCHIP_SET_TYPE_MASKED:           Mask before calling chip.irq_set_type()
562  * IRQCHIP_EOI_IF_HANDLED:            Only issue irq_eoi() when irq was handled
563  * IRQCHIP_MASK_ON_SUSPEND:           Mask non wake irqs in the suspend path
564  * IRQCHIP_ONOFFLINE_ENABLED:         Only call irq_on/off_line callbacks
565  *                                    when irq enabled
566  * IRQCHIP_SKIP_SET_WAKE:             Skip chip.irq_set_wake(), for this irq chip
567  * IRQCHIP_ONESHOT_SAFE:              One shot does not require mask/unmask
568  * IRQCHIP_EOI_THREADED:              Chip requires eoi() on unmask in threaded mode
569  * IRQCHIP_SUPPORTS_LEVEL_MSI:        Chip can provide two doorbells for Level MSIs
570  * IRQCHIP_SUPPORTS_NMI:              Chip can deliver NMIs, only for root irqchips
571  * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND:  Invokes __enable_irq()/__disable_irq() for wake irqs
572  *                                    in the suspend path if they are in disabled state
573  * IRQCHIP_AFFINITY_PRE_STARTUP:      Default affinity update before startup
574  */
575 enum {
576 	IRQCHIP_SET_TYPE_MASKED			= (1 <<  0),
577 	IRQCHIP_EOI_IF_HANDLED			= (1 <<  1),
578 	IRQCHIP_MASK_ON_SUSPEND			= (1 <<  2),
579 	IRQCHIP_ONOFFLINE_ENABLED		= (1 <<  3),
580 	IRQCHIP_SKIP_SET_WAKE			= (1 <<  4),
581 	IRQCHIP_ONESHOT_SAFE			= (1 <<  5),
582 	IRQCHIP_EOI_THREADED			= (1 <<  6),
583 	IRQCHIP_SUPPORTS_LEVEL_MSI		= (1 <<  7),
584 	IRQCHIP_SUPPORTS_NMI			= (1 <<  8),
585 	IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND	= (1 <<  9),
586 	IRQCHIP_AFFINITY_PRE_STARTUP		= (1 << 10),
587 };
588 
589 #include <linux/irqdesc.h>
590 
591 /*
592  * Pick up the arch-dependent methods:
593  */
594 #include <asm/hw_irq.h>
595 
596 #ifndef NR_IRQS_LEGACY
597 # define NR_IRQS_LEGACY 0
598 #endif
599 
600 #ifndef ARCH_IRQ_INIT_FLAGS
601 # define ARCH_IRQ_INIT_FLAGS	0
602 #endif
603 
604 #define IRQ_DEFAULT_INIT_FLAGS	ARCH_IRQ_INIT_FLAGS
605 
606 struct irqaction;
607 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
608 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
609 
610 #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE
611 extern void irq_cpu_online(void);
612 extern void irq_cpu_offline(void);
613 #endif
614 extern int irq_set_affinity_locked(struct irq_data *data,
615 				   const struct cpumask *cpumask, bool force);
616 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
617 
618 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
619 extern void irq_migrate_all_off_this_cpu(void);
620 extern int irq_affinity_online_cpu(unsigned int cpu);
621 #else
622 # define irq_affinity_online_cpu	NULL
623 #endif
624 
625 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
626 void __irq_move_irq(struct irq_data *data);
irq_move_irq(struct irq_data * data)627 static inline void irq_move_irq(struct irq_data *data)
628 {
629 	if (unlikely(irqd_is_setaffinity_pending(data)))
630 		__irq_move_irq(data);
631 }
632 void irq_move_masked_irq(struct irq_data *data);
633 void irq_force_complete_move(struct irq_desc *desc);
634 #else
irq_move_irq(struct irq_data * data)635 static inline void irq_move_irq(struct irq_data *data) { }
irq_move_masked_irq(struct irq_data * data)636 static inline void irq_move_masked_irq(struct irq_data *data) { }
irq_force_complete_move(struct irq_desc * desc)637 static inline void irq_force_complete_move(struct irq_desc *desc) { }
638 #endif
639 
640 extern int no_irq_affinity;
641 
642 #ifdef CONFIG_HARDIRQS_SW_RESEND
643 int irq_set_parent(int irq, int parent_irq);
644 #else
irq_set_parent(int irq,int parent_irq)645 static inline int irq_set_parent(int irq, int parent_irq)
646 {
647 	return 0;
648 }
649 #endif
650 
651 /*
652  * Built-in IRQ handlers for various IRQ types,
653  * callable via desc->handle_irq()
654  */
655 extern void handle_level_irq(struct irq_desc *desc);
656 extern void handle_fasteoi_irq(struct irq_desc *desc);
657 extern void handle_edge_irq(struct irq_desc *desc);
658 extern void handle_edge_eoi_irq(struct irq_desc *desc);
659 extern void handle_simple_irq(struct irq_desc *desc);
660 extern void handle_untracked_irq(struct irq_desc *desc);
661 extern void handle_percpu_irq(struct irq_desc *desc);
662 extern void handle_percpu_devid_irq(struct irq_desc *desc);
663 extern void handle_bad_irq(struct irq_desc *desc);
664 extern void handle_nested_irq(unsigned int irq);
665 
666 extern void handle_fasteoi_nmi(struct irq_desc *desc);
667 extern void handle_percpu_devid_fasteoi_nmi(struct irq_desc *desc);
668 
669 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
670 extern int irq_chip_pm_get(struct irq_data *data);
671 extern int irq_chip_pm_put(struct irq_data *data);
672 #ifdef	CONFIG_IRQ_DOMAIN_HIERARCHY
673 extern void handle_fasteoi_ack_irq(struct irq_desc *desc);
674 extern void handle_fasteoi_mask_irq(struct irq_desc *desc);
675 extern int irq_chip_set_parent_state(struct irq_data *data,
676 				     enum irqchip_irq_state which,
677 				     bool val);
678 extern int irq_chip_get_parent_state(struct irq_data *data,
679 				     enum irqchip_irq_state which,
680 				     bool *state);
681 extern void irq_chip_enable_parent(struct irq_data *data);
682 extern void irq_chip_disable_parent(struct irq_data *data);
683 extern void irq_chip_ack_parent(struct irq_data *data);
684 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
685 extern void irq_chip_mask_parent(struct irq_data *data);
686 extern void irq_chip_mask_ack_parent(struct irq_data *data);
687 extern void irq_chip_unmask_parent(struct irq_data *data);
688 extern void irq_chip_eoi_parent(struct irq_data *data);
689 extern int irq_chip_set_affinity_parent(struct irq_data *data,
690 					const struct cpumask *dest,
691 					bool force);
692 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
693 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
694 					     void *vcpu_info);
695 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
696 extern int irq_chip_request_resources_parent(struct irq_data *data);
697 extern void irq_chip_release_resources_parent(struct irq_data *data);
698 #endif
699 
700 /* Handling of unhandled and spurious interrupts: */
701 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
702 
703 
704 /* Enable/disable irq debugging output: */
705 extern int noirqdebug_setup(char *str);
706 
707 /* Checks whether the interrupt can be requested by request_irq(): */
708 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
709 
710 /* Dummy irq-chip implementations: */
711 extern struct irq_chip no_irq_chip;
712 extern struct irq_chip dummy_irq_chip;
713 
714 extern void
715 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
716 			      irq_flow_handler_t handle, const char *name);
717 
irq_set_chip_and_handler(unsigned int irq,struct irq_chip * chip,irq_flow_handler_t handle)718 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
719 					    irq_flow_handler_t handle)
720 {
721 	irq_set_chip_and_handler_name(irq, chip, handle, NULL);
722 }
723 
724 extern int irq_set_percpu_devid(unsigned int irq);
725 extern int irq_set_percpu_devid_partition(unsigned int irq,
726 					  const struct cpumask *affinity);
727 extern int irq_get_percpu_devid_partition(unsigned int irq,
728 					  struct cpumask *affinity);
729 
730 extern void
731 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
732 		  const char *name);
733 
734 static inline void
irq_set_handler(unsigned int irq,irq_flow_handler_t handle)735 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
736 {
737 	__irq_set_handler(irq, handle, 0, NULL);
738 }
739 
740 /*
741  * Set a highlevel chained flow handler for a given IRQ.
742  * (a chained handler is automatically enabled and set to
743  *  IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
744  */
745 static inline void
irq_set_chained_handler(unsigned int irq,irq_flow_handler_t handle)746 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
747 {
748 	__irq_set_handler(irq, handle, 1, NULL);
749 }
750 
751 /*
752  * Set a highlevel chained flow handler and its data for a given IRQ.
753  * (a chained handler is automatically enabled and set to
754  *  IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
755  */
756 void
757 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
758 				 void *data);
759 
760 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
761 
irq_set_status_flags(unsigned int irq,unsigned long set)762 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
763 {
764 	irq_modify_status(irq, 0, set);
765 }
766 
irq_clear_status_flags(unsigned int irq,unsigned long clr)767 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
768 {
769 	irq_modify_status(irq, clr, 0);
770 }
771 
irq_set_noprobe(unsigned int irq)772 static inline void irq_set_noprobe(unsigned int irq)
773 {
774 	irq_modify_status(irq, 0, IRQ_NOPROBE);
775 }
776 
irq_set_probe(unsigned int irq)777 static inline void irq_set_probe(unsigned int irq)
778 {
779 	irq_modify_status(irq, IRQ_NOPROBE, 0);
780 }
781 
irq_set_nothread(unsigned int irq)782 static inline void irq_set_nothread(unsigned int irq)
783 {
784 	irq_modify_status(irq, 0, IRQ_NOTHREAD);
785 }
786 
irq_set_thread(unsigned int irq)787 static inline void irq_set_thread(unsigned int irq)
788 {
789 	irq_modify_status(irq, IRQ_NOTHREAD, 0);
790 }
791 
irq_set_nested_thread(unsigned int irq,bool nest)792 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
793 {
794 	if (nest)
795 		irq_set_status_flags(irq, IRQ_NESTED_THREAD);
796 	else
797 		irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
798 }
799 
irq_set_percpu_devid_flags(unsigned int irq)800 static inline void irq_set_percpu_devid_flags(unsigned int irq)
801 {
802 	irq_set_status_flags(irq,
803 			     IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
804 			     IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
805 }
806 
807 /* Set/get chip/data for an IRQ: */
808 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
809 extern int irq_set_handler_data(unsigned int irq, void *data);
810 extern int irq_set_chip_data(unsigned int irq, void *data);
811 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
812 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
813 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
814 				struct msi_desc *entry);
815 extern struct irq_data *irq_get_irq_data(unsigned int irq);
816 
irq_get_chip(unsigned int irq)817 static inline struct irq_chip *irq_get_chip(unsigned int irq)
818 {
819 	struct irq_data *d = irq_get_irq_data(irq);
820 	return d ? d->chip : NULL;
821 }
822 
irq_data_get_irq_chip(struct irq_data * d)823 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
824 {
825 	return d->chip;
826 }
827 
irq_get_chip_data(unsigned int irq)828 static inline void *irq_get_chip_data(unsigned int irq)
829 {
830 	struct irq_data *d = irq_get_irq_data(irq);
831 	return d ? d->chip_data : NULL;
832 }
833 
irq_data_get_irq_chip_data(struct irq_data * d)834 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
835 {
836 	return d->chip_data;
837 }
838 
irq_get_handler_data(unsigned int irq)839 static inline void *irq_get_handler_data(unsigned int irq)
840 {
841 	struct irq_data *d = irq_get_irq_data(irq);
842 	return d ? d->common->handler_data : NULL;
843 }
844 
irq_data_get_irq_handler_data(struct irq_data * d)845 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
846 {
847 	return d->common->handler_data;
848 }
849 
irq_get_msi_desc(unsigned int irq)850 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
851 {
852 	struct irq_data *d = irq_get_irq_data(irq);
853 	return d ? d->common->msi_desc : NULL;
854 }
855 
irq_data_get_msi_desc(struct irq_data * d)856 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
857 {
858 	return d->common->msi_desc;
859 }
860 
irq_get_trigger_type(unsigned int irq)861 static inline u32 irq_get_trigger_type(unsigned int irq)
862 {
863 	struct irq_data *d = irq_get_irq_data(irq);
864 	return d ? irqd_get_trigger_type(d) : 0;
865 }
866 
irq_common_data_get_node(struct irq_common_data * d)867 static inline int irq_common_data_get_node(struct irq_common_data *d)
868 {
869 #ifdef CONFIG_NUMA
870 	return d->node;
871 #else
872 	return 0;
873 #endif
874 }
875 
irq_data_get_node(struct irq_data * d)876 static inline int irq_data_get_node(struct irq_data *d)
877 {
878 	return irq_common_data_get_node(d->common);
879 }
880 
irq_get_affinity_mask(int irq)881 static inline struct cpumask *irq_get_affinity_mask(int irq)
882 {
883 	struct irq_data *d = irq_get_irq_data(irq);
884 
885 	return d ? d->common->affinity : NULL;
886 }
887 
irq_data_get_affinity_mask(struct irq_data * d)888 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
889 {
890 	return d->common->affinity;
891 }
892 
893 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
894 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)895 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
896 {
897 	return d->common->effective_affinity;
898 }
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)899 static inline void irq_data_update_effective_affinity(struct irq_data *d,
900 						      const struct cpumask *m)
901 {
902 	cpumask_copy(d->common->effective_affinity, m);
903 }
904 #else
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)905 static inline void irq_data_update_effective_affinity(struct irq_data *d,
906 						      const struct cpumask *m)
907 {
908 }
909 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)910 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
911 {
912 	return d->common->affinity;
913 }
914 #endif
915 
irq_get_effective_affinity_mask(unsigned int irq)916 static inline struct cpumask *irq_get_effective_affinity_mask(unsigned int irq)
917 {
918 	struct irq_data *d = irq_get_irq_data(irq);
919 
920 	return d ? irq_data_get_effective_affinity_mask(d) : NULL;
921 }
922 
923 unsigned int arch_dynirq_lower_bound(unsigned int from);
924 
925 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
926 		      struct module *owner,
927 		      const struct irq_affinity_desc *affinity);
928 
929 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
930 			   unsigned int cnt, int node, struct module *owner,
931 			   const struct irq_affinity_desc *affinity);
932 
933 /* use macros to avoid needing export.h for THIS_MODULE */
934 #define irq_alloc_descs(irq, from, cnt, node)	\
935 	__irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
936 
937 #define irq_alloc_desc(node)			\
938 	irq_alloc_descs(-1, 1, 1, node)
939 
940 #define irq_alloc_desc_at(at, node)		\
941 	irq_alloc_descs(at, at, 1, node)
942 
943 #define irq_alloc_desc_from(from, node)		\
944 	irq_alloc_descs(-1, from, 1, node)
945 
946 #define irq_alloc_descs_from(from, cnt, node)	\
947 	irq_alloc_descs(-1, from, cnt, node)
948 
949 #define devm_irq_alloc_descs(dev, irq, from, cnt, node)		\
950 	__devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
951 
952 #define devm_irq_alloc_desc(dev, node)				\
953 	devm_irq_alloc_descs(dev, -1, 1, 1, node)
954 
955 #define devm_irq_alloc_desc_at(dev, at, node)			\
956 	devm_irq_alloc_descs(dev, at, at, 1, node)
957 
958 #define devm_irq_alloc_desc_from(dev, from, node)		\
959 	devm_irq_alloc_descs(dev, -1, from, 1, node)
960 
961 #define devm_irq_alloc_descs_from(dev, from, cnt, node)		\
962 	devm_irq_alloc_descs(dev, -1, from, cnt, node)
963 
964 void irq_free_descs(unsigned int irq, unsigned int cnt);
irq_free_desc(unsigned int irq)965 static inline void irq_free_desc(unsigned int irq)
966 {
967 	irq_free_descs(irq, 1);
968 }
969 
970 #ifdef CONFIG_GENERIC_IRQ_LEGACY
971 void irq_init_desc(unsigned int irq);
972 #endif
973 
974 /**
975  * struct irq_chip_regs - register offsets for struct irq_gci
976  * @enable:	Enable register offset to reg_base
977  * @disable:	Disable register offset to reg_base
978  * @mask:	Mask register offset to reg_base
979  * @ack:	Ack register offset to reg_base
980  * @eoi:	Eoi register offset to reg_base
981  * @type:	Type configuration register offset to reg_base
982  * @polarity:	Polarity configuration register offset to reg_base
983  */
984 struct irq_chip_regs {
985 	unsigned long		enable;
986 	unsigned long		disable;
987 	unsigned long		mask;
988 	unsigned long		ack;
989 	unsigned long		eoi;
990 	unsigned long		type;
991 	unsigned long		polarity;
992 };
993 
994 /**
995  * struct irq_chip_type - Generic interrupt chip instance for a flow type
996  * @chip:		The real interrupt chip which provides the callbacks
997  * @regs:		Register offsets for this chip
998  * @handler:		Flow handler associated with this chip
999  * @type:		Chip can handle these flow types
1000  * @mask_cache_priv:	Cached mask register private to the chip type
1001  * @mask_cache:		Pointer to cached mask register
1002  *
1003  * A irq_generic_chip can have several instances of irq_chip_type when
1004  * it requires different functions and register offsets for different
1005  * flow types.
1006  */
1007 struct irq_chip_type {
1008 	struct irq_chip		chip;
1009 	struct irq_chip_regs	regs;
1010 	irq_flow_handler_t	handler;
1011 	u32			type;
1012 	u32			mask_cache_priv;
1013 	u32			*mask_cache;
1014 };
1015 
1016 /**
1017  * struct irq_chip_generic - Generic irq chip data structure
1018  * @lock:		Lock to protect register and cache data access
1019  * @reg_base:		Register base address (virtual)
1020  * @reg_readl:		Alternate I/O accessor (defaults to readl if NULL)
1021  * @reg_writel:		Alternate I/O accessor (defaults to writel if NULL)
1022  * @suspend:		Function called from core code on suspend once per
1023  *			chip; can be useful instead of irq_chip::suspend to
1024  *			handle chip details even when no interrupts are in use
1025  * @resume:		Function called from core code on resume once per chip;
1026  *			can be useful instead of irq_chip::suspend to handle
1027  *			chip details even when no interrupts are in use
1028  * @irq_base:		Interrupt base nr for this chip
1029  * @irq_cnt:		Number of interrupts handled by this chip
1030  * @mask_cache:		Cached mask register shared between all chip types
1031  * @type_cache:		Cached type register
1032  * @polarity_cache:	Cached polarity register
1033  * @wake_enabled:	Interrupt can wakeup from suspend
1034  * @wake_active:	Interrupt is marked as an wakeup from suspend source
1035  * @num_ct:		Number of available irq_chip_type instances (usually 1)
1036  * @private:		Private data for non generic chip callbacks
1037  * @installed:		bitfield to denote installed interrupts
1038  * @unused:		bitfield to denote unused interrupts
1039  * @domain:		irq domain pointer
1040  * @list:		List head for keeping track of instances
1041  * @chip_types:		Array of interrupt irq_chip_types
1042  *
1043  * Note, that irq_chip_generic can have multiple irq_chip_type
1044  * implementations which can be associated to a particular irq line of
1045  * an irq_chip_generic instance. That allows to share and protect
1046  * state in an irq_chip_generic instance when we need to implement
1047  * different flow mechanisms (level/edge) for it.
1048  */
1049 struct irq_chip_generic {
1050 	raw_spinlock_t		lock;
1051 	void __iomem		*reg_base;
1052 	u32			(*reg_readl)(void __iomem *addr);
1053 	void			(*reg_writel)(u32 val, void __iomem *addr);
1054 	void			(*suspend)(struct irq_chip_generic *gc);
1055 	void			(*resume)(struct irq_chip_generic *gc);
1056 	unsigned int		irq_base;
1057 	unsigned int		irq_cnt;
1058 	u32			mask_cache;
1059 	u32			type_cache;
1060 	u32			polarity_cache;
1061 	u32			wake_enabled;
1062 	u32			wake_active;
1063 	unsigned int		num_ct;
1064 	void			*private;
1065 	unsigned long		installed;
1066 	unsigned long		unused;
1067 	struct irq_domain	*domain;
1068 	struct list_head	list;
1069 	struct irq_chip_type	chip_types[];
1070 };
1071 
1072 /**
1073  * enum irq_gc_flags - Initialization flags for generic irq chips
1074  * @IRQ_GC_INIT_MASK_CACHE:	Initialize the mask_cache by reading mask reg
1075  * @IRQ_GC_INIT_NESTED_LOCK:	Set the lock class of the irqs to nested for
1076  *				irq chips which need to call irq_set_wake() on
1077  *				the parent irq. Usually GPIO implementations
1078  * @IRQ_GC_MASK_CACHE_PER_TYPE:	Mask cache is chip type private
1079  * @IRQ_GC_NO_MASK:		Do not calculate irq_data->mask
1080  * @IRQ_GC_BE_IO:		Use big-endian register accesses (default: LE)
1081  */
1082 enum irq_gc_flags {
1083 	IRQ_GC_INIT_MASK_CACHE		= 1 << 0,
1084 	IRQ_GC_INIT_NESTED_LOCK		= 1 << 1,
1085 	IRQ_GC_MASK_CACHE_PER_TYPE	= 1 << 2,
1086 	IRQ_GC_NO_MASK			= 1 << 3,
1087 	IRQ_GC_BE_IO			= 1 << 4,
1088 };
1089 
1090 /*
1091  * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1092  * @irqs_per_chip:	Number of interrupts per chip
1093  * @num_chips:		Number of chips
1094  * @irq_flags_to_set:	IRQ* flags to set on irq setup
1095  * @irq_flags_to_clear:	IRQ* flags to clear on irq setup
1096  * @gc_flags:		Generic chip specific setup flags
1097  * @gc:			Array of pointers to generic interrupt chips
1098  */
1099 struct irq_domain_chip_generic {
1100 	unsigned int		irqs_per_chip;
1101 	unsigned int		num_chips;
1102 	unsigned int		irq_flags_to_clear;
1103 	unsigned int		irq_flags_to_set;
1104 	enum irq_gc_flags	gc_flags;
1105 	struct irq_chip_generic	*gc[];
1106 };
1107 
1108 /* Generic chip callback functions */
1109 void irq_gc_noop(struct irq_data *d);
1110 void irq_gc_mask_disable_reg(struct irq_data *d);
1111 void irq_gc_mask_set_bit(struct irq_data *d);
1112 void irq_gc_mask_clr_bit(struct irq_data *d);
1113 void irq_gc_unmask_enable_reg(struct irq_data *d);
1114 void irq_gc_ack_set_bit(struct irq_data *d);
1115 void irq_gc_ack_clr_bit(struct irq_data *d);
1116 void irq_gc_mask_disable_and_ack_set(struct irq_data *d);
1117 void irq_gc_eoi(struct irq_data *d);
1118 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
1119 
1120 /* Setup functions for irq_chip_generic */
1121 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
1122 			 irq_hw_number_t hw_irq);
1123 struct irq_chip_generic *
1124 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
1125 		       void __iomem *reg_base, irq_flow_handler_t handler);
1126 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1127 			    enum irq_gc_flags flags, unsigned int clr,
1128 			    unsigned int set);
1129 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
1130 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1131 			     unsigned int clr, unsigned int set);
1132 
1133 struct irq_chip_generic *
1134 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1135 			    unsigned int irq_base, void __iomem *reg_base,
1136 			    irq_flow_handler_t handler);
1137 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1138 				u32 msk, enum irq_gc_flags flags,
1139 				unsigned int clr, unsigned int set);
1140 
1141 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
1142 
1143 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1144 				     int num_ct, const char *name,
1145 				     irq_flow_handler_t handler,
1146 				     unsigned int clr, unsigned int set,
1147 				     enum irq_gc_flags flags);
1148 
1149 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,	\
1150 				       handler,	clr, set, flags)	\
1151 ({									\
1152 	MAYBE_BUILD_BUG_ON(irqs_per_chip > 32);				\
1153 	__irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1154 					 handler, clr, set, flags);	\
1155 })
1156 
irq_free_generic_chip(struct irq_chip_generic * gc)1157 static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1158 {
1159 	kfree(gc);
1160 }
1161 
irq_destroy_generic_chip(struct irq_chip_generic * gc,u32 msk,unsigned int clr,unsigned int set)1162 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1163 					    u32 msk, unsigned int clr,
1164 					    unsigned int set)
1165 {
1166 	irq_remove_generic_chip(gc, msk, clr, set);
1167 	irq_free_generic_chip(gc);
1168 }
1169 
irq_data_get_chip_type(struct irq_data * d)1170 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1171 {
1172 	return container_of(d->chip, struct irq_chip_type, chip);
1173 }
1174 
1175 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1176 
1177 #ifdef CONFIG_SMP
irq_gc_lock(struct irq_chip_generic * gc)1178 static inline void irq_gc_lock(struct irq_chip_generic *gc)
1179 {
1180 	raw_spin_lock(&gc->lock);
1181 }
1182 
irq_gc_unlock(struct irq_chip_generic * gc)1183 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
1184 {
1185 	raw_spin_unlock(&gc->lock);
1186 }
1187 #else
irq_gc_lock(struct irq_chip_generic * gc)1188 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
irq_gc_unlock(struct irq_chip_generic * gc)1189 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
1190 #endif
1191 
1192 /*
1193  * The irqsave variants are for usage in non interrupt code. Do not use
1194  * them in irq_chip callbacks. Use irq_gc_lock() instead.
1195  */
1196 #define irq_gc_lock_irqsave(gc, flags)	\
1197 	raw_spin_lock_irqsave(&(gc)->lock, flags)
1198 
1199 #define irq_gc_unlock_irqrestore(gc, flags)	\
1200 	raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1201 
irq_reg_writel(struct irq_chip_generic * gc,u32 val,int reg_offset)1202 static inline void irq_reg_writel(struct irq_chip_generic *gc,
1203 				  u32 val, int reg_offset)
1204 {
1205 	if (gc->reg_writel)
1206 		gc->reg_writel(val, gc->reg_base + reg_offset);
1207 	else
1208 		writel(val, gc->reg_base + reg_offset);
1209 }
1210 
irq_reg_readl(struct irq_chip_generic * gc,int reg_offset)1211 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1212 				int reg_offset)
1213 {
1214 	if (gc->reg_readl)
1215 		return gc->reg_readl(gc->reg_base + reg_offset);
1216 	else
1217 		return readl(gc->reg_base + reg_offset);
1218 }
1219 
1220 struct irq_matrix;
1221 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
1222 				    unsigned int alloc_start,
1223 				    unsigned int alloc_end);
1224 void irq_matrix_online(struct irq_matrix *m);
1225 void irq_matrix_offline(struct irq_matrix *m);
1226 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace);
1227 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk);
1228 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk);
1229 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk,
1230 				unsigned int *mapped_cpu);
1231 void irq_matrix_reserve(struct irq_matrix *m);
1232 void irq_matrix_remove_reserved(struct irq_matrix *m);
1233 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk,
1234 		     bool reserved, unsigned int *mapped_cpu);
1235 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
1236 		     unsigned int bit, bool managed);
1237 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit);
1238 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown);
1239 unsigned int irq_matrix_allocated(struct irq_matrix *m);
1240 unsigned int irq_matrix_reserved(struct irq_matrix *m);
1241 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind);
1242 
1243 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1244 #define INVALID_HWIRQ	(~0UL)
1245 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1246 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1247 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1248 int ipi_send_single(unsigned int virq, unsigned int cpu);
1249 int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1250 
1251 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1252 /*
1253  * Registers a generic IRQ handling function as the top-level IRQ handler in
1254  * the system, which is generally the first C code called from an assembly
1255  * architecture-specific interrupt handler.
1256  *
1257  * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1258  * registered.
1259  */
1260 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *));
1261 
1262 /*
1263  * Allows interrupt handlers to find the irqchip that's been registered as the
1264  * top-level IRQ handler.
1265  */
1266 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init;
1267 asmlinkage void generic_handle_arch_irq(struct pt_regs *regs);
1268 #else
1269 #ifndef set_handle_irq
1270 #define set_handle_irq(handle_irq)		\
1271 	do {					\
1272 		(void)handle_irq;		\
1273 		WARN_ON(1);			\
1274 	} while (0)
1275 #endif
1276 #endif
1277 
1278 #endif /* _LINUX_IRQ_H */
1279