1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 11 /* Make stacks aligned to data cache line length */ 12 #define STACK_ALIGNMENT 32 13 14 /* SoC interface registers base address ranges */ 15 #define APB1_BASE 0x40000000 16 #define APB1_SIZE 0x0001d000 17 #define APB2_BASE 0x44000000 18 #define APB2_SIZE 0x00014000 19 #define APB3_BASE 0x50020000 20 #define APB3_SIZE 0x0000b000 21 #define APB4_BASE 0x5a000000 22 #define APB4_SIZE 0x00008000 23 #define APB5_BASE 0x5c000000 24 #define APB5_SIZE 0x0000b000 25 26 #define AHB4_BASE 0x50000000 27 #define AHB4_SIZE 0x00020000 28 #define AHB5_BASE 0x54000000 29 #define AHB5_SIZE 0x00005000 30 31 /* SoC interface registers base address */ 32 #define BSEC_BASE 0x5c005000 33 #define ETZPC_BASE 0x5c007000 34 #define CRYP1_BASE 0x54001000 35 #define DDR_BASE 0xc0000000ul 36 #define GIC_BASE 0xa0021000ul 37 #define GPIOA_BASE 0x50002000 38 #define GPIOB_BASE 0x50003000 39 #define GPIOC_BASE 0x50004000 40 #define GPIOD_BASE 0x50005000 41 #define GPIOE_BASE 0x50006000 42 #define GPIOF_BASE 0x50007000 43 #define GPIOG_BASE 0x50008000 44 #define GPIOH_BASE 0x50009000 45 #define GPIOI_BASE 0x5000a000 46 #define GPIOJ_BASE 0x5000b000 47 #define GPIOK_BASE 0x5000c000 48 #define GPIOZ_BASE 0x54004000 49 #define HASH1_BASE 0x54002000 50 #define I2C4_BASE 0x5c002000 51 #define I2C6_BASE 0x5c009000 52 #define IWDG1_BASE 0x5c003000 53 #define IWDG2_BASE 0x5a002000 54 #define PWR_BASE 0x50001000 55 #define RCC_BASE 0x50000000 56 #define RNG1_BASE 0x54003000 57 #define RTC_BASE 0x5c004000 58 #define SPI6_BASE 0x5c001000 59 #define SYSCFG_BASE 0x50020000 60 #define SYSRAM_BASE 0x2ffc0000 61 #define TAMP_BASE 0x5c00a000 62 #define TZC_BASE 0x5c006000 63 #define UART1_BASE 0x5c000000 64 #define UART2_BASE 0x4000e000 65 #define UART3_BASE 0x4000f000 66 #define UART4_BASE 0x40010000 67 #define UART5_BASE 0x40011000 68 #define UART6_BASE 0x44003000 69 #define UART7_BASE 0x40018000 70 #define UART8_BASE 0x40019000 71 72 /* Console configuration */ 73 #define STM32MP1_DEBUG_USART_BASE UART4_BASE 74 #define GIC_SPI_UART4 84 75 76 #define CONSOLE_UART_BASE STM32MP1_DEBUG_USART_BASE 77 #define CONSOLE_UART_SIZE 1024 78 79 /* BSEC OTP resources */ 80 #define STM32MP1_OTP_MAX_ID 0x5FU 81 #define STM32MP1_UPPER_OTP_START 0x20U 82 83 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 84 85 #define DATA0_OTP 0 86 #define PART_NUMBER_OTP 1 87 #define MONOTONIC_OTP 4 88 #define NAND_OTP 9 89 #define UID0_OTP 13 90 #define UID1_OTP 14 91 #define UID2_OTP 15 92 #define HW2_OTP 18 93 94 #define DATA0_OTP_SECURED_POS 6 95 96 /* GIC resources */ 97 #define GIC_SIZE 0x2000 98 #define GICC_OFFSET 0x1000 99 #define GICD_OFFSET 0x0000 100 101 #define GIC_NON_SEC_SGI_0 0 102 #define GIC_SEC_SGI_0 8 103 #define GIC_SEC_SGI_1 9 104 105 #define TARGET_CPU0_GIC_MASK BIT(0) 106 #define TARGET_CPU1_GIC_MASK BIT(1) 107 #define TARGET_CPUS_GIC_MASK GENMASK_32(CFG_TEE_CORE_NB_CORE - 1, 0) 108 109 /* 110 * GPIO banks: 11 non secure banks (A to K) and 1 secure bank (Z) 111 * Bank register's base address is computed from the bank ID listed here. 112 */ 113 #define GPIOS_NSEC_COUNT 11 114 #define GPIOS_NSEC_BASE GPIOA_BASE 115 #define GPIOS_NSEC_SIZE (GPIOS_NSEC_COUNT * SMALL_PAGE_SIZE) 116 117 #define STM32MP1_GPIOZ_MAX_COUNT 1 118 #define STM32MP1_GPIOZ_PIN_MAX_COUNT 8 119 120 #define GPIO_BANK_OFFSET 0x1000U 121 122 /* Bank IDs used in GPIO driver API */ 123 #define GPIO_BANK_A 0U 124 #define GPIO_BANK_B 1U 125 #define GPIO_BANK_C 2U 126 #define GPIO_BANK_D 3U 127 #define GPIO_BANK_E 4U 128 #define GPIO_BANK_F 5U 129 #define GPIO_BANK_G 6U 130 #define GPIO_BANK_H 7U 131 #define GPIO_BANK_I 8U 132 #define GPIO_BANK_J 9U 133 #define GPIO_BANK_K 10U 134 #define GPIO_BANK_Z 25U 135 136 /* TAMP resources */ 137 #define TAMP_BKP_REGISTER_OFF 0x100 138 139 /* TZC resources */ 140 #define STM32MP1_IRQ_TZC 36 141 142 #define STM32MP1_TZC_A7_ID 0 143 #define STM32MP1_TZC_M4_ID 1 144 #define STM32MP1_TZC_LCD_ID 3 145 #define STM32MP1_TZC_GPU_ID 4 146 #define STM32MP1_TZC_MDMA_ID 5 147 #define STM32MP1_TZC_DMA_ID 6 148 #define STM32MP1_TZC_USB_HOST_ID 7 149 #define STM32MP1_TZC_USB_OTG_ID 8 150 #define STM32MP1_TZC_SDMMC_ID 9 151 #define STM32MP1_TZC_ETH_ID 10 152 #define STM32MP1_TZC_DAP_ID 15 153 154 /* USART/UART resources */ 155 #define USART1_BASE UART1_BASE 156 #define USART2_BASE UART2_BASE 157 #define USART3_BASE UART3_BASE 158 #define USART6_BASE UART6_BASE 159 160 /* SYSRAM layout */ 161 #define SYSRAM_SIZE 0x40000 162 #define SYSRAM_NS_SIZE (SYSRAM_SIZE - SYSRAM_SEC_SIZE) 163 164 /* Non-secure SYSRAM must be above (higher addresses) secure SYSRAM */ 165 #if (CFG_STM32MP1_SCMI_SHM_BASE >= SYSRAM_BASE) && \ 166 ((CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) <= \ 167 (SYSRAM_BASE + SYSRAM_SIZE)) 168 #define SYSRAM_SEC_SIZE (CFG_STM32MP1_SCMI_SHM_BASE - SYSRAM_BASE) 169 #else 170 #define SYSRAM_SEC_SIZE SYSRAM_SIZE 171 #endif 172 173 #endif /*PLATFORM_CONFIG_H*/ 174