1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle
7 */
8 #ifndef __ASM_JAZZ_H
9 #define __ASM_JAZZ_H
10
11 /*
12 * The addresses below are virtual address. The mappings are
13 * created on startup via wired entries in the tlb. The Mips
14 * Magnum R3000 and R4000 machines are similar in many aspects,
15 * but many hardware register are accessible at 0xb9000000 in
16 * instead of 0xe0000000.
17 */
18
19 #define JAZZ_LOCAL_IO_SPACE 0xe0000000
20
21 /*
22 * Revision numbers in PICA_ASIC_REVISION
23 *
24 * 0xf0000000 - Rev1
25 * 0xf0000001 - Rev2
26 * 0xf0000002 - Rev3
27 */
28 #define PICA_ASIC_REVISION 0xe0000008
29
30 /*
31 * The segments of the seven segment LED are mapped
32 * to the control bits as follows:
33 *
34 * (7)
35 * ---------
36 * | |
37 * (2) | | (6)
38 * | (1) |
39 * ---------
40 * | |
41 * (3) | | (5)
42 * | (4) |
43 * --------- . (0)
44 */
45 #define PICA_LED 0xe000f000
46
47 /*
48 * Some characters for the LED control registers
49 * The original Mips machines seem to have a LED display
50 * with integrated decoder while the Acer machines can
51 * control each of the seven segments and the dot independently.
52 * It's only a toy, anyway...
53 */
54 #define LED_DOT 0x01
55 #define LED_SPACE 0x00
56 #define LED_0 0xfc
57 #define LED_1 0x60
58 #define LED_2 0xda
59 #define LED_3 0xf2
60 #define LED_4 0x66
61 #define LED_5 0xb6
62 #define LED_6 0xbe
63 #define LED_7 0xe0
64 #define LED_8 0xfe
65 #define LED_9 0xf6
66 #define LED_A 0xee
67 #define LED_b 0x3e
68 #define LED_C 0x9c
69 #define LED_d 0x7a
70 #define LED_E 0x9e
71 #define LED_F 0x8e
72
73 #ifndef __ASSEMBLY__
74
pica_set_led(unsigned int bits)75 static __inline__ void pica_set_led(unsigned int bits)
76 {
77 volatile unsigned int *led_register = (unsigned int *) PICA_LED;
78
79 *led_register = bits;
80 }
81
82 #endif /* !__ASSEMBLY__ */
83
84 /*
85 * Base address of the Sonic Ethernet adapter in Jazz machines.
86 */
87 #define JAZZ_ETHERNET_BASE 0xe0001000
88
89 /*
90 * Base address of the 53C94 SCSI hostadapter in Jazz machines.
91 */
92 #define JAZZ_SCSI_BASE 0xe0002000
93
94 /*
95 * i8042 keyboard controller for JAZZ and PICA chipsets.
96 * This address is just a guess and seems to differ from
97 * other mips machines such as RC3xxx...
98 */
99 #define JAZZ_KEYBOARD_ADDRESS 0xe0005000
100 #define JAZZ_KEYBOARD_DATA 0xe0005000
101 #define JAZZ_KEYBOARD_COMMAND 0xe0005001
102
103 #ifndef __ASSEMBLY__
104
105 typedef struct {
106 unsigned char data;
107 unsigned char command;
108 } jazz_keyboard_hardware;
109
110 #define jazz_kh ((keyboard_hardware *) JAZZ_KEYBOARD_ADDRESS)
111
112 typedef struct {
113 unsigned char pad0[3];
114 unsigned char data;
115 unsigned char pad1[3];
116 unsigned char command;
117 } mips_keyboard_hardware;
118
119 /*
120 * For now. Needs to be changed for RC3xxx support. See below.
121 */
122 #define keyboard_hardware jazz_keyboard_hardware
123
124 #endif /* !__ASSEMBLY__ */
125
126 /*
127 * i8042 keyboard controller for most other Mips machines.
128 */
129 #define MIPS_KEYBOARD_ADDRESS 0xb9005000
130 #define MIPS_KEYBOARD_DATA 0xb9005003
131 #define MIPS_KEYBOARD_COMMAND 0xb9005007
132
133 /*
134 * Serial and parallel ports (WD 16C552) on the Mips JAZZ
135 */
136 #define JAZZ_SERIAL1_BASE (unsigned int)0xe0006000
137 #define JAZZ_SERIAL2_BASE (unsigned int)0xe0007000
138 #define JAZZ_PARALLEL_BASE (unsigned int)0xe0008000
139
140 /*
141 * Dummy Device Address. Used in jazzdma.c
142 */
143 #define JAZZ_DUMMY_DEVICE 0xe000d000
144
145 /*
146 * JAZZ timer registers and interrupt no.
147 * Note that the hardware timer interrupt is actually on
148 * cpu level 6, but to keep compatibility with PC stuff
149 * it is remapped to vector 0. See arch/mips/kernel/entry.S.
150 */
151 #define JAZZ_TIMER_INTERVAL 0xe0000228
152 #define JAZZ_TIMER_REGISTER 0xe0000230
153
154 /*
155 * DRAM configuration register
156 */
157 #ifndef __ASSEMBLY__
158 #ifdef __MIPSEL__
159 typedef struct {
160 unsigned int bank2 : 3;
161 unsigned int bank1 : 3;
162 unsigned int mem_bus_width : 1;
163 unsigned int reserved2 : 1;
164 unsigned int page_mode : 1;
165 unsigned int reserved1 : 23;
166 } dram_configuration;
167 #else /* defined (__MIPSEB__) */
168 typedef struct {
169 unsigned int reserved1 : 23;
170 unsigned int page_mode : 1;
171 unsigned int reserved2 : 1;
172 unsigned int mem_bus_width : 1;
173 unsigned int bank1 : 3;
174 unsigned int bank2 : 3;
175 } dram_configuration;
176 #endif
177 #endif /* !__ASSEMBLY__ */
178
179 #define PICA_DRAM_CONFIG 0xe00fffe0
180
181 /*
182 * JAZZ interrupt control registers
183 */
184 #define JAZZ_IO_IRQ_SOURCE 0xe0010000
185 #define JAZZ_IO_IRQ_ENABLE 0xe0010002
186
187 /*
188 * JAZZ Interrupt Level definitions
189 *
190 * This is somewhat broken. For reasons which nobody can remember anymore
191 * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
192 */
193 #define JAZZ_IRQ_START 24
194 #define JAZZ_IRQ_END (24 + 9)
195 #define JAZZ_PARALLEL_IRQ (JAZZ_IRQ_START + 0)
196 #define JAZZ_FLOPPY_IRQ (JAZZ_IRQ_START + 1)
197 #define JAZZ_SOUND_IRQ (JAZZ_IRQ_START + 2)
198 #define JAZZ_VIDEO_IRQ (JAZZ_IRQ_START + 3)
199 #define JAZZ_ETHERNET_IRQ (JAZZ_IRQ_START + 4)
200 #define JAZZ_SCSI_IRQ (JAZZ_IRQ_START + 5)
201 #define JAZZ_KEYBOARD_IRQ (JAZZ_IRQ_START + 6)
202 #define JAZZ_MOUSE_IRQ (JAZZ_IRQ_START + 7)
203 #define JAZZ_SERIAL1_IRQ (JAZZ_IRQ_START + 8)
204 #define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9)
205
206 #define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6)
207
208
209 /*
210 * JAZZ DMA Channels
211 * Note: Channels 4...7 are not used with respect to the Acer PICA-61
212 * chipset which does not provide these DMA channels.
213 */
214 #define JAZZ_SCSI_DMA 0 /* SCSI */
215 #define JAZZ_FLOPPY_DMA 1 /* FLOPPY */
216 #define JAZZ_AUDIOL_DMA 2 /* AUDIO L */
217 #define JAZZ_AUDIOR_DMA 3 /* AUDIO R */
218
219 /*
220 * JAZZ R4030 MCT_ADR chip (DMA controller)
221 * Note: Virtual Addresses !
222 */
223 #define JAZZ_R4030_CONFIG 0xE0000000 /* R4030 config register */
224 #define JAZZ_R4030_REVISION 0xE0000008 /* same as PICA_ASIC_REVISION */
225 #define JAZZ_R4030_INV_ADDR 0xE0000010 /* Invalid Address register */
226
227 #define JAZZ_R4030_TRSTBL_BASE 0xE0000018 /* Translation Table Base */
228 #define JAZZ_R4030_TRSTBL_LIM 0xE0000020 /* Translation Table Limit */
229 #define JAZZ_R4030_TRSTBL_INV 0xE0000028 /* Translation Table Invalidate */
230
231 #define JAZZ_R4030_CACHE_MTNC 0xE0000030 /* Cache Maintenance */
232 #define JAZZ_R4030_R_FAIL_ADDR 0xE0000038 /* Remote Failed Address */
233 #define JAZZ_R4030_M_FAIL_ADDR 0xE0000040 /* Memory Failed Address */
234
235 #define JAZZ_R4030_CACHE_PTAG 0xE0000048 /* I/O Cache Physical Tag */
236 #define JAZZ_R4030_CACHE_LTAG 0xE0000050 /* I/O Cache Logical Tag */
237 #define JAZZ_R4030_CACHE_BMASK 0xE0000058 /* I/O Cache Byte Mask */
238 #define JAZZ_R4030_CACHE_BWIN 0xE0000060 /* I/O Cache Buffer Window */
239
240 /*
241 * Remote Speed Registers.
242 *
243 * 0: free, 1: Ethernet, 2: SCSI, 3: Floppy,
244 * 4: RTC, 5: Kb./Mouse 6: serial 1, 7: serial 2,
245 * 8: parallel, 9: NVRAM, 10: CPU, 11: PROM,
246 * 12: reserved, 13: free, 14: 7seg LED, 15: ???
247 */
248 #define JAZZ_R4030_REM_SPEED 0xE0000070 /* 16 Remote Speed Registers */
249 /* 0xE0000070,78,80... 0xE00000E8 */
250 #define JAZZ_R4030_IRQ_ENABLE 0xE00000E8 /* Internal Interrupt Enable */
251 #define JAZZ_R4030_INVAL_ADDR 0xE0000010 /* Invalid address Register */
252 #define JAZZ_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Register */
253 #define JAZZ_R4030_I386_ERROR 0xE0000208 /* i386/EISA Bus Error */
254
255 /*
256 * Virtual (E)ISA controller address
257 */
258 #define JAZZ_EISA_IRQ_ACK 0xE0000238 /* EISA interrupt acknowledge */
259
260 /*
261 * Access the R4030 DMA and I/O Controller
262 */
263 #ifndef __ASSEMBLY__
264
r4030_delay(void)265 static inline void r4030_delay(void)
266 {
267 __asm__ __volatile__(
268 ".set\tnoreorder\n\t"
269 "nop\n\t"
270 "nop\n\t"
271 "nop\n\t"
272 "nop\n\t"
273 ".set\treorder");
274 }
275
r4030_read_reg16(unsigned long addr)276 static inline unsigned short r4030_read_reg16(unsigned long addr)
277 {
278 unsigned short ret = *((volatile unsigned short *)addr);
279 r4030_delay();
280 return ret;
281 }
282
r4030_read_reg32(unsigned long addr)283 static inline unsigned int r4030_read_reg32(unsigned long addr)
284 {
285 unsigned int ret = *((volatile unsigned int *)addr);
286 r4030_delay();
287 return ret;
288 }
289
r4030_write_reg16(unsigned long addr,unsigned val)290 static inline void r4030_write_reg16(unsigned long addr, unsigned val)
291 {
292 *((volatile unsigned short *)addr) = val;
293 r4030_delay();
294 }
295
r4030_write_reg32(unsigned long addr,unsigned val)296 static inline void r4030_write_reg32(unsigned long addr, unsigned val)
297 {
298 *((volatile unsigned int *)addr) = val;
299 r4030_delay();
300 }
301
302 #endif /* !__ASSEMBLY__ */
303
304 #define JAZZ_FDC_BASE 0xe0003000
305 #define JAZZ_RTC_BASE 0xe0004000
306 #define JAZZ_PORT_BASE 0xe2000000
307
308 #define JAZZ_EISA_BASE 0xe3000000
309
310 #endif /* __ASM_JAZZ_H */
311