1 /* 2 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef JUNO_DEF_H 8 #define JUNO_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /****************************************************************************** 13 * Definition of platform soc id 14 *****************************************************************************/ 15 #define JUNO_SOC_ID 1 16 17 /******************************************************************************* 18 * Juno memory map related constants 19 ******************************************************************************/ 20 21 /* Board revisions */ 22 #define REV_JUNO_R0 U(0x1) /* Rev B */ 23 #define REV_JUNO_R1 U(0x2) /* Rev C */ 24 #define REV_JUNO_R2 U(0x3) /* Rev D */ 25 26 /* Bypass offset from start of NOR flash */ 27 #define BL1_ROM_BYPASS_OFFSET UL(0x03EC0000) 28 29 #define EMMC_BASE UL(0x0c000000) 30 #define EMMC_SIZE UL(0x04000000) 31 32 #define PSRAM_BASE UL(0x14000000) 33 #define PSRAM_SIZE UL(0x02000000) 34 35 #define JUNO_SSC_VER_PART_NUM U(0x030) 36 37 /******************************************************************************* 38 * Juno topology related constants 39 ******************************************************************************/ 40 #define JUNO_CLUSTER_COUNT U(2) 41 #define JUNO_CLUSTER0_CORE_COUNT U(2) 42 #define JUNO_CLUSTER1_CORE_COUNT U(4) 43 44 /******************************************************************************* 45 * TZC-400 related constants 46 ******************************************************************************/ 47 #define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ 48 #define TZC400_NSAID_PCIE 1 49 #define TZC400_NSAID_HDLCD0 2 50 #define TZC400_NSAID_HDLCD1 3 51 #define TZC400_NSAID_USB 4 52 #define TZC400_NSAID_DMA330 5 53 #define TZC400_NSAID_THINLINKS 6 54 #define TZC400_NSAID_AP 9 55 #define TZC400_NSAID_GPU 10 56 #define TZC400_NSAID_SCP 11 57 #define TZC400_NSAID_CORESIGHT 12 58 59 /******************************************************************************* 60 * TRNG related constants 61 ******************************************************************************/ 62 #define TRNG_BASE UL(0x7FE60000) 63 #define TRNG_NOUTPUTS 4 64 #define TRNG_STATUS UL(0x10) 65 #define TRNG_INTMASK UL(0x14) 66 #define TRNG_CONFIG UL(0x18) 67 #define TRNG_CONTROL UL(0x1C) 68 #define TRNG_NBYTES 16 /* Number of bytes generated per round. */ 69 70 /******************************************************************************* 71 * MMU-401 related constants 72 ******************************************************************************/ 73 #define MMU401_SSD_OFFSET UL(0x4000) 74 #define MMU401_DMA330_BASE UL(0x7fb00000) 75 76 /******************************************************************************* 77 * Interrupt handling constants 78 ******************************************************************************/ 79 #define JUNO_IRQ_DMA_SMMU 126 80 #define JUNO_IRQ_HDLCD0_SMMU 128 81 #define JUNO_IRQ_HDLCD1_SMMU 130 82 #define JUNO_IRQ_USB_SMMU 132 83 #define JUNO_IRQ_THIN_LINKS_SMMU 134 84 #define JUNO_IRQ_SEC_I2C 137 85 #define JUNO_IRQ_GPU_SMMU_1 73 86 #define JUNO_IRQ_ETR_SMMU 75 87 88 /******************************************************************************* 89 * Memprotect definitions 90 ******************************************************************************/ 91 /* PSCI memory protect definitions: 92 * This variable is stored in a non-secure flash because some ARM reference 93 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 94 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 95 */ 96 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 97 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 98 99 #endif /* JUNO_DEF_H */ 100