1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_LINK_DP_H__ 27 #define __DC_LINK_DP_H__ 28 29 #define LINK_TRAINING_ATTEMPTS 4 30 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ 31 #define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/ 32 #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/ 33 #define MAX_MTP_SLOT_COUNT 64 34 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 35 #define TRAINING_AUX_RD_INTERVAL 100 //us 36 37 struct dc_link; 38 struct dc_stream_state; 39 struct dc_link_settings; 40 41 enum { 42 LINK_TRAINING_MAX_RETRY_COUNT = 5, 43 /* to avoid infinite loop where-in the receiver 44 * switches between different VS 45 */ 46 LINK_TRAINING_MAX_CR_RETRY = 100, 47 /* 48 * Some receivers fail to train on first try and are good 49 * on subsequent tries. 2 retries should be plenty. If we 50 * don't have a successful training then we don't expect to 51 * ever get one. 52 */ 53 LINK_TRAINING_MAX_VERIFY_RETRY = 2, 54 PEAK_FACTOR_X1000 = 1006, 55 }; 56 57 bool dp_verify_link_cap( 58 struct dc_link *link, 59 struct dc_link_settings *known_limit_link_setting, 60 int *fail_count); 61 62 bool dp_verify_link_cap_with_retries( 63 struct dc_link *link, 64 struct dc_link_settings *known_limit_link_setting, 65 int attempts); 66 67 bool dp_verify_mst_link_cap( 68 struct dc_link *link); 69 70 bool dp_validate_mode_timing( 71 struct dc_link *link, 72 const struct dc_crtc_timing *timing); 73 74 bool decide_edp_link_settings(struct dc_link *link, 75 struct dc_link_settings *link_setting, 76 uint32_t req_bw); 77 78 void decide_link_settings( 79 struct dc_stream_state *stream, 80 struct dc_link_settings *link_setting); 81 82 bool perform_link_training_with_retries( 83 const struct dc_link_settings *link_setting, 84 bool skip_video_pattern, 85 int attempts, 86 struct pipe_ctx *pipe_ctx, 87 enum signal_type signal, 88 bool do_fallback); 89 90 bool hpd_rx_irq_check_link_loss_status( 91 struct dc_link *link, 92 union hpd_irq_data *hpd_irq_dpcd_data); 93 94 bool is_mst_supported(struct dc_link *link); 95 96 bool detect_dp_sink_caps(struct dc_link *link); 97 98 void detect_edp_sink_caps(struct dc_link *link); 99 100 bool is_dp_active_dongle(const struct dc_link *link); 101 102 bool is_dp_branch_device(const struct dc_link *link); 103 104 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing); 105 106 void dp_enable_mst_on_sink(struct dc_link *link, bool enable); 107 108 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link); 109 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode); 110 111 bool dp_overwrite_extended_receiver_cap(struct dc_link *link); 112 113 void dpcd_set_source_specific_data(struct dc_link *link); 114 /* Write DPCD link configuration data. */ 115 enum dc_status dpcd_set_link_settings( 116 struct dc_link *link, 117 const struct link_training_settings *lt_settings); 118 /* Write DPCD drive settings. */ 119 enum dc_status dpcd_set_lane_settings( 120 struct dc_link *link, 121 const struct link_training_settings *link_training_setting, 122 uint32_t offset); 123 /* Read training status and adjustment requests from DPCD. */ 124 enum dc_status dp_get_lane_status_and_lane_adjust( 125 struct dc_link *link, 126 const struct link_training_settings *link_training_setting, 127 union lane_status ln_status[LANE_COUNT_DP_MAX], 128 union lane_align_status_updated *ln_align, 129 union lane_adjust ln_adjust[LANE_COUNT_DP_MAX], 130 uint32_t offset); 131 132 void dp_wait_for_training_aux_rd_interval( 133 struct dc_link *link, 134 uint32_t wait_in_micro_secs); 135 136 bool dp_is_cr_done(enum dc_lane_count ln_count, 137 union lane_status *dpcd_lane_status); 138 139 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count, 140 union lane_status *dpcd_lane_status); 141 142 bool dp_is_ch_eq_done(enum dc_lane_count ln_count, 143 union lane_status *dpcd_lane_status); 144 bool dp_is_symbol_locked(enum dc_lane_count ln_count, 145 union lane_status *dpcd_lane_status); 146 bool dp_is_interlane_aligned(union lane_align_status_updated align_status); 147 148 bool dp_is_max_vs_reached( 149 const struct link_training_settings *lt_settings); 150 void dp_hw_to_dpcd_lane_settings( 151 const struct link_training_settings *lt_settings, 152 const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX], 153 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]); 154 void dp_decide_lane_settings( 155 const struct link_training_settings *lt_settings, 156 const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX], 157 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX], 158 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]); 159 160 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval); 161 162 enum dpcd_training_patterns 163 dc_dp_training_pattern_to_dpcd_training_pattern( 164 struct dc_link *link, 165 enum dc_dp_training_pattern pattern); 166 167 uint8_t dc_dp_initialize_scrambling_data_symbols( 168 struct dc_link *link, 169 enum dc_dp_training_pattern pattern); 170 171 enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready); 172 void dp_set_fec_enable(struct dc_link *link, bool enable); 173 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable); 174 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update); 175 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable); 176 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx); 177 bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable); 178 179 /* Initialize output parameter lt_settings. */ 180 void dp_decide_training_settings( 181 struct dc_link *link, 182 const struct dc_link_settings *link_setting, 183 struct link_training_settings *lt_settings); 184 185 /* Convert PHY repeater count read from DPCD uint8_t. */ 186 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count); 187 188 /* Check DPCD training status registers to detect link loss. */ 189 enum link_training_result dp_check_link_loss_status( 190 struct dc_link *link, 191 const struct link_training_settings *link_training_setting); 192 193 enum dc_status dpcd_configure_lttpr_mode( 194 struct dc_link *link, 195 struct link_training_settings *lt_settings); 196 197 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings); 198 bool dpcd_write_128b_132b_sst_payload_allocation_table( 199 const struct dc_stream_state *stream, 200 struct dc_link *link, 201 struct link_mst_stream_allocation_table *proposed_table, 202 bool allocate); 203 204 enum dc_status dpcd_configure_channel_coding( 205 struct dc_link *link, 206 struct link_training_settings *lt_settings); 207 208 bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link); 209 210 struct fixed31_32 calculate_sst_avg_time_slots_per_mtp( 211 const struct dc_stream_state *stream, 212 const struct dc_link *link); 213 void enable_dp_hpo_output(struct dc_link *link, const struct dc_link_settings *link_settings); 214 void disable_dp_hpo_output(struct dc_link *link, enum signal_type signal); 215 void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable); 216 bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx); 217 void reset_dp_hpo_stream_encoders_for_link(struct dc_link *link); 218 219 bool dp_retrieve_lttpr_cap(struct dc_link *link); 220 #endif /* __DC_LINK_DP_H__ */ 221