1 /* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2018 Marvell International Ltd.
4 */
5
6 #ifndef __CGX_H__
7 #define __CGX_H__
8
9 #include "cgx_intf.h"
10
11 #define PCI_DEVICE_ID_OCTEONTX2_CGX 0xA059
12
13 #define MAX_LMAC_PER_CGX 4
14 #define CGX_PER_NODE 3
15
16 enum lmac_type {
17 LMAC_MODE_SGMII = 0,
18 LMAC_MODE_XAUI = 1,
19 LMAC_MODE_RXAUI = 2,
20 LMAC_MODE_10G_R = 3,
21 LMAC_MODE_40G_R = 4,
22 LMAC_MODE_QSGMII = 6,
23 LMAC_MODE_25G_R = 7,
24 LMAC_MODE_50G_R = 8,
25 LMAC_MODE_100G_R = 9,
26 LMAC_MODE_USXGMII = 10,
27 };
28
29 extern char lmac_type_to_str[][8];
30
31 extern char lmac_speed_to_str[][8];
32
33 struct lmac_priv {
34 u8 enable:1;
35 u8 full_duplex:1;
36 u8 speed:4;
37 u8 mode:1;
38 u8 rsvd:1;
39 u8 mac_addr[6];
40 };
41
42 struct cgx;
43 struct nix;
44 struct nix_af;
45
46 struct lmac {
47 struct cgx *cgx;
48 struct nix *nix;
49 char name[16];
50 enum lmac_type lmac_type;
51 bool init_pend;
52 u8 instance;
53 u8 lmac_id;
54 u8 pknd;
55 u8 link_num;
56 u32 chan_num;
57 u8 mac_addr[6];
58 };
59
60 struct cgx {
61 struct nix_af *nix_af;
62 void __iomem *reg_base;
63 struct udevice *dev;
64 struct lmac *lmac[MAX_LMAC_PER_CGX];
65 u8 cgx_id;
66 u8 lmac_count;
67 };
68
cgx_write(struct cgx * cgx,u8 lmac,u64 offset,u64 val)69 static inline void cgx_write(struct cgx *cgx, u8 lmac, u64 offset, u64 val)
70 {
71 writeq(val, cgx->reg_base + CMR_SHIFT(lmac) + offset);
72 }
73
cgx_read(struct cgx * cgx,u8 lmac,u64 offset)74 static inline u64 cgx_read(struct cgx *cgx, u8 lmac, u64 offset)
75 {
76 return readq(cgx->reg_base + CMR_SHIFT(lmac) + offset);
77 }
78
79 /**
80 * Given an LMAC/PF instance number, return the lmac
81 * Per design, each PF has only one LMAC mapped.
82 *
83 * @param instance instance to find
84 *
85 * @return pointer to lmac data structure or NULL if not found
86 */
87 struct lmac *nix_get_cgx_lmac(int lmac_instance);
88
89 int cgx_lmac_set_pkind(struct lmac *lmac, u8 lmac_id, int pkind);
90 int cgx_lmac_internal_loopback(struct lmac *lmac, int lmac_id, bool enable);
91 int cgx_lmac_rx_tx_enable(struct lmac *lmac, int lmac_id, bool enable);
92 int cgx_lmac_link_enable(struct lmac *lmac, int lmac_id, bool enable,
93 u64 *status);
94 int cgx_lmac_link_status(struct lmac *lmac, int lmac_id, u64 *status);
95 void cgx_lmac_mac_filter_setup(struct lmac *lmac);
96
97 int cgx_intf_get_link_sts(u8 cgx, u8 lmac, u64 *lnk_sts);
98 int cgx_intf_link_up_dwn(u8 cgx, u8 lmac, u8 up_dwn, u64 *lnk_sts);
99 int cgx_intf_get_mac_addr(u8 cgx, u8 lmac, u8 *mac);
100 int cgx_intf_set_macaddr(struct udevice *dev);
101 int cgx_intf_prbs(u8 qlm, u8 mode, u32 time, u8 lane);
102 int cgx_intf_display_eye(u8 qlm, u8 lane);
103 int cgx_intf_display_serdes(u8 qlm, u8 lane);
104
105 #endif /* __CGX_H__ */
106