1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> 4 * 5 */ 6 7 #ifndef _MAILBOX_S10_H_ 8 #define _MAILBOX_S10_H_ 9 10 /* user define Uboot ID */ 11 #include <linux/bitops.h> 12 #define MBOX_CLIENT_ID_UBOOT 0xB 13 #define MBOX_ID_UBOOT 0x1 14 15 #define MBOX_CMD_DIRECT 0 16 #define MBOX_CMD_INDIRECT 1 17 18 #define MBOX_MAX_CMD_INDEX 2047 19 #define MBOX_CMD_BUFFER_SIZE 32 20 #define MBOX_RESP_BUFFER_SIZE 16 21 22 #define MBOX_HDR_CMD_LSB 0 23 #define MBOX_HDR_CMD_MSK (BIT(11) - 1) 24 #define MBOX_HDR_I_LSB 11 25 #define MBOX_HDR_I_MSK BIT(11) 26 #define MBOX_HDR_LEN_LSB 12 27 #define MBOX_HDR_LEN_MSK 0x007FF000 28 #define MBOX_HDR_ID_LSB 24 29 #define MBOX_HDR_ID_MSK 0x0F000000 30 #define MBOX_HDR_CLIENT_LSB 28 31 #define MBOX_HDR_CLIENT_MSK 0xF0000000 32 33 /* Interrupt flags */ 34 #define MBOX_FLAGS_INT_COE BIT(0) /* COUT update interrupt enable */ 35 #define MBOX_FLAGS_INT_RIE BIT(1) /* RIN update interrupt enable */ 36 #define MBOX_FLAGS_INT_UAE BIT(8) /* Urgent ACK interrupt enable */ 37 #define MBOX_ALL_INTRS (MBOX_FLAGS_INT_COE | \ 38 MBOX_FLAGS_INT_RIE | \ 39 MBOX_FLAGS_INT_UAE) 40 41 /* Status */ 42 #define MBOX_STATUS_UA_MSK BIT(8) 43 44 #define MBOX_CMD_HEADER(client, id, len, indirect, cmd) \ 45 ((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \ 46 (((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \ 47 (((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \ 48 (((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK) | \ 49 (((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK)) 50 51 #define MBOX_RESP_ERR_GET(resp) \ 52 (((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB) 53 #define MBOX_RESP_LEN_GET(resp) \ 54 (((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB) 55 #define MBOX_RESP_ID_GET(resp) \ 56 (((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB) 57 #define MBOX_RESP_CLIENT_GET(resp) \ 58 (((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB) 59 60 /* Response error list */ 61 enum ALT_SDM_MBOX_RESP_CODE { 62 /* CMD completed successfully, but check resp ARGS for any errors */ 63 MBOX_RESP_STATOK = 0, 64 /* CMD is incorrectly formatted in some way */ 65 MBOX_RESP_INVALID_COMMAND = 1, 66 /* BootROM Command code not undesrtood */ 67 MBOX_RESP_UNKNOWN_BR = 2, 68 /* CMD code not recognized by firmware */ 69 MBOX_RESP_UNKNOWN = 3, 70 /* Length setting is not a valid length for this CMD type */ 71 MBOX_RESP_INVALID_LEN = 4, 72 /* Indirect setting is not valid for this CMD type */ 73 MBOX_RESP_INVALID_INDIRECT_SETTING = 5, 74 /* HW source which is not allowed to send CMD type */ 75 MBOX_RESP_CMD_INVALID_ON_SRC = 6, 76 /* Client with ID not associated with any running PR CMD tries to run 77 * RECONFIG_DATA RECONFIG_STATUS and accessing QSPI / SDMMC using ID 78 * without exclusive access 79 */ 80 MBOX_RESP_CLIENT_ID_NO_MATCH = 8, 81 /* Address provided to the system is invalid (alignment, range 82 * permission) 83 */ 84 MBOX_RESP_INVALID_ADDR = 0x9, 85 /* Signature authentication failed */ 86 MBOX_RESP_AUTH_FAIL = 0xA, 87 /* CMD timed out */ 88 MBOX_RESP_TIMEOUT = 0xB, 89 /* HW (i.e. QSPI) is not ready (initialized or configured) */ 90 MBOX_RESP_HW_NOT_RDY = 0xC, 91 /* Invalid license for IID registration */ 92 MBOX_RESP_PUF_ACCCES_FAILED = 0x80, 93 MBOX_PUF_ENROLL_DISABLE = 0x81, 94 MBOX_RESP_PUF_ENROLL_FAIL = 0x82, 95 MBOX_RESP_PUF_RAM_TEST_FAIL = 0x83, 96 MBOX_RESP_ATTEST_CERT_GEN_FAIL = 0x84, 97 /* Operation not allowed under current security settings */ 98 MBOX_RESP_NOT_ALLOWED_UNDER_SECURITY_SETTINGS = 0x85, 99 MBOX_RESP_PUF_TRNG_FAIL = 0x86, 100 MBOX_RESP_FUSE_ALREADY_BLOWN = 0x87, 101 MBOX_RESP_INVALID_SIGNATURE = 0x88, 102 MBOX_RESP_INVALID_HASH = 0x8b, 103 MBOX_RESP_INVALID_CERTIFICATE = 0x91, 104 /* Indicates that the device (FPGA or HPS) is not configured */ 105 MBOX_RESP_NOT_CONFIGURED = 0x100, 106 /* Indicates that the device is busy */ 107 MBOX_RESP_DEVICE_BUSY = 0x1FF, 108 /* Indicates that there is no valid response available */ 109 MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF, 110 /* General Error */ 111 MBOX_RESP_ERROR = 0x3FF, 112 }; 113 114 /* Mailbox command list */ 115 #define MBOX_RESTART 2 116 #define MBOX_CONFIG_STATUS 4 117 #define MBOX_RECONFIG 6 118 #define MBOX_RECONFIG_MSEL 7 119 #define MBOX_RECONFIG_DATA 8 120 #define MBOX_RECONFIG_STATUS 9 121 #define MBOX_VAB_SRC_CERT 11 122 #define MBOX_QSPI_OPEN 50 123 #define MBOX_QSPI_CLOSE 51 124 #define MBOX_QSPI_DIRECT 59 125 #define MBOX_REBOOT_HPS 71 126 127 /* Mailbox registers */ 128 #define MBOX_CIN 0 /* command valid offset */ 129 #define MBOX_ROUT 4 /* response output offset */ 130 #define MBOX_URG 8 /* urgent command */ 131 #define MBOX_FLAGS 0x0c /* interrupt enables */ 132 #define MBOX_COUT 0x20 /* command free offset */ 133 #define MBOX_RIN 0x24 /* respond valid offset */ 134 #define MBOX_STATUS 0x2c /* mailbox status */ 135 #define MBOX_CMD_BUF 0x40 /* circular command buffer */ 136 #define MBOX_RESP_BUF 0xc0 /* circular response buffer */ 137 #define MBOX_DOORBELL_TO_SDM 0x400 /* Doorbell to SDM */ 138 #define MBOX_DOORBELL_FROM_SDM 0x480 /* Doorbell from SDM */ 139 140 /* Status and bit information returned by RECONFIG_STATUS */ 141 #define RECONFIG_STATUS_RESPONSE_LEN 6 142 #define RECONFIG_STATUS_STATE 0 143 #define RECONFIG_STATUS_PIN_STATUS 2 144 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3 145 146 /* Macros for specifying number of arguments in mailbox command */ 147 #define MBOX_NUM_ARGS(n, b) (((n) & 0xFF) << (b)) 148 #define MBOX_DIRECT_COUNT(n) MBOX_NUM_ARGS((n), 0) 149 #define MBOX_ARG_DESC_COUNT(n) MBOX_NUM_ARGS((n), 8) 150 #define MBOX_RESP_DESC_COUNT(n) MBOX_NUM_ARGS((n), 16) 151 152 #define MBOX_CFGSTAT_STATE_IDLE 0x00000000 153 #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 154 #define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 155 #define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 156 #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 157 #define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 158 #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 159 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 160 #define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 161 #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 162 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 163 164 #define RCF_SOFTFUNC_STATUS_CONF_DONE BIT(0) 165 #define RCF_SOFTFUNC_STATUS_INIT_DONE BIT(1) 166 #define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) 167 #define RCF_PIN_STATUS_NSTATUS BIT(31) 168 169 int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, 170 u32 *resp_buf_len, u32 *resp_buf); 171 int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, 172 u8 urgent, u32 *resp_buf_len, u32 *resp_buf); 173 int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg); 174 int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg); 175 int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len); 176 int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len); 177 int mbox_init(void); 178 179 #ifdef CONFIG_CADENCE_QSPI 180 int mbox_qspi_close(void); 181 int mbox_qspi_open(void); 182 #endif 183 184 int mbox_reset_cold(void); 185 int mbox_get_fpga_config_status(u32 cmd); 186 int mbox_get_fpga_config_status_psci(u32 cmd); 187 #endif /* _MAILBOX_S10_H_ */ 188