1 /*
2  * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MCE_H
8 #define MCE_H
9 
10 #include <lib/mmio.h>
11 
12 #include <tegra_def.h>
13 
14 /*******************************************************************************
15  * MCE commands
16  ******************************************************************************/
17 typedef enum mce_cmd {
18 	MCE_CMD_ENTER_CSTATE = 0U,
19 	MCE_CMD_UPDATE_CSTATE_INFO = 1U,
20 	MCE_CMD_UPDATE_CROSSOVER_TIME = 2U,
21 	MCE_CMD_READ_CSTATE_STATS = 3U,
22 	MCE_CMD_WRITE_CSTATE_STATS = 4U,
23 	MCE_CMD_IS_SC7_ALLOWED = 5U,
24 	MCE_CMD_ONLINE_CORE = 6U,
25 	MCE_CMD_CC3_CTRL = 7U,
26 	MCE_CMD_ECHO_DATA = 8U,
27 	MCE_CMD_READ_VERSIONS = 9U,
28 	MCE_CMD_ENUM_FEATURES = 10U,
29 	MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11U,
30 	MCE_CMD_ENUM_READ_MCA = 12U,
31 	MCE_CMD_ENUM_WRITE_MCA = 13U,
32 	MCE_CMD_ROC_FLUSH_CACHE = 14U,
33 	MCE_CMD_ROC_CLEAN_CACHE = 15U,
34 	MCE_CMD_ENABLE_LATIC = 16U,
35 	MCE_CMD_UNCORE_PERFMON_REQ = 17U,
36 	MCE_CMD_MISC_CCPLEX = 18U,
37 	MCE_CMD_IS_CCX_ALLOWED = 0xFEU,
38 	MCE_CMD_MAX = 0xFFU,
39 } mce_cmd_t;
40 
41 #define MCE_CMD_MASK				0xFFU
42 
43 /*******************************************************************************
44  * Timeout value used to powerdown a core
45  ******************************************************************************/
46 #define MCE_CORE_SLEEP_TIME_INFINITE		0xFFFFFFFFU
47 
48 /*******************************************************************************
49  * Struct to prepare UPDATE_CSTATE_INFO request
50  ******************************************************************************/
51 typedef struct mce_cstate_info {
52 	/* cluster cstate value */
53 	uint32_t cluster;
54 	/* ccplex cstate value */
55 	uint32_t ccplex;
56 	/* system cstate value */
57 	uint32_t system;
58 	/* force system state? */
59 	uint8_t system_state_force;
60 	/* wake mask value */
61 	uint32_t wake_mask;
62 	/* update the wake mask? */
63 	uint8_t update_wake_mask;
64 } mce_cstate_info_t;
65 
66 /* public interfaces */
67 int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
68 		uint64_t arg2);
69 int mce_update_reset_vector(void);
70 int mce_update_gsc_videomem(void);
71 int mce_update_gsc_tzdram(void);
72 __dead2 void mce_enter_ccplex_state(uint32_t state_idx);
73 void mce_update_cstate_info(const mce_cstate_info_t *cstate);
74 void mce_verify_firmware_version(void);
75 
76 #endif /* MCE_H */
77